Prosecution Insights
Last updated: May 29, 2026

Agilesoda Inc.

5 pending office actions • 4 art units • 5 examiners • 0 of 5 (0%) have an AI response strategy ready • 1 patents granted in the last 365 days

Portfolio Summary

5
Total Pending OAs
5
Non-Final OAs
0
Final Rejections
0
Advisory / Quayle

Response Deadline Pressure

Based on the USPTO statutory response window for each pending office action. 5 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.

3
Overdue
0
Due this week
2
Due this month
0
Due in next 60 days
0
Due later

Deadline Fire Line

Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 5 of the docket's apps have a known mailing date.

-30dToday30d60d90d120d
Overdue (3)Due ≤ 30 days (2)

Case Difficulty Mix

Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.

0
Hard (0%)
3
Medium (60%)
2
Easy (40%)
0
Unknown (0%)

Rejection Statute Mix

BucketCases
§103 only2 (40%)
§102 only1 (20%)
§112 only2 (40%)

Industry Mix

How the docket's pending cases split across USPTO tech-center bands.

0
Life Sciences
0% of docket
4
Information Tech
80% of docket
0
Communications
0% of docket
1
Semiconductors
20% of docket
0
Mechanical / Eng
0% of docket
0
Business / Other
0% of docket

Time-on-OA Estimate

Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.

50 h
Manual time on pending OAs
10 h
Time saved (low, 20%)
18 h
Time saved (mid, 35%)
0.4 wks
FTE-weeks freed (mid)

Top Examiners on this docket

ExaminerApps on this docketAllow rateInterview lift
LIN, ARIC 1 60.0% +12.9%
DRAPEAU, SIMEON PAUL 1 12.5% +50.0%
LU, HWEI-MIN 1 62.6% +40.5%
STOICA, ADRIAN 1 68.0% +30.6%
GAN, CHUEN-MEEI 1 81.6% +41.5%

Quick Wins (1)

Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 1 ordered by deadline are shown.

App #TitleExaminerDue in
17878482 REINFORCEMENT LEARNING APPARATUS AND METHOD BASED ON USER LEARNING ENVIRONMENT GAN, CHUEN-MEEI 97d overdue

Hard Cases (1)

Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 1 ordered by deadline are shown.

App #TitleExaminerDue in
18082823 APPARATUS AND METHOD FOR REINFORCEMENT LEARNING FOR OBJECT POSITION OPTIMIZATION BASED ON SEMICONDUCTOR DESIGN DATA DRAPEAU, SIMEON PAUL 21d

Interview Candidates (5)

Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 5 ordered by deadline are shown.

App #TitleExaminerDue in
17878451 REINFORCEMENT LEARNING APPARATUS AND REINFORCEMENT LEARNING METHOD FOR OPTIMIZING POSITION OF OBJECT BASED ON DESIGN DATA STOICA, ADRIAN 155d overdue
18074749 APPARATUS AND METHOD FOR REINFORCEMENT LEARNING BASED ON USER LEARNING ENVIRONMENT IN SEMICONDUCTOR DESIGN LU, HWEI-MIN 147d overdue
17878482 REINFORCEMENT LEARNING APPARATUS AND METHOD BASED ON USER LEARNING ENVIRONMENT GAN, CHUEN-MEEI 97d overdue
18296440 DEEP REINFORCEMENT LEARNING-BASED INTEGRATED CIRCUIT DESIGN SYSTEM USING PARTITIONING AND DEEP REINFORCEMENT LEARNING-BASED INTEGRATED CIRCUIT DESIGN METHOD USING PARTITIONING LIN, ARIC 21d
18082823 APPARATUS AND METHOD FOR REINFORCEMENT LEARNING FOR OBJECT POSITION OPTIMIZATION BASED ON SEMICONDUCTOR DESIGN DATA DRAPEAU, SIMEON PAUL 21d

Top Art Units

Art UnitApps
2188 2
2851 1
2142 1
2189 1

Pending Office Actions

App #TitleExaminerArt UnitStatutesStatusDue inAIFiled
18296440 DEEP REINFORCEMENT LEARNING-BASED INTEGRATED CIRCUIT DESIGN SYSTEM USING PARTITIONING AND DEEP REINFORCEMENT LEARNING-BASED INTEGRATED CIRCUIT DESIGN METHOD USING PARTITIONING LIN, ARIC 2851 §112 Non-Final OA 21d Pending Apr 06, 2023
18082823 APPARATUS AND METHOD FOR REINFORCEMENT LEARNING FOR OBJECT POSITION OPTIMIZATION BASED ON SEMICONDUCTOR DESIGN DATA DRAPEAU, SIMEON PAUL 2188 §102 Non-Final OA 21d Pending Dec 16, 2022
18074749 APPARATUS AND METHOD FOR REINFORCEMENT LEARNING BASED ON USER LEARNING ENVIRONMENT IN SEMICONDUCTOR DESIGN LU, HWEI-MIN 2142 §112 Non-Final OA 147d overdue Pending Dec 05, 2022
17878451 REINFORCEMENT LEARNING APPARATUS AND REINFORCEMENT LEARNING METHOD FOR OPTIMIZING POSITION OF OBJECT BASED ON DESIGN DATA STOICA, ADRIAN 2188 §103 Non-Final OA 155d overdue Pending Aug 01, 2022
17878482 REINFORCEMENT LEARNING APPARATUS AND METHOD BASED ON USER LEARNING ENVIRONMENT GAN, CHUEN-MEEI 2189 §103 Non-Final OA 97d overdue Pending Aug 01, 2022

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