DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 16 Dec 2022 for application number 18/082,851. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, and Claims.
Claims 1-20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 16 Apr 2024 was filed before the mailing of this Office Action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant's election with traverse in the reply filed on 11 May 2026 is acknowledged. The traversal is on the ground(s) that an excessive examination burden would not exist. This is found to be persuasive. As such, claims 1-20 are examined below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Reznicek et al. [hereinafter as Reznicek] (US 2021/0193829 A1 – as cited in IDS filed 16 Apr 2024).
In reference to claim 1, Reznicek teaches An integrated circuit comprising:
a first semiconductor device having a subfin [semiconductor substrate 100; Fig. 14B, para 0017] and one or more first semiconductor bodies [left nanosheet stack 120/130; Fig. 14B, para 0045] extending in a first direction [vertical direction; Fig. 14B] between a first source or drain region [source/drain region 1010 to the right of left 120/130; Fig. 14B, para 0062] and a second source or drain region [1010 to the right of left 120/130; Fig. 14B, para 0062];
a second semiconductor device having the subfin [100] and one or more second semiconductor bodies [right 120/130; Fig. 14B] extending in the first direction [vertical direction; Fig. 14B] between the first source or drain region [1010 to the right of left 120/130] and a third source or drain region [1010 to the right of right 120/130; Fig. 14B, para 0062];
a conductive layer [conductive layer 1410; Fig. 14B, para 0105] that wraps around the first source or drain region [1010 to the right of left 120/130] between the one or more first semiconductor bodies [left 120/130] and the one or more second semiconductor bodies [right 120/130], wherein the subfin [100] extends beneath the conductive layer [1410]; and
a dielectric layer [epitaxial oxide 710; Fig. 14B, para 0072] on a top surface of the subfin [100], such that the dielectric layer [710] is between the subfin [100] and the conductive layer [1410].
In reference to claim 3, Reznicek teaches The integrated circuit of claim 1, further comprising a silicide layer [silicide layer 1420; Fig. 14B, para 0105] around an outer surface of the first source or drain region [1010 to the right of left 120/130].
In reference to claim 4, Reznicek teaches The integrated circuit of claim 1, wherein the conductive layer [1410] extends in a second direction [into and out of the page in Fig. 14B; horizontal direction of Fig. 14C] between the first source or drain region [1010 to the right of left 120/130] and a dielectric plug [ILD 1230; Fig. 14C, para 0087], the second direction being orthogonal to the first direction [the first and second directions are orthogonal].
In reference to claim 8, Reznicek teaches A printed circuit board comprising the integrated circuit of claim 1 [para 0002 discloses a circuit].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 9-12, 15-17, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Reznicek in view of Lilak et al. [hereinafter as Lilak] (US 2020/0294998 A1).
In reference to claim 2, Reznicek teaches the invention of claim 1.
However, while Reznicek teaches The integrated circuit of claim 1, wherein the one or more first semiconductor bodies [left 120/130] and the one or more second semiconductor bodies [right 120/130] are nanosheets that comprise germanium, silicon, or any combination thereof [para 0046 discloses 120/130 can be silicon germanium], Reznicek does not explicitly teach that the semiconductor bodies are nanoribbons.
Lilak teaches that the semiconductor bodies are nanoribbons [paras 0015 disclose the semiconductor bodies can be nanoribbons].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Reznicek and Lilak before the effective filing date of the claimed invention, to include the nanoribbons as disclosed by Lilak into the semiconductor device of Reznicek in order to obtain a semiconductor device with nanoribbons.
One of ordinary skill in the art would be motivated to obtain a semiconductor device with nanoribbons to provide the predictable result of achieving stronger quantum confinement and better electrostatic control.
In reference to claim 9, Reznicek teaches An electronic device, comprising:
a chip package [para 0002 discloses an integrated circuits, which have dies] comprising one or more dies, at least one of the one or more dies comprising
a first semiconductor device having a subfin [semiconductor substrate 100; Fig. 14B, para 0017] and one or more first semiconductor nanosheets [left nanosheet stack 120/130; Fig. 14B, para 0045] extending in a first direction [vertical direction; Fig. 14B] between a first source or drain region [source/drain region 1010 to the right of left 120/130; Fig. 14B, para 0062] and a second source or drain region [1010 to the right of left 120/130; Fig. 14B, para 0062];
a second semiconductor device having the subfin [100] and one or more second semiconductor nanosheets [right 120/130; Fig. 14B] extending in the first direction [vertical direction; Fig. 14B] between the first source or drain region [1010 to the right of left 120/130] and a third source or drain region [1010 to the right of right 120/130; Fig. 14B, para 0062];
a conductive layer [conductive layer 1410; Fig. 14B, para 0105] that extends completely around the first source or drain region [1010 to the right of left 120/130] between the one or more first semiconductor nanosheets [left 120/130] and the one or more second semiconductor nanosheets [right 120/130], wherein the subfin [100] extends beneath the conductive layer [1410]; and
a dielectric layer [epitaxial oxide 710; Fig. 14B, para 0072] on a top surface of the subfin [100], such that the dielectric layer [710] is between the subfin [100] and the conductive layer [1410].
However, while Reznicek teaches nanosheets, Reznicek does not explicitly teach that the semiconductor bodies are nanoribbons.
Lilak teaches that the semiconductor bodies are nanoribbons [paras 0015 disclose the semiconductor bodies can be nanoribbons].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Reznicek and Lilak before the effective filing date of the claimed invention, to include the nanoribbons as disclosed by Lilak into the semiconductor device of Reznicek in order to obtain a semiconductor device with nanoribbons.
One of ordinary skill in the art would be motivated to obtain a semiconductor device with nanoribbons to provide the predictable result of achieving stronger quantum confinement and better electrostatic control.
In reference to claim 10, Reznicek and Lilak teach the invention of claim 9.
Reznicek teaches The electronic device of claim 9, wherein the at least one of the one or more dies further comprises a silicide layer [silicide layer 1420; Fig. 14B, para 0105] around an outer surface of the first source or drain region [1010 to the right of left 120/130].
In reference to claim 11, Reznicek and Lilak teach the invention of claim 10.
Reznicek teaches The electronic device of claim 10, wherein the silicide layer [1420] is directly between the first source or drain region [1010 to the right of left 120/130] and the conductive layer [1410].
In reference to claim 12, Reznicek and Lilak teach the invention of claim 9.
Reznicek teaches The electronic device of claim 9, wherein the conductive layer [1410] extends in a second direction [into and out of the page in Fig. 14B; horizontal direction of Fig. 14C] between the first source or drain region [1010 to the right of left 120/130] and a dielectric plug [ILD 1230; Fig. 14C, para 0087], the second direction being orthogonal to the first direction [the first and second directions are orthogonal].
In reference to claim 15, Reznicek teaches An integrated circuit comprising:
a semiconductor device having a subfin [semiconductor substrate 100; Fig. 14B, para 0017] and one or more semiconductor nanoribbons [left nanosheet stack 120/130; Fig. 14B, para 0045] extending in a first direction [vertical direction; Fig. 14B] from a source or drain region [source/drain region 1010 to the right of left 120/130; Fig. 14B, para 0062];
a conductive layer [conductive layer 1410; Fig. 14B, para 0105] that extends completely around the source or drain region [1010 to the right of left 120/130], wherein the subfin [100] extends beneath the conductive layer [1410]; and
a dielectric layer [epitaxial oxide 710; Fig. 14B, para 0072] on a top surface of the subfin [100], such that at least a portion of the dielectric layer [710] is between the subfin [100] and the conductive layer [1410].
However, while Reznicek teaches that the semiconductors are nanosheets, Reznicek does not explicitly teach that the semiconductors are nanoribbons.
Lilak teaches that the semiconductors are nanoribbons [paras 0015 disclose the semiconductor bodies can be nanoribbons].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Reznicek and Lilak before the effective filing date of the claimed invention, to include the nanoribbons as disclosed by Lilak into the semiconductor device of Reznicek in order to obtain a semiconductor device with nanoribbons.
One of ordinary skill in the art would be motivated to obtain a semiconductor device with nanoribbons to provide the predictable result of achieving stronger quantum confinement and better electrostatic control.
In reference to claim 16, Reznicek and Lilak teach the invention of claim 15.
Reznicek teaches The integrated circuit of claim 15, further comprising a silicide layer [silicide layer 1420; Fig. 14B, para 0105] around an outer surface of the source or drain region [1010 to the right of left 120/130].
In reference to claim 17, Reznicek and Lilak teach the invention of claim 15.
Reznicek teaches The integrated circuit of claim 15, wherein the conductive layer [1410] extends in a second direction [into and out of the page in Fig. 14B; horizontal direction of Fig. 14C] between the source or drain region [1010 to the right of left 120/130] and a dielectric plug [ILD 1230; Fig. 14C, para 0087], the second direction being orthogonal to the first direction [the first and second directions are orthogonal].
In reference to claim 20, Reznicek and Lilak teach the invention of claim 15.
Reznicek and Lilak teach The integrated circuit of claim 15, further comprising: a backside contact [source/drain contact 138; Fig. 9C, para 0013 of Lilak] below the source or drain region [1010 to the right of left 120/130 of Reznicek; analogously, source/drain 124 of Lilak; Fig. 9C, para 0023] and coupled to a bottom surface of the conductive layer [1410 of Reznicek], wherein a portion of the dielectric layer [710 of Reznicek; analogously, spacer 126 of Lilak; Fig. 9C, para 0013] is adjacent to each of the source or drain region [1010 to the right of left 120/130 of Reznicek; analogously, 124 of Lilak], the conductive layer [1410 of Reznicek], and the backside contact [138 of Lilak].
Allowable Subject Matter
Claim 5-7, 13-14, and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Examiner’s Note
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure as follows. Applicant is reminded that in amending in response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR § 1.111(0).
Radosavljevic et al. (US-11302808-B2) discloses trapezoidal-shaped structures in a nanoribbon device [Fig. 2].
Dewey et al. (US-20200105751-A1) discloses trapezoidal-shaped structures in a nanoribbon device [Fig. 4A].
Hsu et al. (US-20200006478-A1) discloses trapezoidal-shaped structures in a nanoribbon device [Fig. 2].
Conclusion
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/ANDREW CHUNG/
Examiner, Art Unit 2898
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