Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification submitted 12/16/2022 has been accepted by the examiner.
Drawings
The drawings submitted on 12/16/2022 have been accepted by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4, 6-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hung (US # 20190267374) in view of Hsieh (US # 20200135580) and Mallick (US # 20090104789).
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Regarding Claim 1, Hung (US # 20190267374) teaches an integrated circuit (see Figs. 11-14 and corresponding text) comprising:
a semiconductor device having a semiconductor region (fins 52 and S/D regions 70) extending in a first direction from a source region (source/drain region 70) to a drain region (source/drain region 70), and a gate structure (corresponds to feature 92) extending in a second direction over the semiconductor region; and
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a dielectric structure (104) extending in a third direction (perpendicular to the substrate active surface 50) through at least an entire thickness of the gate structure (see Fig. 11D showing gate cut 102 penetration depth), the dielectric structure comprising multiple different insulating materials, such as in a multi-layered configuration ([0054] insulating material may include or be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, the like, or a combination thereof).
Although Hung discloses much of the claimed invention, it does not explicitly teach the dielectric structure comprising a first dielectric layer along edges of the dielectric structure, the first dielectric layer having a first material composition, a second dielectric layer on the first dielectric layer, the second dielectric layer having a second material composition elementally different from the first material composition, a third dielectric layer on the second dielectric layer, the third dielectric layer having a greater density than the second dielectric layer, and a dielectric fill within a remaining volume of the dielectric structure and on the third dielectric layer.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
Firstly, Hsieh (US # 20200135580) is in the same or analogous field, and it teaches a dielectric structure comprising a first dielectric layer (275) along edges of the dielectric structure, the first dielectric layer having a first material composition (silicon oxide), a second dielectric layer (400) on the first dielectric layer, the second dielectric layer having a second material composition (SiCN or SiCON) elementally different from the first material composition (different elements shown), a third dielectric layer (500) on the second dielectric layer (direct physical contact is shown), a dielectric fill (510) within a remaining volume of the dielectric structure and on the third dielectric layer (shown).
A person having ordinary skill in the art would have recognized that modifying the dielectric structure materials of Hung with the materials and structures suggested by Hsieh would be obvious. Specifically, the modification suggested by Hsieh would be to employ a dielectric structure comprising a first dielectric layer along edges of the dielectric structure, the first dielectric layer having a first material composition, a second dielectric layer on the first dielectric layer, the second dielectric layer having a second material composition elementally different from the first material composition, a third dielectric layer on the second dielectric layer, and a dielectric fill within a remaining volume of the dielectric structure and on the third dielectric layer. Hsieh teaches forming stacked dielectric layers with different densities to reduce voids or seams in trench fill structures. For example, Figures 3D–3F show sequential dielectric layers deposited such that a later-formed dielectric layer is denser and exhibits fewer voids than the underlying dielectric layer. The reference explains that increasing film density through deposition conditions (e.g., plasma density or annealing conditions) results in improved void suppression and seam reduction in gap-fill structures.
Secondly, Mallick (US # 20090104789) is in the same or analogous field, and it teaches a dielectric structure and density-control techniques (see [0035]).
A person of ordinary skill in the art would have recognized that controlling dielectric density in stacked films is a known technique for reducing voids and seams, and improving the structural reliability of dielectric fills in narrow trenches. Since Hung’s structure includes a dielectric trench or gate-cut feature, the same void-reduction considerations would apply. Therefore, it would have been obvious to form the upper dielectric layer with greater density than the underlying layer (i.e. the third dielectric layer having a greater density than the second dielectric layer), as taught by Mallick, in order to improve gap-fill quality and reduce defects.
Regarding Claim 2, Hsieh, as applied to claim 1, teaches the integrated circuit of claim 1, wherein the first dielectric layer (275) directly contacts the gate structure (contacts 800, see Fig. 14).
Regarding Claim 4, Hsieh, as applied to claim 1, teaches the integrated circuit of claim 1, wherein the second dielectric layer comprises silicon and carbon and the third dielectric layer comprises silicon and carbon (SiON or SiCN).
Regarding Claim 6, Hung teaches the integrated circuit of claim 1, wherein the gate structure includes a gate dielectric around the semiconductor region and the gate dielectric is not present on any sidewall of the dielectric structure (shown in Fig. 12B).
Regarding Claim 7, the applicant recites that the dielectric structure has a height-to-width aspect ratio between 1:1 and 3:1.
Hung teaches a gate-cut dielectric structure extending through the gate stack (see Figs. 12A–12B). Hsieh teaches a multilayer dielectric structure within a trench or recess, and 20090104789A1 teaches that in high-aspect-ratio trenches, forming stacked dielectric layers with controlled densities is required to avoid voids or seams during deposition.
In particular, Mallick explains that height-to-width ratios exceeding approximately 3:1 may result in void formation, while ratios of 1:1 to 3:1 allow void-free, reliable dielectric fill (see [0030-32]).
Accordingly, it would have been obvious to a person of ordinary skill in the art to select a dielectric structure with a height-to-width aspect ratio within the 1:1 to 3:1 range to ensure that the dielectric fill could completely and reliably fill the gate-cut trench without forming voids, as taught by Mallick. Thus, the claimed aspect ratio is taught or suggested by the prior art in view of the known limitations of gap-fill processes for trenches and recesses, and claim 7 would have been obvious to a POSITA at the time of the invention.
Claim 8 recites a printed circuit board comprising the integrated circuit of claim 1. It would have been obvious to a person of ordinary skill in the art to mount the integrated circuit taught by Hung (see, e.g., Figs. 12A–12B) onto a printed circuit board, as this is conventional and well-known in the electronics industry. Accordingly, claim 8 would have been obvious in view of the combination of Hung, Hsieh, and Mallick, as mounting an IC on a PCB is a routine implementation of known ICs.
Claim 9 recites an electronic device comprising a chip package with one or more dies, at least one of which includes the integrated circuit of claim 1. Hung teaches the integrated circuit of claim 1 (see Figs. 12A–12B), and Hsieh teaches multilayer dielectric structures. Mallick teaches densification of dielectric layers to reduce voids. It would have been obvious to a person of ordinary skill in the art to incorporate the integrated circuit taught by Hung into a standard chip package, as packaging semiconductor dies is conventional in electronic devices. Accordingly, the combination of Hung, Hsieh, and Mallick teaches or suggests the claimed electronic device.
Claims 10-13 are rejected for essentially the same reasons as claims 2-4 and 7, respectively.
Claim 14 recites an integrated circuit comprising: one or more semiconductor regions, a gate structure extending over the semiconductor regions, a gate cut through the gate structure, and a dielectric structure extending through the gate structure, wherein the dielectric structure comprises a stacked multilayer dielectric with a dielectric fill and a top width greater than the underlying gate cut width, and the third dielectric layer has a greater density than the second dielectric layer and the dielectric fill.
As discussed in the rejection of claim 1, Hung teaches a gate-cut dielectric structure extending through a gate stack (see Figs. 12A–12B). In particular, feature 104 in Fig. 12B exhibits a trapezoidal cross section, with the top of the dielectric structure wider than the underlying gate cut, suggesting the claimed second width is greater than the first width.
Hsieh teaches a multilayer dielectric structure within a recess, including a first dielectric layer along the edges, a second dielectric layer over the first, a third dielectric layer on the second, and a dielectric fill within the remaining volume of the dielectric structure (layers 275, 400, 500, and 510). The reference shows that these layers can be formed in direct contact and is in the same field of semiconductor recess and gate-cut structures.
Mallick teaches forming multilayer dielectric structures with differing densities to reduce voids and seams. In particular, forming a denser third layer over a less dense second layer is a well-known technique for achieving void-free high-aspect-ratio dielectric fills.
It would have been obvious to a person of ordinary skill in the art to combine the teachings of Hung, Hsieh, and Mallick to form a dielectric structure in which: the dielectric structure extends through the gate stack, the dielectric comprises stacked first, second, and third dielectric layers, the third dielectric layer has greater density than the second layer and the fill, and the top of the dielectric structure is wider than the underlying gate cut to facilitate void-free deposition of the multilayer dielectric. Such a configuration is a predictable result of applying known gap-fill and densification techniques to the gate-cut structures taught by Hung and Hsieh. Accordingly, the combination of Hung, Hsieh, and Mallick teaches or renders obvious all limitations of claim 14.
Claims 15-17 and 20 are rejected for essentially the same reasons as claims 2-4 and 7, respectively.
Claim 19 recites that the second width of the dielectric structure is at least six times greater than the first width of the underlying gate cut.
Hung teaches a dielectric structure with a trapezoidal cross section, where the top of the dielectric structure is wider than the underlying gate cut (see Fig. 12B). Mallick teaches that forming a denser upper dielectric layer over lower dielectric layers reduces voids and seams in high-aspect-ratio trenches. A person of ordinary skill in the art would have recognized that to achieve void-free deposition in such structures, the top of the dielectric structure may need to be substantially wider than the underlying cut.
Accordingly, it would have been obvious to a POSITA to select the top width to be at least six times the underlying gate cut width to ensure reliable, void-free fill of the multilayer dielectric stack, as taught by Mallick and suggested by Hung. Therefore, the claimed limitation of a second width ≥6× the first width would have been obvious in view of the combination of Hung, Hsieh, and Mallick.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hung (US # 20190267374) in view of Hsieh (US # 20200135580) and Mallick (US # 20090104789) and further in view of Kane (US # 20240194696).
Regarding Claim 3, although Hung in view of Hsieh and Mallick discloses much of the claimed invention, it does not explicitly teach the integrated circuit of claim 1, wherein the first dielectric layer comprises silicon and nitrogen.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
For example, Kane (US # 20240194696) is in the same or analogous field, and it teaches an integrated circuit wherein a gate-cutting dielectric feature (145) comprises silicon and nitrogen ([0079]).
A person having ordinary skill in the art would have recognized that modifying the first material of Hung in view of Hsieh and Mallick with the material suggested by Kane would be obvious. Specifically, the modification suggested by Kane would be to employ an integrated circuit of claim 1, wherein the first dielectric layer comprises silicon and nitrogen. It would have been obvious to one of ordinary skill in the art at the time the claimed invention was made to use SiN since it has been held by the courts that selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill. In re Leshing, 125 USPQ 416 (CCPA 1960) and Sinclair & Carroll Co. v. Interchemical Corp., 65 USPQ 297 (1945).
Claims 5 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hung (US # 20190267374) in view of Hsieh (US # 20200135580) and Mallick (US # 20090104789) in view of Zhou (US # 20190355717).
Claim 5 depends from claim 4 and further recites that the dielectric fill has the second material composition, wherein the second material composition comprises silicon and carbon. Hung and Hsieh teach forming a dielectric fill within a dielectric structure extending through a gate structure, as discussed above with respect to claim 1.
However, Hung and Hsieh do not explicitly disclose that the dielectric fill comprises a material containing both silicon and carbon.
Zhou teaches filling recesses or trenches in semiconductor devices with dielectric materials. In particular, Fig. 9 and paragraph [0102] disclose that recess fills (275) may comprise insulating dielectric materials including silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or silicon borocarbide (SiBC). These materials contain both silicon and carbon and are disclosed as dielectric materials used to fill recess structures.
Accordingly, it would have been obvious to a person of ordinary skill in the art to employ a silicon-carbon dielectric material, such as SiCN or SiOCN, as the dielectric fill in the modified structure of Hung in view of Hsieh and 20090104789 in order to provide suitable dielectric insulation for the recess structure, since such silicon-carbon dielectric materials were known dielectric fill materials for semiconductor recesses and trenches. Therefore, the subject matter of claim 5 would have been obvious to a person of ordinary skill in the art at the time of the invention.
Claim 18 is rejected for essentially the same reasons as claim 5.
Conclusion
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/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899