Prosecution Insights
Last updated: October 02, 2026
Application No. 18/083,212

LIGHT EMITTING DEVICE AND LIGHT EMITTING MODULE

Non-Final OA §103
Filed
Dec 16, 2022
Priority
Dec 19, 2021 — provisional 63/291,448 +2 more
Examiner
KHALIFA, MOATAZ
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Seoul Viosys Co., Ltd.
OA Round
5 (Non-Final)
91%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
60 granted / 66 resolved
+22.9% vs TC avg
Minimal +2% lift
Without
With
+2.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
36 currently pending
Career history
112
Total Applications
across all art units

Statute-Specific Performance

§103
74.2%
+34.2% vs TC avg
§102
18.7%
-21.3% vs TC avg
§112
4.6%
-35.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 66 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments, see Remarks pages 6-10, filed 08/31/2026, with respect to the rejection(s) of claim(s) 1-5, 8, 10, 21-25 and 27-28 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Iguchi et al, US 20220069186 A1 (Iguchi). New Grounds of Rejection New grounds of rejection, over prior art reference Iguchi et al, US 20220069186 A1 (Iguchi), appears below. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s). Claims 1-5, 8, 21-25 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Iguchi et al, US 20220069186 A1 (Iguchi) in view of Leng, US 20220165993 A1 (Leng). Regarding claim 1; Iguchi teaches a light emitting module (Iguchi: Annotated Fig (1A) shared in this OA: 200) comprising: a circuit board (Fig (1A): 50); a plurality of light emitting devices (100) disposed on the circuit board (50); a first molding layer (15+16) surrounding side surfaces of the plurality of light emitting devices (100); a second molding layer disposed on the first molding layer; and a first electrode (30); wherein each of the plurality of light emitting devices (100) comprises a first semiconductor layer (11), a second semiconductor layer (13), and an active layer (12) disposed between the first semiconductor layer (11) and the second semiconductor layer (13), wherein a first surface of the first semiconductor layer (11) corresponds to a light exit surface of each of the plurality of light emitting devices (100), wherein the first electrode (30) covers the first surface of each of the plurality of light emitting devices (100) and a plurality of openings of the first molding layer (15+16), wherein the first molding layer (15+16) is no higher than a portion of the first electrode (30) covering the first surface of each of the plurality of light emitting devices (100), and wherein the second molding layer covers the first electrode. PNG media_image1.png 812 1109 media_image1.png Greyscale Iguchi does not teach a second molding layer disposed on the first molding layer, and wherein the second molding layer covers the first electrode. However, Leng teaches a second molding layer (Leng: Fig (3): 160) disposed on the first molding layer (170), and wherein the second molding layer (160) covers the first electrode (123). Iguchi and Leng are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Iguchi by incorporating a second molding layer such as disclosed in Leng to improve the protection of the device against external elements leading to a more reliable device. PNG media_image2.png 603 945 media_image2.png Greyscale Regarding claim 2; Iguchi in view of Leng discloses all the limitations of the light emitting module according to claim 1. Further, Iguchi teaches wherein each of the light emitting devices (Iguchi: Annotated Fig (1A) shared in this OA: 100) comprises a second electrode (23P) electrically connected to the second semiconductor layer (13), the first electrode (30) and the second electrode (23P) being disposed to face the circuit board (50). Regarding claim 3; Iguchi in view of Leng discloses all the limitations of the light emitting module according to claim 2. Further, Iguchi teaches wherein the first electrode (Iguchi: Annotated Fig (1A) shared in this OA: 30) and the second electrode (23P) of each of the plurality of light emitting devices (100) are electrically connected to the circuit board (50). Regarding claim 4; Iguchi in view of Leng discloses all the limitations of the light emitting module according to claim 2. Further, Iguchi teaches wherein the first electrode (Iguchi: Annotated Fig (1A) shared in this OA: 30) overlaps with an interface between the side surfaces of the plurality of light emitting devices (100) and the first molding layer (15+16). Regarding claim 5; Iguchi in view of Leng discloses all the limitations of the light emitting module according to claim 1. Further, Iguchi teaches wherein each of the plurality of light emitting devices (Iguchi: Annotated Fig (1A) shared in this OA: 100) comprises a second electrode (23P) electrically connected to the second semiconductor layer (13), the second electrode (23P) being disposed to face the circuit board (50). Regarding claim 8; Iguchi in view of Leng discloses all the limitations of the light emitting module according to claim 1. Further, Iguchi teaches wherein the first molding layer (Iguchi: Annotated Fig (1A) shared in this OA: 15+16) has an upper surface, having a periphery (upper surface of 16) flush with the first surface of the first semiconductor layer (11). Regarding claim 21; Iguchi teaches a light emitting module (Iguchi: Annotated Fig (1A) shared in this OA: 200) comprising: a circuit board (50); a plurality of light emitting devices (100) disposed on the circuit board (50); a first molding layer (15+16) surrounding side surfaces of the plurality of light emitting devices (100); a second molding layer disposed on the first molding layer; and a first electrode (30); wherein each of the plurality of light emitting devices (100) comprises a first semiconductor layer (11), a second semiconductor layer (13), and an active layer (12) disposed between the first semiconductor layer (11) and the second semiconductor layer (13), wherein a first surface (top surface) of the first semiconductor layer (11) corresponds to a light exit surface of each of the plurality of light emitting devices (100), wherein the first electrode (30) contacts the first surface of each of the plurality of light emitting devices (100) and a plurality of openings of the first molding layer (15+16), wherein the first molding layer (15+16) is no higher than a portion of the first electrode (30) contacting the first surface of each of the plurality of light emitting devices (100), and wherein the second molding layer covers the first electrode. Iguchi does not teach a second molding layer disposed on the first molding layer, and wherein the second molding layer covers the first electrode. However, Leng teaches a second molding layer (Leng: Fig (3): 160) disposed on the first molding layer (170), and wherein the second molding layer (160) covers the first electrode (123). Iguchi and Leng are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Iguchi by incorporating a second molding layer such as disclosed in Leng to improve the protection of the device against external elements leading to a more reliable device. Regarding claim 22; Iguchi in view of Leng discloses all the limitations of the light emitting module according to claim 21. Further, Iguchi teaches wherein each of the plurality of light emitting devices (Iguchi: Annotated Fig (1A) shared in this OA: 100) comprises a second electrode (23P) electrically connected to the second semiconductor layer (13), the first electrode (30) and the second electrode (23P) being disposed to face the circuit board (50). Regarding claim 23; Iguchi in view of Leng discloses all the limitations of the light emitting module according to claim 22. Further, Iguchi teaches wherein the first electrode (Iguchi: Annotated Fig (1A) shared in this OA: 30) and the second electrode (23P) of the light emitting device (100) are electrically connected to the circuit board (50). Regarding case 24; Iguchi in view of Leng discloses all the limitations of the light emitting module according to claim 21. Further, Iguchi teaches wherein the first electrode (Iguchi: Annotated Fig (1A) shared in this OA: 30) overlaps with an interface between the side surfaces of the plurality of light emitting devices (100) and the first molding layer (15+16). Regarding claim 25; Iguchi in view of Leng discloses all the limitations of the light emitting module according to claim 21. Further, Iguchi teaches wherein each of the plurality of light emitting devices (Iguchi: Annotated Fig (1A): 100) comprises a second electrode (23P) electrically connected to the second semiconductor layer (13), the second electrode (23P) being disposed to face the circuit board (50). Regarding claim 27; Iguchi in view of Leng discloses all the limitations of the light emitting module according to claim 21. Further, Iguchi teaches wherein the upper surface of the first molding layer (Iguchi: Annotated Fig (1A): 15+16) includes a periphery (upper surface of 16) flush with the first surface of the first semiconductor layer (11). Claims 10 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Iguchi et al, US 20220069186 A1 (Iguchi) in view of Leng, US 20220165993 A1 (Leng) in further view of Choe, US 20210074770 A1 (Choe). Regarding claim 10; Iguchi in view of Leng discloses all the limitations of the light emitting module according to claim 1. However, Iguchi in view of Leng does not teach wherein the second molding layer includes a plurality of openings corresponding to the plurality of openings of the first molding layer. Choe teaches wherein the second molding layer (Choe: Fig (14): BM3) includes a plurality of openings corresponding to the plurality of openings of the first molding layer (119). Iguchi in view of Leng and Choe are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application to modify Iguchi in view of Leng by using the openings in the second molding layer that correspond to the openings in the first molding layer as disclosed in Choe to improve the resolution of the device. Regarding claim 28; Iguchi in view of Leng discloses all the limitations of the light emitting module according to claim 21. However, Iguchi in view of Leng does not teach wherein the second molding layer includes a plurality of openings corresponding to the plurality of openings of the first molding layer. Choe teaches wherein the second molding layer (Choe: Fig (14): BM3) includes a plurality of openings corresponding to the plurality of openings of the first molding layer (119). Iguchi in view of Leng and Choe are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application to modify Iguchi in view of Leng by using the openings in the second molding layer that correspond to the openings in the first molding layer as disclosed in Choe to improve the resolution of the device. Conclusion Prior art made of record but not relied upon is considered pertinent to applicant’s disclosure: Sakong et al, US 20210013236 A1 (Sakong); teaches a plurality of LED units that contain two semiconductor layers and an active layer in between surrounded by molding layers. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /M.K./Examiner, Art Unit 2817 /Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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Prosecution Timeline

Show 9 earlier events
May 19, 2026
Response Filed
Jul 02, 2026
Final Rejection mailed — §103
Jul 27, 2026
Interview Requested
Aug 06, 2026
Interview Requested
Aug 26, 2026
Applicant Interview (Telephonic)
Aug 26, 2026
Examiner Interview Summary
Aug 31, 2026
Response after Non-Final Action
Sep 17, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
91%
Grant Probability
93%
With Interview (+2.3%)
3y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 66 resolved cases by this examiner. Grant probability derived from career allowance rate.

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