DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/16/2022 is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “third metal line” in claims 12 and 13 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 5, 7-9, 11-20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Li et al. (US 20220293513 A1).
Regarding claim 1, Li discloses a semiconductor device (200), comprising:
a transistor structure (260) comprising a plurality of source/drain regions (per [0078] as well as annotated below), wherein base portions (annotated below) of the plurality of source/drain regions correspond to a second side (below 230) of the semiconductor device (200) opposite to a first side (above 230) of the semiconductor device (200); ([0046], Fig. 2)
a plurality of metal lines (252, 254, 256) disposed on the second side (below 230) of the semiconductor device (200), wherein the plurality of metal lines (252, 254, 256) comprise at least a first metal line (252) and a second metal line (254); and
at least one dielectric layer (253) disposed between the first metal line (252) and the second metal line (254). ([0048], Fig. 2)
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Regarding claim 4, Li discloses the semiconductor device of claim 1, wherein the second side (below 230) comprises a backside (240) of the semiconductor device (200) and the first side (above 230) comprises a frontside (210) of the semiconductor device (200). ([0045], [0047], Fig. 2)
Regrading claim 5, Li discloses the semiconductor device of claim 1, wherein the at least one dielectric layer (253) comprises a high-K dielectric material. ([0049], Fig. 2)
Regarding claim 7, Li discloses the semiconductor device of claim 1, wherein the at least one dielectric layer (253) is disposed on a sidewall of the first metal line (252) and on a sidewall of the second metal line (254) opposite the sidewall of the first metal line (252). (Fig. 2)
Regarding claim 8, Li discloses the semiconductor device of claim 1, wherein the at least one dielectric layer (253) is disposed on a top surface of the first metal line (252) and on a bottom surface of the second metal line (254) opposite the top surface of the first metal line (252). (Fig. 2)
Regarding claim 9, Li discloses the semiconductor device of claim 1, wherein the second metal line (254) is stacked on the first metal line (252). (Fig. 2)
Regarding claim 11, Li discloses the semiconductor device of claim 1, wherein the at least one dielectric layer (253) is disposed on a first surface of at least one of the plurality of metal lines (252) and on a second surface of the at least one of the plurality of metal lines (254), wherein the second surface is perpendicular to the first surface. (Fig. 2)
Regarding claim 12, Li discloses the semiconductor device of claim 1, wherein the plurality of metal lines (252, 254, 256) further comprise at least a third metal line (256) stacked on top of at least one of the first metal line (252) and the second metal line (254). ([0048], Fig. 2)
Regrading claim 13, Li discloses the semiconductor device of claim 12, wherein third metal line (256) is connected to one of the first metal line (252) and the second metal line through at least one via (see inside 240/250 per [0048]). (Fig. 2)
Regarding claim 14, Li discloses the semiconductor device of claim 12, wherein the at least one via (see inside 250 per [0048]) comprises a dielectric layer (inside 240 per [0048]) on a sidewall of the at least one via (see inside 250 per [0048]).
Regrading claim 15, Li discloses a semiconductor device, comprising:
a plurality of metal lines (452, 454, 446, 448) disposed on a backside (below 430) of the semiconductor device (400), wherein the plurality of metal lines (452, 454, 446, 448) comprise at least a power supply line (454) and a ground line (452); ([0061], Fig. 4) and
at least one dielectric layer (453) disposed between the power supply line (454) and the ground line (452). ([0059], Fig. 2)
Regrading claim 16, Li discloses the semiconductor device of claim 15, wherein the at least one dielectric layer (453) is disposed on a sidewall of the power supply line (454) and on a sidewall of the ground line (452) opposite the sidewall of the power supply line (454). ([0059], Fig. 4)
Regarding claim 17, Li discloses the semiconductor device of claim 15, wherein the at least one dielectric layer (442) is disposed on a top surface of the power supply line (454) and on a bottom surface of the ground line (452) opposite the top surface of the power supply line (454). ([0061], Fig. 4)
Regarding claim 18, Li discloses a semiconductor device, comprising:
a transistor structure (160), wherein a base portion of the transistor structure (160) corresponds to a second side (below 130) of the semiconductor device (100) opposite to a first side (above 130) of the semiconductor device (100); ([0032], Fig. 1A)
a plurality of conductive lines (152 and 154) disposed on the second side (below 130) of the semiconductor device (100); ([0033], Fig. 1A) and
at least one dielectric layer (153) disposed between at least two conductive lines (152 and 154) of the plurality of conductive lines. ([0033], Fig. 1A)
Regarding claim 19, Li discloses the semiconductor device of claim 18, wherein the at least one dielectric layer (153) is disposed on a sidewall of a first conductive line (152) of the at least two conductive lines (152 and 154) and on a sidewall of a second conductive line (154) of the at least two conductive lines (152 and 154) opposite the sidewall of the first conductive line (152). (Fig. 1A)
Regarding claim 20, Li discloses the semiconductor device of claim 18, wherein the at least one dielectric layer (153) is disposed on a top surface of a first conductive line (152) of the at least two conductive lines (152 and 154) and on a bottom surface of a second conductive line (154) of the at least two conductive lines (152 and 154) opposite the top surface of the first conductive line (152). (Fig. 1A)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 20220293513 A1) as applied to claim 1, and further in view of Livengood et al. (US 20020020862 A1).
Regarding claim 2, Li discloses the semiconductor device of claim 1. Li does not disclose further comprising a plurality of contacts formed on the base portions respective ones of the plurality of source/drain regions, wherein at least one of the first metal line and the second metal line is connected to one or more of the plurality of contacts.
However, Livengood discloses:
a plurality of contacts (117a and 206) formed on the base portions (annotated below) respective ones of the plurality of source/drain regions (104), wherein at least one of the first metal line (116) and the second metal line (204) is connected to one or more of the plurality of contacts (117a and 206). (inverted Fig. 2)
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It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Li and Livengood to have a plurality of contacts formed on the base portions respective ones of the plurality of source/drain regions, wherein at least one of the first metal line and the second metal line is connected to one or more of the plurality of contacts in order to have “ an interconnect structure for integrated circuits that reduces the noise margin and voltage drop constraints” so as to “ to reduce power consumption.” (Livengood, [0007], [0006])
Regrading claim 3, Li discloses the semiconductor device of claim 2, wherein at least one of the first metal line (116) and the second metal line (204) is disposed on the one or more of the plurality of contacts (117a and 206).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Li and Livengood for similar reasons as stated above.
Claims 6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 20220293513 A1).
Regarding claim 6, Li Fig. 2 discloses the semiconductor device of claim 1. Li Fig. 2 does not explicitly disclose wherein the first metal line comprises a ground line and the second metal line comprises a supply voltage line.
However, Li Fig. 4 discloses:
the first metal line (452) comprises a ground line (Vss) and the second metal line (454) comprises a supply voltage line (Vdd). ([0061], Fig. 4)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Li for wherein the first metal line comprises a ground line and the second metal line comprises a supply voltage line because “multiple plate MIM capacitors can be used to decouple the power supply lines (Vdd) to improve processor performance” (Li, [0002])
Regarding claim 10, Li Fig. 2 discloses the semiconductor device of claim 9. Li Fig. 2 does not explicitly disclose wherein the first metal line comprises a ground line and the second metal line comprises a supply voltage line.
However, Li Fig. 4 discloses:
the first metal line (452) comprises a ground line (Vss) and the second metal line (454) comprises a supply voltage line (Vdd). ([0061], Fig. 4)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Li for wherein the first metal line comprises a ground line and the second metal line comprises a supply voltage line because “multiple plate MIM capacitors can be used to decouple the power supply lines (Vdd) to improve processor performance” (Li, [0002])
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897