DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see page 6, filed 04/22/2026, with respect to the drawings have been fully considered and are persuasive. The objection of the drawings has been withdrawn.
Applicant’s arguments, see pages 6-8, filed 04/22/2026, with respect to the rejection(s) of claims 1-20 under 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Zhang et al. (US 20200303244 A1).
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 4, 6, 7, 15, 16, 18 and 19 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Zhang et al. (US 20200303244 A1).
Regarding claim 1, Zhang discloses a semiconductor device (2100), comprising:
a transistor structure (2111/2112) disposed on a first side (front/top) of a substrate (at least 104), the transistor structure (2111/2112) comprising a plurality of source/drain regions (502/504 in Fig. 7 corresponding to 2504/2505 in Fig. 8) which extend through the substrate (at least 104) from the first side (top/front) of the substrate (at least 104) to a second side (bottom/back) of the substrate, opposite the first side, wherein base portions of the plurality of source/drain regions (502/504 in Fig. 7 corresponding to 2504/2505 in Fig. 8) correspond to the second side of the substrate (at least 104), (Fig. 9-11)
a plurality of metal lines (2515/2514) of a power delivery network (per [0055]) disposed on the second side (back) of the substrate (at least 104) wherein the plurality of metal lines (2515/2514) comprise at least a first metal line (2515) and a second metal line (2514), wherein the base portions of the plurality of source/drain regions (2505/2504) are coupled to at least one of the first metal line (2515) and the second metal line (2514); ([0055], Fig. 12) and
at least one dielectric layer (2400) disposed between the first metal line (2515) and the second metal line (2514). ([0055], Fig. 12)
Regarding claim 4, Zhang discloses the semiconductor device of claim 1, wherein:
the second side comprises a backside of the substrate (at least 104) and
the first side comprises a frontside of the substrate (at least 104). (Fig. 7-12)
the substrate (at least 104) is formed of a dielectric material (buried oxide). ([0037], Fig. 7-12)
Regarding claim 6, Zhang discloses the semiconductor device of claim 1, wherein the first metal line (2515) comprises a ground line (per [0055]) and the second metal line (2514) comprises a supply voltage line (per [0055]). (Fig. 12)
Regarding claim 7, Zhang discloses the semiconductor device of claim 1, wherein the at least one dielectric layer (2400) is disposed on a sidewall of the first metal line (2515) and on a sidewall of the second metal line (2514) opposite the sidewall of the first metal line. (Fig. 12)
Regrading claim 15, Zhang discloses a semiconductor device (2100), comprising:
a transistor structure (2111/2112) disposed on a first side (front/top) of a dielectric substrate (at least 104), the transistor structure(2111/2112) comprising a first source/drain region (2504) and second source/drain region (2505) which extend through the dielectric substrate (at least 104) from the first side (front/top) of the dielectric substrate to a second side (bottom/back) of the dielectric substrate (at least 104), opposite the first side; (Fig. 9-12)
a plurality of metal lines (2515/2514) disposed on the second side (bottom/back) of the dielectric substrate (at least 104) wherein the plurality of metal lines (2515/2514) comprise at least a power supply line and a ground line (per [00655]), and wherein respective bottom portions of the first and second source/drain regions (2505/2504) are connected to at least one of the power supply line (2514) and the ground line (2515); ([0055], Fig. 12) and
at least one dielectric layer (2400) disposed between the power supply line (2514) and the ground line (2515). ([0055], Fig. 12)
Regrading claim 16, Zhang discloses the semiconductor device of claim 15, wherein the at least one dielectric layer (2400) is disposed on a sidewall of the power supply line (2514) and on a sidewall of the ground line (2515) opposite the sidewall of the power supply line (2514). ([0055], Fig. 12)
Regarding claim 18, Zhang discloses a semiconductor device, comprising:
a dielectric substrate (at least 104) comprising a first side (front/top) and a second side (bottom/back) opposite the first side; (Fig. 7-12)
a first transistor structure (2112) disposed on the first side (front/top) of a dielectric substrate (at least 104) and comprising a first source/drain region (2505) which extends through the dielectric substrate (at least 104) from the first side to the second side; (Fig. 12)
a second transistor structure (2111) disposed on the first side of the dielectric substrate (at least 104) and comprising a second source/drain region (2504) which extends through the dielectric substrate (at least 104) from the first side to the second side; (Fig. 12)
a plurality of conductive lines of a power delivery network (2515/2514) disposed on the second side of the dielectric substrate (bottom/back); (Fig. 12) and
at least one dielectric layer (2400) disposed between at least two conductive lines (2515/2514) of the plurality of conductive lines; (Fig. 12)
wherein a bottom portion of the first source/drain region (2505) is coupled to a first conductive line (2515) of the at least two conductive lines; (Fig. 12) and
wherein a bottom portion of the second source/drain region (2504) is coupled to a second conductive line (2514) of the at least two conductive lines. (Fig. 12)
Regarding claim 19, Zhang discloses the semiconductor device of claim 18, wherein the at least one dielectric layer (2400) is disposed on a sidewall of the first conductive line (2515) of the at least two conductive lines and on a sidewall of the second conductive line (2514) of the at least two conductive lines opposite the sidewall of the first conductive line (2515). ([0055], Fig. 12)
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 2,3,5,8-14 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 20200303244 A1) as applied to claims 1, 15 and 18 above, and further in view of Livengood et al. (US 20020020862 A1).
Regarding claim 2, Zhang discloses the semiconductor device of claim 1. Zhang does not disclose wherein the base portions of the plurality of source/drain regions are coupled to at least one of the first metal line and the second metal line by respective via contacts formed on the base portions of the plurality of source/drain regions.
However, Livengood discloses:
wherein the base portions of the plurality of source/drain regions (104) are coupled to at least one of the first metal line (116) and the second metal line (204) by respective via contacts (117a/206) formed on the base portions of the plurality of source/drain regions (104). (Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Zhang and Livengood for the base portions of the plurality of source/drain regions are coupled to at least one of the first metal line and the second metal line by respective via contacts formed on the base portions of the plurality of source/drain regions in order to have “ an interconnect structure for integrated circuits that reduces the noise margin and voltage drop constraints” so as to “ to reduce power consumption.” (Livengood, [0007], [0006])
Regrading claim 3, Livengood discloses the semiconductor device of claim 2. Livengood does not disclose wherein the first metal line and the second metal line are disposed in a first metallization level.
However, Zhang discloses:
the first metal line (2515) and the second metal line (2514) are disposed in a first metallization level. (Fig. 12)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Livengood and Zhang for the first metal line and the second metal line are disposed in a first metallization level in order to “reduce the overcrowding of wiring” (Zhang, [0036])
Regrading claim 5, Zhang discloses the semiconductor device of claim 1. Zhang does not disclose the at least one dielectric layer comprises a high-K dielectric material.
However, Livengood discloses:
at least one dielectric layer (202) comprises a high-K dielectric material. ([0041], Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Zhang and Livengood for at least one dielectric layer comprises a high-K dielectric material so that “power supply decoupling capacitance is increased” (Livengood, [0041])
Regarding claim 8, Zhang discloses the semiconductor device of claim 1. Zhang does not disclose
wherein the at least one dielectric layer is disposed on a top surface of the first metal line and on a bottom surface of the second metal line opposite the top surface of the first metal line.
However, Livengood discloses:
wherein the at least one dielectric layer (202) is disposed on a top surface of the first metal line (204) and on a bottom surface of the second metal line (116) opposite the top surface of the first metal line (204). (Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Zhang and Livengood for at least one dielectric layer is disposed on a top surface of the first metal line and on a bottom surface of the second metal line opposite the top surface of the first metal line so that “power supply decoupling capacitance is increased” (Livengood, [0041])
Regarding claim 9, Zhang discloses the semiconductor device of claim 1. Zhang does not disclose wherein the second metal line is stacked on the first metal line.
However, Livengood discloses:
wherein the second metal line (116) is stacked on the first metal line (204). (Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Zhang and Livengood for the second metal line is stacked on the first metal line so that “power supply decoupling capacitance is increased” (Livengood, [0041])
Regarding claim 10, Livengood discloses the semiconductor device of claim 9, wherein the first metal line (116) comprises a ground line (per [0034]) and the second metal line (204) comprises a supply voltage line (per [0064]). (Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Livengood for the first metal line comprises a ground line and the second metal line comprises a supply voltage line so that “appropriate voltages may be applied” (Livengood, [0034])
Regarding claim 11, Zhang discloses the semiconductor device of claim 1. Zhang does not disclose wherein the at least one dielectric layer is disposed on a first surface of at least one of the plurality of metal lines and on a second surface of the at least one of the plurality of metal lines, wherein the second surface is perpendicular to the first surface.
However, Livengood discloses:
wherein the at least one dielectric layer (202) is disposed on a first surface of at least one of the plurality of metal lines (204) and on a second surface of the at least one of the plurality of metal lines (116), wherein the second surface is perpendicular to the first surface. (Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Zhang and Livengood for at least one dielectric layer is disposed on a first surface of at least one of the plurality of metal lines and on a second surface of the at least one of the plurality of metal lines, wherein the second surface is perpendicular to the first surface so that “power supply decoupling capacitance is increased” (Livengood, [0041])
Regarding claim 12, Zhang discloses the semiconductor device of claim 1. Zhang does not disclose wherein the plurality of metal lines further comprise at least a third metal line stacked on top of at least one of the first metal line and the second metal line.
However, Livengood discloses:
wherein the plurality of metal lines (116, 204, 110b) further comprise at least a third metal line (110b) stacked on top of at least one of the first metal line (116) and the second metal line (204). (Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Zhang and Livengood for the plurality of metal lines further comprise at least a third metal line stacked on top of at least one of the first metal line and the second metal line so that “appropriate voltages may be applied” (Livengood, [0034])
Regrading claim 13, Livengood discloses the semiconductor device of claim 12, wherein third metal line (110b) is connected to one of the first metal line (116) and the second metal line through at least one via (109a). (Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Zhang and Livengood for similar reasons mentioned beforehand.
Regarding claim 14, Livengood discloses the semiconductor device of claim 12, wherein the at least one via (109a) comprises a dielectric layer (108) on a sidewall of the at least one via (109a). (Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Zhang and Livengood for similar reasons mentioned beforehand.
Regarding claim 17, Zhang discloses the semiconductor device of claim 15. Zhang does not disclose wherein the at least one dielectric layer is disposed on a top surface of the power supply line and on a bottom surface of the ground line opposite the top surface of the power supply line.
However, Livengood discloses:
wherein the at least one dielectric layer (202) is disposed on a top surface of the power supply line (204) and on a bottom surface of the ground line (116) opposite the top surface of the power supply line (204). ([0034], [0064], Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Zhang and Livengood for at least one dielectric layer is disposed on a top surface of the power supply line and on a bottom surface of the ground line opposite the top surface of the power supply line so that “power supply decoupling capacitance is increased” (Livengood, [0041])
Regarding claim 20, Zhang discloses the semiconductor device of claim 18. Zhang does not disclose wherein the at least one dielectric layer is disposed on a top surface of a first conductive line of the at least two conductive lines and on a bottom surface of a second conductive line of the at least two conductive lines opposite the top surface of the first conductive line.
However, Livengood discloses:
wherein the at least one dielectric layer (202) is disposed on a top surface of a first conductive line (204) of the at least two conductive lines and on a bottom surface of a second conductive line (116) of the at least two conductive lines opposite the top surface of the first conductive line (204). (Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Zhang and Livengood for at least one dielectric layer is disposed on a top surface of a first conductive line of the at least two conductive lines and on a bottom surface of a second conductive line of the at least two conductive lines opposite the top surface of the first conductive line so that “power supply decoupling capacitance is increased” (Livengood, [0041])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Collins et al. (US 20220059476 A1) discloses a power delivery network of a package substrate in paragraph [0037], in Fig. 1b but does not disclose all the limitations as required by the claims.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights