DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species ‘a’ (claims 1-13 and 21-27) in the reply filed on 6/15/26 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 7-10 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Min (US 10,734,054) in view of Singh (US 2023/0335325).
Regarding claim 1, Min discloses a probabilistic logic device (this preamble is not given any particular weight since the body of the claim does not reference any logic or probability function) comprising: a spin orbit layer (see Figure 3, 24 for example); an insulating layer (22) on the SO layer; a ferromagnetic material layer (23) on the insulating layer; and a conductive electrode (33) on the FM material layer.
Min fails to teach the SO layer comprises a reduced symmetry material. However, the use of low symmetry layers in such devices was known at the time of filing (see Singh, Figure 3A, 302). Therefore, it would have been obvious to one having ordinary skill at the time of filing to use the low symmetry material in order to allow for an non-zero out of plane anitdamping torque (see paragraphs 0022-0027, 0032).
Regarding claim 2 and 3, Min discloses the logic device of claim 2, wherein the 2D TMD material comprises at least one of Niobium, Selenium, Molybdenum, and Tellurium (see paragraph 0023 for example).
Regarding claim 7, Min discloses the logic device of claim 1, wherein the insulating layer comprises at least one of Magnesium, Aluminum, and Oxygen (see column 8, lines 41+).
Regarding claim 8, Min discloses the logic device of claim 1, wherein the FM material layer comprises at least one of Cobalt, Iron, and Nickel (see column 8, lines 25+).
Regarding claim 9, Min discloses an integrated circuit device comprising: a plurality of probabilistic logic devices (MRAM array), at least one probabilistic logic device comprising (this is functionally descriptive, drawn to the intended use of the device and is not given any particular weight): a spin orbit layer comprising a two-dimensional transition metal dichalcogenide material (See Figure 3, 24 in view of rejection of claim 1 above); an insulating layer (22) on the SO layer; a ferromagnetic material layer (23) on the insulating layer; and a conductive electrode (33) on the FM material layer.
Regarding claim 10, Min discloses the integrated circuit device of claim 9, wherein the 2D TMD material comprises at least one of Niobium, Selenium, Molybdenum, and Tellurium (see rejections above).
Regarding claim 13, Min discloses the device of claim 9, but fails to specifically teach it deployed as an integrated circuit device assembly comprising a circuit board. However, it would have been obvious to one having ordinary skill at the time of filing to provide such a circuit board in order to distribute and integrate the device with other circuits.
Claim(s) 4, 12, and 21-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Min (US 10,734,054) in view of Singh (US 2023/0335325) as modified above and further in view of Wu (US 2019/0377037).
Regarding claim 21, Min discloses a device comprising: a spin orbit layer, wherein the SO layer comprises a reduced symmetry material; an insulating layer on the SO layer; a ferromagnetic material layer on the insulating layer (see rejections above).
Min as modified above fails to teach that the SO layer forms a Hall cross, with the stack formed on the middle part along with circuitry to detect a voltage induced in a first direction in the SO layer based on current induced through the FM material layer, the insulating layer, and the SO layer in a second direction in the SO layer orthogonal to the first direction.
However, this represents a hall cross configuration for sensing a magnetic field which was well known at the time of filing (se Wu , Figure 2). Therefore, it would have been obvious to one having ordinary skill at the time of filing provide the layer in a hall cross configuration and to provide readout circuitry as noted in order to sense the magnetic field.
Regarding claim 22, Min discloses the device of claim 21, wherein the reduced symmetry material comprises a two-dimensional transition metal dichalcogenide material (see rejection above).
Regarding claim 23, Min discloses the device of claim 22, wherein the 2D TMD material comprises at least one of Niobium, Selenium, Molybdenum, and Tellurium (see rejection above).
Regarding claim 24, Min discloses the device of claim 21, wherein the insulating layer comprises at least one of Magnesium, Aluminum, and Oxygen (see rejection above). .
Regarding claim 25, Min discloses the device of claim 21, wherein the FM material layer comprises at least one of Cobalt, Iron, and Nickel (see rejection above).
Regarding claim 4, Min discloses the logic device of claim 1, wherein the SO layer defines a Hall cross structure, and the insulating layer and FM layer are formed in a middle portion of the Hall cross structure (see rejection of claim 21).
Regarding claim 12, Min discloses the integrated circuit device of claim 9, wherein the SO layer defines a Hall cross structure, and the insulating layer and FM layer are formed in a middle portion of the Hall cross structure (see rejection of claim 21).
Claim(s) 5, 6, 11, 26 and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Min (US 10,734,054) in view of Singh (US 2023/0335325) and Wu (US 2019/0377037) an further in view of Withers (US 2018/0158913).
Regarding claims 5, 6, 11, 26 and 27, Min discloses the logic device of claim 1, but fails to teach wherein the SO layer comprises a heterostructure comprising a first reduced symmetry material and a second reduced symmetry material or (as in claim 6) wherein the SO layer comprises a heterostructure comprising the reduced symmetry material and a full symmetry material.
However, the use of different low symmetry TMD materials in a heterostructure and low symmetry TMD with full symmetry material in a heterostructure was known at the time (see Withers, paragraph 0097, 0135-0138; e.g. graphene being symmetric).
Regarding claim 26, Min discloses the device of claim 21, wherein the SO layer comprises a heterostructure comprising a first reduced symmetry material and a second reduced symmetry material.
Regarding claim 27, Min discloses the device of claim 21, wherein the SO layer comprises a heterostructure comprising the reduced symmetry material and a full symmetry material.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The remaining cited and attached references teach various embodiments of SOT layer configurations.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS KING whose telephone number is (571)272-2311. The examiner can normally be reached M-F: 9:00AM-5:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS KING/Primary Examiner, Art Unit 2824
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