DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to filing on 06/23/2026.
Claims 1, 3-8, 10-15 and 17-21 have been amended.
Claims 2, 9 and 16 have been cancelled.
Claims 22-24 have been newly added.
Claim 1- 24 are currently pending and have been considered below.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/29/2026 and 08/12/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicants’ arguments with respect to claims 1-24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3-8, 10-15 and 17-24 are rejected under 35 U.S.C. 103 as being unpatentable over Kundu et al (US 20210390004) in view of Banuli et al (WO 2021207429 A1) further in view of Rasal et al (US 2023/0306082 A1).
Regarding claim 1, Kundu discloses one or more processors (Figure 2, CPU 202) comprising circuitry to:
in response to receipt of an application programming interface (API) call , ([0073] states that “an AAL interface, through a set of one or more API functions, launches multiple workloads, such as those described in greater detail below in connection with FIGS. 3 and 16, on one or more hardware accelerators.”) cause one or more (Figure 2 and [0092] state that “… hardware accelerator 210 comprises hardware such as a FPGA, an ASIC, a DSP, a GPU …”) to generate packaging information for one or more wireless data packets (e.g., “a control plane is a component of a network architecture that configures data flow (e.g., packets) and handles routing of data.” and [e.g., signals, data packets]), ([0141] “In at least one embodiment, a control plane is a component of a network architecture that configures data flow and handles routing of data. In at least one embodiment, PHY driver 1306 sends a control-plane message to FH driver 1308 indicating reception of various data. Further information regarding a control plane can be found in description of FIG. 55. See also, [0150] “… In at least one embodiment, a control plane is a component of a network architecture that configures data flow and handles routing of data. In at least one embodiment, PHY driver 1406 sends a control-plane message to FH driver 1408 indicating transmission of various data …” ), and ( [0073] an inline acceleration model, in which …physical layer pipelines are offloaded; [0090] and FIG. 2, “an inline acceleration model … for accelerating various functions (e.g., 5G new radio operations) in which acceleration by function and input/output based acceleration are performed on a physical interface (e.g., a hardware accelerator) as packets ingress (e.g., enter) and/or egress (e.g., exit); further, Figure 16A); Figure 16A-16B and [0089] further discloses that “acceleration abstraction layer interface 106 provides various interfaces, functions, and processes usable by software such as software of layer 2+ application software 102 to offload certain functions that may be compute and/or power intensive and may be better performed on one or more hardware accelerators, such as hardware accelerator unit 114.” [0090] further states that “… accelerating various functions (e.g., 5G new radio operations) …”).
Kundu does not expressly disclose accelerators to perform a remote direct memory access (RDMA) read operation.
Banuli discloses a processor to perform an application programming interface (API) (table entry associated with each access to GPU- attached memory 1720-1723 is accessed prior to actual access to a GPU memory, causing the following operations. First, local requests from GPU 1710-1713 that find their page in GPU bias are forwarded directly to a corresponding GPU memory 1720-1723, see Banuli [0294]); Banuli’s [0002] discloses the environment being a 5G-NR).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Kundu to include Banuli’s teachings for the purpose of performing reading in a 5G-NR environment by using a hardware-assisted software means that efficiently accomplishes the reading.
Kundu in view of Banuli do not disclose explicitly to obtain information directly from memory of a network interface controller (NIC).
Rasal discloses to read … information directly being read from a network interface controller (NIC) memory (directly reading or writing to attached storage devices in response to remote initiator requests where the network device is a smart NIC ( Rasal, [0033]).
It would have been obvious to one having ordinary skill in the art before the effective date of the claimed invention to incorporate Rasal’s teachings with Kundu’s teachings in view of Banuli’s teachings. One skilled in the art would have been motivated to combine them for the purpose of securely performing reading in the storage of a smart NIC by using a direct access memory for securely perform directly reading from the NIC memory.
Claim 2. (Cancelled)
Regarding claim 3, in the obvious combination, Kundu discloses the one or more processors of claim 1, wherein the one or more accelerators function layer of the DU ([0073] states that “an AAL interface, through a set of one or more API functions, launches multiple workloads, such as those described in greater detail below in connection with FIGS. 3 and 16, on one or more hardware accelerators.” [0164] “functions up to resource element mapping in a O-RAN distributed unit (O-DU) and supports both an O-RAN radio unit (O-RU)”) that is to operate in an inline acceleration mode ([0096] “In at least one embodiment, diagram 300 depicts an implementation of an inline acceleration model such as those described in connection with FIG. 2.”).
Regarding claim 4, in the obvious combination, Kundu discloses the one or more processors of claim 1, wherein the one or more GPUs ([0219] “In at least one embodiment, data center may use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other ..”) function layer of the DU ([0164] “or downlink, split option 7-2x implements functions up to resource element mapping in a O-RAN distributed unit (O-DU) and supports both an O-RAN radio unit (O-RU)”) an AAL interface supports various offload architectures such as look-aside, inline, …”); also, [0432] “In at least one embodiment, MMU 3045 may include address translation lookaside buffers (TLB) or caches that may reside within graphics multiprocessor 3034 or L1 cache or processing cluster 3014”).
Regarding claim 5, in the obvious combination, Kundu discloses the one or more processors of claim 1, wherein the resource element mapping in a O-RAN distributed unit (O-DU) … for uplink, split option 7-2x implements resource mapping and higher functions in O-DU ”).
Regarding claim 6, in the obvious combination, Kundu discloses the one or more processors of claim 1, wherein the 5G-NR packaging information includes user data ([0567] “ … SGW 4510 routes and forwards user data packets, …”), wherein the user data comprises data to generated by user devices of an open radio access network ([0164] “In at least one embodiment, for uplink, split option 7-2x implements resource mapping and higher functions in O-DU and digital BF and lower functions in O-RU”).
Regarding claim 7, in the obvious combination, Kundu discloses the one or more processors of claim 1, wherein the processor is a host central processing unit of a distributed unit ([0211] “… central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices”).
Claim 8 contains subject matter similar to claim 1, and thus, is rejected under similar rationale. (Kundu, Abstract “Apparatuses, systems, and techniques to perform fifth generation (5G) new radio operations”).
Claim 9. (Cancelled)
Claim 10 contains subject matter similar to claim 3, and thus, is rejected under similar rationale.
Claim 11 contains subject matter similar to claim 4, and thus, is rejected under similar rationale.
Claim 12 contains subject matter similar to claim 5, and thus, is rejected under similar rationale.
Claim 13 contains subject matter similar to claim 6, and thus, is rejected under similar rationale.
Claim 14 contains subject matter similar to claim 7, and thus, is rejected under similar rationale.
Claim 15 contains subject matter similar to claim 1, and thus, is rejected under similar rationale. (Kundu, [0337] FIG. 23 “computer system 2300 is configured to implement various processes and methods described throughout this disclosure”).
Claim 16. (Cancelled)
Claim 17 contains subject matter similar to claim 3, and thus, is rejected under similar rationale.
Claim 18 contains subject matter similar to claim 4, and thus, is rejected under similar rationale.
Claim 19 contains subject matter similar to claim 5, and thus, is rejected under similar rationale.
Claim 20 contains subject matter similar to claim 6, and thus, is rejected under similar rationale.
Regarding claim 21, in the obvious combination, Kundu discloses the one or more processors of claim 1, wherein the at least one of: signal synchronization information, a workload identifier usable to associate the
Regarding claim 22, in the obvious combination, Banuli discloses one or more processors of claim 1, wherein the RDMA read operation is performed via a Peripheral Component Interconnect Express (PCI-e) interface ([0063] In at least one embodiment, vehicle 1200 may include CPU(s) 1218 (e.g., discrete CPU(s), or dCPU(s)), that may be coupled to SoC(s) 1204 via a high-speed interconnect (e.g., PCIe)).
It would have been obvious to one having ordinary skill in the art before the effective date of the claimed invention to incorporate Banuli’s teachings with Kundu’s teachings in view of Rasal’s teachings. One skilled in the art would have been motivated to combine them for the purpose of providing high-speed, low-latency, and direct data transfer between the Central Processing Unit, the memory and the hardware devices.
Regarding claim 23, in the obvious combination, Kundu discloses the system of claim 8, wherein the packaging information includes header information usable to determine: where at least one of the one or more wireless data packets is to be sent, or to what protocol layer the at least one wireless data packet is related ([0089] further discloses that “acceleration abstraction layer interface 106 provides various interfaces, functions, and processes usable by software such as software of layer 2+ application software 102 to offload certain functions that may be compute and/or power intensive and may be better performed on one or more hardware accelerators, such as hardware accelerator unit 114.”).
Regarding claim 24, in the obvious combination, Kundu discloses the method of claim 15, wherein the API call includes an accelerator identifier and a request to read header information for the one or more wireless data packets ([0073] states that “an AAL interface, through a set of one or more API functions, launches multiple workloads, such as those described in greater detail below in connection with FIGS. 3 and 16, on one or more hardware accelerators.” And, e.g., “a control plane is a component of a network architecture that configures data flow (e.g., packets) and handles routing of data.” and [e.g., signals, data packets]), ([0141] “In at least one embodiment, a control plane is a component of a network architecture that configures data flow and handles routing of data. In at least one embodiment, PHY driver 1306 sends a control-plane message to FH driver 1308 indicating reception of various data. Further information regarding a control plane can be found in description of FIG. 55).
Conclusion
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIO R PEREZ whose telephone number is (571)272-7846. The examiner can normally be reached 10Am - 6PM EST M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kathy Wang-Hurst can be reached at 5712705371. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JULIO R PEREZ/Primary Examiner, Art Unit 2644
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