DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to filing on 02/04/2026.
Claims 1- 6, 8-13 and 15-21 have been amended.
Claim 1- 21 are currently pending and have been considered below.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/04/2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/05/2026 and 02/23/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant’s arguments with respect to claims 1-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-21 are rejected under 35 U.S.C. 103 as being unpatentable over Kundu et al (US 20210390004).
Regarding claim 1, Kundu discloses a processor (Figure 2, CPU 202) comprising circuitry to:
in response to receipt of an application programming interface (API) call [from a second function layer of a distributed unit (DU) ] of a fifth generation new radio (5G-NR) network, ([0073] states that “an AAL interface, through a set of one or more API functions, launches multiple workloads, such as those described in greater detail below in connection with FIGS. 3 and 16, on one or more hardware accelerators.”) cause one or more graphics processing units (GPUs) [of a first function layer of the DU] (Figure 2 and [0092] state that “… hardware accelerator 210 comprises hardware such as a FPGA, an ASIC, a DSP, a GPU …”) to generate packaging ., “a control plane is a component of a network architecture that configures data flow (e.g., packets) and handles routing of data.” and [e.g., signals, data packets]), ([0141] “In at least one embodiment, a control plane is a component of a network architecture that configures data flow and handles routing of data. In at least one embodiment, PHY driver 1306 sends a control-plane message to FH driver 1308 indicating reception of various data. Further information regarding a control plane can be found in description of FIG. 55. See also, [0150] “… In at least one embodiment, a control plane is a component of a network architecture that configures data flow and handles routing of data. In at least one embodiment, PHY driver 1406 sends a control-plane message to FH driver 1408 indicating transmission of various data …” ), and ( [0073] an inline acceleration model, in which …physical layer pipelines are offloaded; [0090] and FIG. 2, “an inline acceleration model … for accelerating various functions (e.g., 5G new radio operations) in which acceleration by function and input/output based acceleration are performed on a physical interface (e.g., a hardware accelerator) as packets ingress (e.g., enter) and/or egress (e.g., exit); further, Figure 16A); Figure 16A-16B and [0089] further discloses that “acceleration abstraction layer interface 106 provides various interfaces, functions, and processes usable by software such as software of layer 2+ application software 102 to offload certain functions that may be compute and/or power intensive and may be better performed on one or more hardware accelerators, such as hardware accelerator unit 114.” [0090] further states that “… accelerating various functions (e.g., 5G new radio operations) …”).
Kundu ‘90004, does not expressly disclose application programming interface (API) call from a second function layer of a distributed unit (DU) or causing the one or more graphics processing units (GPUs) of a first function layer of the DU.
However, Kundu ‘90004 discloses, in different embodiments, an AAL interface is also referred to as an AAL, AAL API, AALI and/or variations thereof. In at least one embodiment, layer 2+ application software 102, through layer 2 (e.g., second or higher layer) to layer 1 (e.g., first or lower layer) interface 104, utilizes acceleration abstraction layer interface 106 to perform various functions, which are processed by drivers 108 through kernel space 112 to cause hardware 118 to perform one or more functions … , Kundu, [0077] and Figure 1.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective date of the claimed invention to combine the teachings of first embodiments with other Kundu’ embodiments in order to balance system flexibility with high-performance, real-time data processing.
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective date of the claimed invention to combine the teachings of different embodiments of Kundu in order to arrive at the invention specified in claim 1.
Regarding claim 2, Kundu discloses the processor of claim 1, wherein to generate includes to read the 5G-NR packaging In at least one embodiment, a control plane is a component of a network architecture that configures data flow and handles routing of data. In at least one embodiment, PHY driver 1306 sends a control-plane message to FH driver 1308 indicating reception of various data. Further information regarding a control plane can be found in description of FIG. 55”) from memory of a network interface ([0161] “in uplink data packets received”) from memory of a network interface ([0164] “Open radio access network (O-RAN) front haul (FH) 1604, also referred to as … network interface,” which is “an interface that enables transmission and reception of data.” Thus, “packaging information” is read (received) from a network interface. Note that the generated 5G-NR ‘packaging information’ (read as ‘data packets sent in uplink’) are received, therefore, given the broadest reasonable interpretation the data packets are read).
Regarding claim 3, Kundu discloses the processor of claim 1, wherein the function layer of the DU ([0164] “functions up to resource element mapping in a O-RAN distributed unit (O-DU) and supports both an O-RAN radio unit (O-RU)”) that is to operate in an inline acceleration mode ([0096] “In at least one embodiment, diagram 300 depicts an implementation of an inline acceleration model such as those described in connection with FIG. 2.”).
Regarding claim 4, Kundu discloses the processor of claim 1, wherein the one or more GPUs ([0219] “In at least one embodiment, data center may use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other ..”) function layer of the DU ([0164] “or downlink, split option 7-2x implements functions up to resource element mapping in a O-RAN distributed unit (O-DU) and supports both an O-RAN radio unit (O-RU)”) an AAL interface supports various offload architectures such as look-aside, inline, …”); also, [0432] “In at least one embodiment, MMU 3045 may include address translation lookaside buffers (TLB) or caches that may reside within graphics multiprocessor 3034 or L1 cache or processing cluster 3014”).
Regarding claim 5, Kundu discloses the processor of claim 1, wherein the 5G-NR packaging resource element mapping in a O-RAN distributed unit (O-DU) … for uplink, split option 7-2x implements resource mapping and higher functions in O-DU ”).
Regarding claim 6, Kundu discloses the processor of claim 1, wherein the 5G-NR packaging SGW 4510 routes and forwards user data packets, …”), wherein the user data comprises data to generated by user devices of an open radio access network ([0164] “In at least one embodiment, for uplink, split option 7-2x implements resource mapping and higher functions in O-DU and digital BF and lower functions in O-RU”).
Regarding claim 7, Kundu discloses the processor of claim 1, wherein the processor is a host central processing unit of a distributed unit ([0211] “… central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices”).
Claim 8 contains subject matter similar to claim 1, and thus, is rejected under similar rationale. (Kundu, Abstract “Apparatuses, systems, and techniques to perform fifth generation (5G) new radio operations”).
Claim 9 contains subject matter similar to claim 2, and thus, is rejected under similar rationale.
Claim 10 contains subject matter similar to claim 3, and thus, is rejected under similar rationale.
Claim 11 contains subject matter similar to claim 4, and thus, is rejected under similar rationale.
Claim 12 contains subject matter similar to claim 5, and thus, is rejected under similar rationale.
Claim 13 contains subject matter similar to claim 6, and thus, is rejected under similar rationale.
Claim 14 contains subject matter similar to claim 7, and thus, is rejected under similar rationale.
Claim 15 contains subject matter similar to claim 1, and thus, is rejected under similar rationale. (Kundu, [0337] FIG. 23 “computer system 2300 is configured to implement various processes and methods described throughout this disclosure”).
Claim 16 contains subject matter similar to claim 2, and thus, is rejected under similar rationale.
Claim 17 contains subject matter similar to claim 3, and thus, is rejected under similar rationale.
Claim 18 contains subject matter similar to claim 4, and thus, is rejected under similar rationale.
Claim 19 contains subject matter similar to claim 5, and thus, is rejected under similar rationale.
Claim 20 contains subject matter similar to claim 6, and thus, is rejected under similar rationale.
Regarding claim 21, Kundu discloses the processor of claim 1, wherein the 5G-NR packaging information includes at least one of: signal synchronization information, a workload identifier usable to associate the 5G-NR header information with a GPU operation, or routing information (pars. [0141] and [0150] discloses at least , routing information: “a control plane is a component of a network architecture that configures data flow and handles routing of data.” See [0150], ll. 2-3).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIO R PEREZ whose telephone number is (571)272-7846. The examiner can normally be reached 10Am - 6PM EST M-F.
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/JULIO R PEREZ/Primary Examiner, Art Unit 2644