DETAILED ACTION
This office action is in response to the arguments filed on February 11, 2026. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgements
Applicant's arguments filed on February 11, 2026, in response to the office action mailed on December 3, 2025 are acknowledged. The present office action is made with all the suggested arguments being fully considered. Accordingly, claims 1-20 are currently pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 19, 2022 is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 8-11, 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Romig (US 2021/0257282) in view of Mabutas (US 2020/0135620).
With respect to Claim 1, Romig shows (Fig. 2) most aspects of the current invention including a semiconductor package (MCM package), comprising:
a substrate (lead frame 110 containing terminals 115 in the MCM package)
a high voltage semiconductor die (130) attached to an electrically conductive part of the substrate (the input side of the lead frame 110)
a gate driver semiconductor die (142) attached, by an electrically insulative die attach material (143), to the electrically conductive part of the substrate (the output side of the lead frame 110) or to a side of the high voltage semiconductor die that faces away from the substrate,
Further Romig shows wherein the gate driver semiconductor die comprises a semiconductor body. However, Romig does not show wherein the gate driver semiconductor die comprises a polymer material covering a backside of the semiconductor body, wherein the polymer material is interposed between the semiconductor body and the die attach material such that the semiconductor body is electrically insulated from the substrate or the side of the high voltage semiconductor die that faces away from the substrate by an insulator stack that comprises both the polymer material and the die attach material.
On the other hand, and in the same field of endeavor, Mabutas teaches (Fig 8) a semiconductor package, comprising a semiconductor die (120) attached, by an electrically insulative die attach material (102), to a substrate (not shown but described), wherein the semiconductor die comprises a semiconductor body (120) and a polymer material (114) covering a backside of the semiconductor body (par 39), wherein the polymer material is interposed between the semiconductor body and the die attach material such that the semiconductor body is electrically insulated from the substrate or the side of the high voltage semiconductor die that faces away from the substrate by an insulator stack that comprises both the polymer material and the die attach material. Mabutas teaches the polymer material is used to electrically isolate the gate driver semiconductor die and the die attach material (par 39).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to incorporate wherein the gate driver semiconductor die comprises a polymer material covering a backside of the semiconductor body, wherein the polymer material is interposed between the semiconductor body and the die attach material such that the semiconductor body is electrically insulated from the substrate or the side of the high voltage semiconductor die that faces away from the substrate by an insulator stack that comprises both the polymer material and the die attach material in the device of Romig, as taught by Mabutas because the polymer material is used to electrically isolate the gate driver semiconductor die and the die attach material.
With respect to Claim 2, Romig shows (Fig. 2) further comprising: a mold compound (157) encapsulating the high voltage semiconductor die and the gate driver semiconductor die.
With respect to Claim 8, Mabutas teaches (Fig 8) wherein the polymer material is an epoxy or a polyimide.
With respect to Claim 9, Romig shows (Fig. 2) wherein the die attach material is a die attach film or an epoxy adhesive.
With respect to Claim 10, Romig shows (Fig. 2) wherein the substrate is a lead frame (115), wherein both the gate driver semiconductor die and the high voltage semiconductor die are attached to a die paddle of the lead frame. Furthermore, Mabutas teaches (Fig 1) wherein the semiconductor body of the gate driver semiconductor die is electrically insulated from the die paddle (lead frame) by both the polymer material and the die attach material.
With respect to Claim 11, Mabutas teaches (Fig 3) wherein the substrate is a lead frame (see Fig 6; par 33), a high voltage semiconductor die (112) is attached to a die paddle of the lead frame, and a semiconductor die (120) is attached to the side of the high voltage semiconductor die that faces away from the die paddle, and wherein the semiconductor body of the semiconductor die is electrically insulated from the high voltage semiconductor die by a polymer material (124) and a die attach material (124; par 27; layer 124 contains one or more of a polymer material, an epoxy material, or other polyepoxides, prepolymers, or polymers containing epoxide groups) and wherein the semiconductor body of the semiconductor die is electrically insulated from the high voltage semiconductor die by both the polymer material and the die attach material.
With respect to Claim 14, Romig shows (Fig. 2) wherein an edge of the gate driver semiconductor die tapers inward
With respect to Claim 15, Romig shows (Fig. 2) wherein the high voltage semiconductor die is a microcontroller die for a high voltage transistor or is a discrete high voltage transistor die.
With respect to Claim 16, Mabutas teaches (Fig 8) wherein the polymer material comprises a different material than the die attach material.
Claims 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over Romig (US 2021/0257282) in view of Mabutas (US 2020/0135620) and in further view of Bonifield (US 2021/0272886).
With respect to Claim 3, Romig in view of Mabutas shows most aspects the present invention. Further, although Mabutas teaches a polymer material (114) covering a backside of the semiconductor body, the combination of references fails to show wherein the polymer material has a thickness of at least 25 µm. However, it is noted that the specification fails to provide teachings about the criticality of the thickness of the polymer material.
On the other hand, and in the same field of endeavor, Bonifield teaches (Fig 1) a semiconductor package, comprising a semiconductor die (112) attached, by an electrically insulative die attach material (156), to a substrate, and a polymer material (136) covering a backside of the semiconductor body (par 21), wherein the polymer material is interposed between the semiconductor body and the die attach material and wherein the polymer material has a thickness of at least 25 µm (par 26).
Bonifield teaches the polymer material is a non-electrically conductive, that is also compatible with the packaging process and the mold compound material (par 21).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to incorporate wherein the polymer material has a thickness of at least 25 µm in the device of Romig and Mabutas, as taught by Bonifield because the polymer material is a non-electrically conductive, that is also compatible with the packaging process and the mold compound material.
Regarding claim 3, the courts have held that differences in the thickness will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Criticality: Since the applicant has not established the criticality of the thickness and similar thickness are known in the art (see e.g. Bonifield), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Romig in view of Mabutas. The specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
With respect to Claim 4, Bonifield teaches (Fig 1) wherein the thickness of the polymer material is in a range of 25 µm to 50 µm.
With respect to Claim 5, Romig in view of Mabutas shows most aspects the present invention. Further, although Mabutas teaches a polymer material (114) covering a backside of the semiconductor body, the combination of references fails to show wherein the thickness of the polymer material is thicker than the die attach material. However, it is noted that the specification fails to provide teachings about the criticality of the thickness of the polymer material.
On the other hand, and in the same field of endeavor, Bonifield teaches (Fig 1) a semiconductor package, comprising a semiconductor die (112) attached, by an electrically insulative die attach material (156), to a substrate, and a polymer material (136) covering a backside of the semiconductor body (par 21), wherein the polymer material is interposed between the semiconductor body and the die attach material and wherein the polymer material has a thickness of at least 25 µm (par 26).
Regarding claim 5, the courts have held that differences in the thickness will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Criticality: Since the applicant has not established the criticality of the thickness and similar thickness are known in the art (see e.g. Bonifield), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Romig in view of Mabutas. The specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
With respect to Claim 6, Romig in view of Mabutas shows most aspects the present invention. Further, although Mabutas teaches a polymer material (114) covering a backside of the semiconductor body, the combination of references fails to show wherein the polymer material has a dielectric strength greater than 25kV/mm. However, it is noted that the specification fails to provide teachings about the criticality of the dielectric strength of the polymer material
On the other hand, and in the same field of endeavor, Bonifield teaches (Fig 1) a semiconductor package, comprising a semiconductor die (112) attached, by an electrically insulative die attach material (156), to a substrate, and a polymer material (136) covering a backside of the semiconductor body (par 21), wherein the polymer material is interposed between the semiconductor body and the die attach material and wherein the polymer material has a thickness of at least 25 µm (par 26).
Regarding claim 6, the courts have held that differences in the dielectric strengths will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such dielectric strengths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Criticality: Since the applicant has not established the criticality of the dielectric strengths and similar dielectric strengths are known in the art (see e.g. Bonifield), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Romig in view of Mabutas. The specification contains no disclosure of either the critical nature of the claimed dielectric strengths or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
With respect to Claim 7, Romig in view of Mabutas shows most aspects the present invention. Further, although Mabutas teaches a polymer material (114) covering a backside of the semiconductor body, the combination of references fails to show wherein the insulator stack has a breakdown voltage greater than 3kV. However, it is noted that the specification fails to provide teachings about the criticality of the breakdown voltage of the insulator stack
On the other hand, and in the same field of endeavor, Bonifield teaches (Fig 1) a semiconductor package, comprising a semiconductor die (112) attached, by an electrically insulative die attach material (156), to a substrate, and a polymer material (136) covering a backside of the semiconductor body (par 21), wherein the semiconductor die is electrically insulated by an insulator stack that comprises both the polymer material and the die attach material, and wherein the polymer material has a thickness of at least 25 µm (par 26).
Regarding claim 7, the courts have held that differences in the breakdown voltage will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such breakdown voltages are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Criticality: Since the applicant has not established the criticality of the breakdown voltages and similar breakdown voltages are known in the art (see e.g. Bonifield), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Romig in view of Mabutas. The specification contains no disclosure of either the critical nature of the claimed breakdown voltages or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Romig (US 2021/0257282) in view of Mabutas (US 2020/0135620) and in further view of Celaya (US 2011/0298115).
With respect to Claim 12, Romig in view of Mabutas shows most aspects the present invention. Further, Mabutas teaches (Fig 8) wherein the semiconductor body of the semiconductor die is electrically insulated from the substrate by both the polymer material and the die attach material.
However, the combination of references fails to show wherein the substrate comprises a ceramic body, wherein the electrically conductive part of the substrate is a segment of a patterned metallization formed on the ceramic body, wherein both the gate driver semiconductor die and the high voltage semiconductor die are attached to the segment of the patterned metallization.
On the other hand, and in the same field of endeavor, Celaya teaches (Fig 5) a semiconductor package, comprising a high voltage semiconductor die (12) attached to an electrically conductive part of a substrate (152), and a gate driver semiconductor die (18) attached, by an electrically insulative die attach material, to the electrically conductive part of the substrate, wherein the substrate comprises a ceramic body, wherein the electrically conductive part of the substrate is a segment of a patterned metallization formed on the ceramic body, wherein both the gate driver semiconductor die and the high voltage semiconductor die are attached to the segment of the patterned metallization (par 32). Celaya teaches the breakdown voltage and the leakage current of the low side FET can be determined without damaging the gate driver that is coupled to the gate of the high side FET because the floating supply input is electrically isolated from the switching node (par 28).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to incorporate wherein the substrate comprises a ceramic body, wherein the electrically conductive part of the substrate is a segment of a patterned metallization formed on the ceramic body, wherein both the gate driver semiconductor die and the high voltage semiconductor die are attached to the segment of the patterned metallization in the device of Romig in view of Mabutas, as taught by Celaya because the breakdown voltage and the leakage current of the low side FET can be determined without damaging the gate driver that is coupled to the gate of the high side FET because the floating supply input is electrically isolated from the switching node.
With respect to Claim 13, Romig in view of Mabutas shows most aspects the present invention. Further, Mabutas teaches (Fig 8) wherein the semiconductor body of the semiconductor die is electrically insulated from the substrate by both the polymer material and the die attach material.
However, the combination of references fails to show wherein the substrate is a laminate, wherein the electrically conductive part of the substrate is a segment of a patterned metallization formed on the laminate, wherein both the gate driver semiconductor die and the high voltage semiconductor die are attached to the segment of the patterned metallization.
On the other hand, and in the same field of endeavor, Celaya teaches (Fig 5) a semiconductor package, comprising a high voltage semiconductor die (12) attached to an electrically conductive part of a substrate (152), and a gate driver semiconductor die (18) attached, by an electrically insulative die attach material, to the electrically conductive part of the substrate, wherein the substrate is a laminate, wherein the electrically conductive part of the substrate is a segment of a patterned metallization formed on the laminate, wherein both the gate driver semiconductor die and the high voltage semiconductor die are attached to the segment of the patterned metallization (par 32). Celaya teaches the breakdown voltage and the leakage current of the low side FET can be determined without damaging the gate driver that is coupled to the gate of the high side FET because the floating supply input is electrically isolated from the switching node (par 28).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to incorporate wherein the substrate is a laminate, wherein the electrically conductive part of the substrate is a segment of a patterned metallization formed on the laminate, wherein both the gate driver semiconductor die and the high voltage semiconductor die are attached to the segment of the patterned metallization in the device of Romig in view of Mabutas, as taught by Celaya because the breakdown voltage and the leakage current of the low side FET can be determined without damaging the gate driver that is coupled to the gate of the high side FET because the floating supply input is electrically isolated from the switching node.
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Romig (US 2021/0257282) in view of Mabutas (US 2020/0135620) and in further view of Chen (US 2021/0375826).
With respect to Claim 17, Romig shows (Fig. 2) most aspects of the current invention including a method of producing a plurality of semiconductor packages, the method comprising:
forming a gate driver circuit (142) at a plurality of die locations in a semiconductor wafer;
for each gate driver semiconductor die:
attaching a high voltage semiconductor die (130) to an electrically conductive part (the input side of the lead frame 110) of a substrate (lead frame 110 containing terminals 115 in the MCM package)
attaching, by an electrically insulative die attach material (143), the gate driver semiconductor die to the electrically conductive part of the substrate (the output side of the lead frame 110) or to a side of the high voltage semiconductor die that faces away from the substrate,
Further Romig shows wherein the gate driver semiconductor die comprises a semiconductor body. However, Romig does not show method steps of thinning a backside of the semiconductor wafer, covering the thinned backside of the semiconductor wafer with a polymer material, singulating the semiconductor wafer with the polymer material into a plurality of gate driver semiconductor dies and wherein the polymer material is interposed between a semiconductor body of the gate driver semiconductor die and the die attach material such that the semiconductor body is electrically insulated from the substrate or the side of the high voltage semiconductor die that faces away from the substrate by an insulator stack that comprises both the polymer material and the die attach material.
On the other hand, and in the same field of endeavor, Mabutas teaches (Fig 8) a semiconductor package, comprising a semiconductor die (120) attached, by an electrically insulative die attach material (102), to a substrate (not shown but described), wherein the semiconductor die comprises a semiconductor body (120) and a polymer material (114) covering a backside of the semiconductor body (par 39), wherein the polymer material is interposed between the semiconductor body and the die attach material such that the semiconductor body is electrically insulated from the substrate or the side of the high voltage semiconductor die that faces away from the substrate by an insulator stack that comprises both the polymer material and the die attach material. Mabutas teaches the polymer material is used to electrically isolate the gate driver semiconductor die and the die attach material (par 39).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to incorporate wherein the gate driver semiconductor die comprises a polymer material covering a backside of the semiconductor body, wherein the polymer material is interposed between the semiconductor body and the die attach material such that the semiconductor body is electrically insulated from the substrate or the side of the high voltage semiconductor die that faces away from the substrate by an insulator stack that comprises both the polymer material and the die attach material in the device of Romig, as taught by Mabutas because the polymer material is used to electrically isolate the gate driver semiconductor die and the die attach material.
However, Mabutas does not show method steps of thinning a backside of the semiconductor wafer, covering the thinned backside of the semiconductor wafer with a polymer material, singulating the semiconductor wafer with the polymer material into a plurality of gate driver semiconductor dies.
On the other hand, and in the same field of endeavor, Chen teaches (Fig 2A-2K) a method of producing a plurality of semiconductor packages, the method comprising forming a plurality of die locations (200) in a semiconductor wafer (202), thinning a backside of the semiconductor wafer (Fig 2E; par 41), covering the thinned backside of the semiconductor wafer with a polymer material (302) (Fig 2E-2F; par 42) and singulating the semiconductor wafer with the polymer material into a plurality of gate driver semiconductor dies (Fig 2I-2J; par 52-53)
Chen teaches during the thinning down process, the semiconductor substrates are thinned down and over-removed slightly from the back surfaces to form a recess R revealing portions of the through semiconductor vias which assist with the further process of performing the wafer sawing process for singulated die stack structures (par 42,54).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to incorporate method steps of thinning a backside of the semiconductor wafer, covering the thinned backside of the semiconductor wafer with a polymer material, singulating the semiconductor wafer with the polymer material into a plurality of gate driver semiconductor dies in the device of Romig in view of Mabutas, as taught by Chen because during the thinning down process, the semiconductor substrates are thinned down and over-removed slightly from the back surfaces to form a recess R revealing portions of the through semiconductor vias which assist with the further process of performing the wafer sawing process for singulated die stack structures.
With respect to Claim 18, Chen teaches (Fig 2A-2K) wherein the singulating comprises: attaching the thinned backside of the semiconductor wafer with the polymer material to a temporary carrier (TP) by a die attach film or epoxy adhesive (412); cutting through the semiconductor wafer along dicing streets which delimit the die locations using a first blade having a first width; and cutting through both the polymer material and the die attach film or epoxy adhesive along the dicing streets using a second blade having a second width that is less than the first width.
With respect to Claim 19, Chen teaches (Fig 2A-2K) wherein the cutting using the first blade tapers inward an edge of each gate driver semiconductor die.
With respect to Claim 20, Chen teaches (Fig 2A-2K) wherein the die attach film or epoxy adhesive remains on the polymer material of the gate driver semiconductor dies after the singulating and forms the electrically insulative die attach material.
Response to Arguments
Applicant's arguments filed on February 11, 2026 have been fully considered but they are not persuasive.
Applicant argues: That is, the pending claims require the gate driver semiconductor die to be attached to the high voltage semiconductor die or the high voltage semiconductor die and the gate drive semiconductor die to be attached to the same electrically conductive part of the substrate, Furthermore, even if Romig did teach a high voltage semiconductor die and a gate driver semiconductor die attached to the same electrically conductive part of the substrate, or a gate driver semiconductor die attached to a high voltage semiconductor die, as required by the pending claims, a point Applicant does not concede for the reasons explained above, Mabutas fails to teach a polymer material interposed between a semiconductor body and a die attach material as required by the pending claims. More specifically, the Office erroneously concluded that the die-attach pad 102 of Mabutas' lead frame 104 corresponds to the claimed die attach material, instead suggesting that Mabutas describes but doesn't show a substrate. Mabutas' lead frame 104 is clearly a substrate, not a die attach material.
Examiner responds: The examiner respectfully disagrees. In response to applicant's arguments that the primary references fail to show a feature of the Applicant’s invention, it is noted that the examiner is entitled to the broadest reasonable interpretation of the claim language. Additionally, although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). In particular, the limitations as recited in the body of claim 1 do not preclude the examiner's interpretation of the claimed “electrically conductive part of the substrate” feature as reading on the substrate/lead frame comprising an input side in which the high voltage semiconductor die (130) is attached and an output side in which the gate driver semiconductor die (142) attached, as disclosed by Romig. The examiner is not precluded from interpreting the claims as identified in the disclosure of the present application. The examiner has interpreted Romig consistently with the applicant’s disclosure, and has made a proper rejection of the currently presented claims.
Additionally, in response to applicant's argument that “Mabutas fails to teach a polymer material interposed between a semiconductor body and a die attach material as required by the pending claims”, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Mabutas teaches (Fig 8) a semiconductor die (120) attached to a substrate (not shown but described), wherein the semiconductor die comprises a semiconductor body (120), the semiconductor die attached to the substrate by a die attach material (102), and further comprising a polymer material (114) covering a backside of the semiconductor body (par 39). Mabutas teaches the polymer material (114) is used to electrically isolate the semiconductor die and the die attach material.
As a result, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to incorporate the polymer material (114) in the device of Romig, as taught by Mabutas because the polymer material can be used to electrically isolate the gate driver semiconductor die and the die attach material. Therefore, the examiner maintains the rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUINTON A BRASFIELD whose telephone number is (571)272-0804. The examiner can normally be reached M-F 9AM-4PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Q.A.B/ Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814