DETAILED ACTION
This office action is in response to the arguments filed on May 6, 2026. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgements
Applicant's arguments filed on May 6, 2026, in response to the office action mailed on March 18, 2026 are acknowledged. The present office action is made with all the suggested arguments being fully considered. Accordingly, claims 1-20 are currently pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 19, 2022 is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 8-10, 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2022/0139812) in view of Romig (US 2021/0257282)
With respect to Claim 1, Huang discloses (Fig. 3) most aspects of the current invention including a semiconductor package (20), comprising:
a substrate (100)
a high voltage semiconductor die (500) attached to an electrically conductive part of the substrate (portion 100)
an interposer/electronic component (200) attached, by an electrically insulative die attach material (710), to the electrically conductive part of the substrate (portion 100) or to a side of the high voltage semiconductor die that faces away from the substrate,
wherein the interposer/electronic component (200) comprises a semiconductor body (201) and a polymer material (520) covering a backside of the semiconductor body
wherein the polymer material is interposed between the semiconductor body (201) and the die attach material (710) such that the semiconductor body is electrically insulated from the substrate or the side of the high voltage semiconductor die that faces away from the substrate by an insulator stack that comprises both the polymer material and the die attach material
Furthermore, although Huang discloses that the interposer (200) may be an electronic component (par 30,36), Huang fails to disclose that the electronic component is a gate driver semiconductor die.
On the other hand, and in the same field of endeavor, Romig teaches (Fig 1-2) a semiconductor package, comprising a high voltage semiconductor die (130) and a gate driver semiconductor die (142) attached to an electrically conductive part of a substrate/lead frame (110). Romig teaches the gate driver semiconductor die is configured to drive gates of power transistors.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to incorporate wherein the electronic component is a gate driver semiconductor die in the device of Huang, as taught by Huang because the gate driver semiconductor die is configured to drive gates of power transistors.
With respect to Claim 2, Huang discloses (Fig. 3) further comprising: a mold compound (600) encapsulating the high voltage semiconductor die and the electronic component (gate driver device).
With respect to Claim 8, Huang discloses (Fig. 3) wherein the polymer material (520) is an epoxy or a polyimide (par 39)
With respect to Claim 9, Huang discloses (Fig. 3) wherein the die attach material (710) is a die attach film or an epoxy adhesive (par 38)
With respect to Claim 10, Huang discloses (Fig. 3) wherein the substrate is a lead frame (par 20), wherein both the electronic component (gate driver device) and the high voltage semiconductor die are attached to a die paddle (110) of the lead frame, and wherein the semiconductor body of the electronic component (gate driver device) is electrically insulated from the die paddle by both the polymer material and the die attach material.
With respect to Claim 15, Huang discloses (Fig. 3) wherein the high voltage semiconductor die is a microcontroller die for a high voltage transistor or is a discrete high voltage transistor die
With respect to Claim 16, Huang discloses (Fig. 3) wherein the polymer material (520) may comprise a different material than the die attach material (710).
Claims 3-7 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2022/0139812) in view of Romig and in further view of Bonifield (US 2021/0272886).
With respect to Claim 3, Huang in view of Romig shows most aspects the present invention. However, the combination of references do not show wherein the polymer material has a thickness of at least 25 µm.
On the other hand, and in the same field of endeavor, Bonifield teaches (Fig 1) a semiconductor package, comprising a semiconductor die (112) attached, by an electrically insulative die attach material (156), to a substrate, and a polymer material (136) covering a backside of the semiconductor body (par 21), wherein the polymer material is interposed between the semiconductor body and the die attach material and wherein the polymer material has a thickness of at least 25 µm (par 26).
Bonifield teaches the polymer material is a non-electrically conductive, that is also compatible with the packaging process and the mold compound material (par 21).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to incorporate wherein the polymer material has a thickness of at least 25 µm in the device of Huang and Romig, as taught by Bonifield because the polymer material is a non-electrically conductive, that is also compatible with the packaging process and the mold compound material.
However, it is noted that the specification fails to provide teachings about the criticality of the thickness of the polymer material.
Regarding claim 3, the courts have held that differences in the thickness will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the thickness and similar thickness are known in the art (see e.g. Bonifield), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Huang and Romig.
Criticality: The specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
With respect to Claim 4, Bonifield teaches (Fig 1) wherein the thickness of the polymer material is in a range of 25 µm to 50 µm.
With respect to Claim 5, Huang in view of Romig shows most aspects the present invention. Furthermore, although Huang discloses the polymer material covering a backside of the semiconductor body, the combination of references fails to show wherein the thickness of the polymer material is thicker than the die attach material.
On the other hand, and in the same field of endeavor, Bonifield teaches (Fig 1) a semiconductor package, comprising a semiconductor die (112) attached, by an electrically insulative die attach material (156), to a substrate, and a polymer material (136) covering a backside of the semiconductor body (par 21), wherein the polymer material is interposed between the semiconductor body and the die attach material and wherein the polymer material has a thickness of at least 25 µm (par 26). Bonifield teaches the polymer material is a non-electrically conductive, that is also compatible with the packaging process and the mold compound material (par 21).
However, it is noted that the specification fails to provide teachings about the criticality of the thickness of the polymer material thicker than the die attach material.
Regarding claim 5, the courts have held that differences in the thickness will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the thickness and similar thickness are known in the art (see e.g. Bonifield), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Huang and Romig.
Criticality: The specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
With respect to Claim 6, Huang in view of Romig shows most aspects the present invention. Furthermore, although Huang discloses the polymer material covering a backside of the semiconductor body, the combination of references fails to show wherein the polymer material has a dielectric strength greater than 25kV/mm.
On the other hand, and in the same field of endeavor, Bonifield teaches (Fig 1) a semiconductor package, comprising a semiconductor die (112) attached, by an electrically insulative die attach material (156), to a substrate, and a polymer material (136) covering a backside of the semiconductor body (par 21), wherein the polymer material is interposed between the semiconductor body and the die attach material and wherein the polymer material has a thickness of at least 25 µm (par 26). Bonifield teaches the polymer material is a non-electrically conductive, that is also compatible with the packaging process and the mold compound material (par 21).
However, it is noted that the specification fails to provide teachings about the criticality of the dielectric strength of the polymer material.
Regarding claim 6, the courts have held that differences in the dielectric strengths will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such dielectric strengths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the dielectric strengths and similar dielectric strengths are known in the art (see e.g. Bonifield), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Huang and Romig.
Criticality: The specification contains no disclosure of either the critical nature of the claimed dielectric strengths or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
With respect to Claim 7, Huang in view of Romig shows most aspects the present invention. Furthermore, although Huang discloses the polymer material covering a backside of the semiconductor body, the combination of references fails to show wherein the insulator stack has a breakdown voltage greater than 3kV.
On the other hand, and in the same field of endeavor, Bonifield teaches (Fig 1) a semiconductor package, comprising a semiconductor die (112) attached, by an electrically insulative die attach material (156), to a substrate, and a polymer material (136) covering a backside of the semiconductor body (par 21), wherein the polymer material is interposed between the semiconductor body and the die attach material and wherein the polymer material has a thickness of at least 25 µm (par 26). Bonifield teaches the polymer material is a non-electrically conductive, that is also compatible with the packaging process and the mold compound material (par 21).
However, it is noted that the specification fails to provide teachings about the criticality of the breakdown voltage of the insulator stack.
Regarding claim 7, the courts have held that differences in the breakdown voltage will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such breakdown voltages are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the breakdown voltages and similar breakdown voltages are known in the art (see e.g. Bonifield), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Huang and Romig.
Criticality: The specification contains no disclosure of either the critical nature of the claimed breakdown voltages or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Romig and in further view of Celaya (US 2011/0298115).
With respect to Claim 12, Huang in view of Romig shows most aspects the present invention. Furthermore, although Huang discloses wherein the semiconductor body of the electronic component (200) is electrically insulated from the substrate by both the polymer material and the die attach material, the combination of references fails to show wherein the substrate comprises a ceramic body, wherein the electrically conductive part of the substrate is a segment of a patterned metallization formed on the ceramic body, wherein both the gate driver semiconductor die and the high voltage semiconductor die are attached to the segment of the patterned metallization.
On the other hand, and in the same field of endeavor, Celaya teaches (Fig 5) a semiconductor package, comprising a high voltage semiconductor die (12) attached to an electrically conductive part of a substrate (152), and a gate driver semiconductor die (18) attached, to the electrically conductive part of the substrate and further wherein the substrate comprises a ceramic body, wherein the electrically conductive part of the substrate is a segment of a patterned metallization formed on the ceramic body, wherein both the gate driver semiconductor die and the high voltage semiconductor die are attached to the segment of the patterned metallization (par 32). Celaya teaches the substrate provides a support structure for the high voltage semiconductor die and the gate driver semiconductor die.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to incorporate wherein the substrate comprises a ceramic body, wherein the electrically conductive part of the substrate is a segment of a patterned metallization formed on the ceramic body, wherein both the gate driver semiconductor die and the high voltage semiconductor die are attached to the segment of the patterned metallization in the device of Huang and Romig, as taught by Celaya because the substrate provides a support structure for the high voltage semiconductor die and the gate driver semiconductor die.
With respect to Claim 13, Huang in view of Romig shows most aspects the present invention. Furthermore, although Huang discloses wherein the semiconductor body of the electronic component (200) is electrically insulated from the substrate by both the polymer material and the die attach material, the combination of references fails to show wherein the substrate is a laminate, wherein the electrically conductive part of the substrate is a segment of a patterned metallization formed on the laminate, wherein both the gate driver semiconductor die and the high voltage semiconductor die are attached to the segment of the patterned metallization.
On the other hand, and in the same field of endeavor, Celaya teaches (Fig 5) a semiconductor package, comprising a high voltage semiconductor die (12) attached to an electrically conductive part of a substrate (152), and a gate driver semiconductor die (18) attached, to the electrically conductive part of the substrate and further wherein the substrate is a laminate, wherein the electrically conductive part of the substrate is a segment of a patterned metallization formed on the laminate, wherein both the gate driver semiconductor die and the high voltage semiconductor die are attached to the segment of the patterned metallization (par 32). Celaya teaches the substrate provides a support structure for the high voltage semiconductor die and the gate driver semiconductor die.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to incorporate wherein the substrate is a laminate, wherein the electrically conductive part of the substrate is a segment of a patterned metallization formed on the laminate, wherein both the gate driver semiconductor die and the high voltage semiconductor die are attached to the segment of the patterned metallization in the device of Huang and Romig, as taught by Celaya because the substrate provides a support structure for the high voltage semiconductor die and the gate driver semiconductor die.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Huang US 2022/0139812) in view of Romig and in further view of Noguchi (US 2022/0208689).
With respect to Claim 14, Huang in view of Romig shows most aspects the present invention. However, the combination of references fails to show wherein an edge of the gate driver semiconductor die tapers inward.
On the other hand, and in the same field of endeavor, Noguchi teaches (Fig 1B,1D) a semiconductor package, comprising a semiconductor die (102), wherein an edge (102c) of the semiconductor die tapers inward. Noguchi teaches a semiconductor die having an edge that tapers inward may be applied generally to any type of packages, bare die, or a die with/without mold encapsulation.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to incorporate wherein an edge of the gate driver semiconductor die tapers is straight, or in the alternative, an edge of the gate driver semiconductor die tapers inward in the device of Huang and Romig, because having an edge of a semiconductor die that tapers inward is known in the semiconductor packaging art for their use in enhancing the semiconductor device, as suggested by Noguchi, and implementing such structure for its conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 17, the prior art of record fails to disclose or suggest a method of producing a plurality of semiconductor packages, the method comprising method steps of covering the thinned backside of the semiconductor wafer with a polymer material and singulating the semiconductor wafer with the polymer material into a plurality of gate driver semiconductor dies.
Examiner’s comments: the closest prior art references: (Huang US 2022/0139812; Romig; Noguchi US 2022/0208689; Chen US 2021/0375826; Celaya US 2011/0298115) are all directed in part to a method of producing a plurality of semiconductor packages or a method of producing a gate driver semiconductor die, similar to the instant invention.
However, the prior art neither anticipates nor renders obvious the following method steps of covering the thinned backside of the semiconductor wafer with a polymer material and singulating the semiconductor wafer with the polymer material into a plurality of gate driver semiconductor dies
Response to Arguments
Applicant’s arguments, see pages 1-5, filed on May 6, 2026, with respect to the rejection(s) of claim(s) 1-20 under 35 USC 103 have been fully considered and are persuasive. Therefore, the previous rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Huang (US 2022/0139812) in view of Romig (US 2021/0257282).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUINTON A BRASFIELD whose telephone number is (571)272-0804. The examiner can normally be reached M-F 9AM-4PM.
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/Q.A.B/ Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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