DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/19/2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over US PG Pub 2022/0344280 to Hsieh et al (hereinafter Hsieh).
Regarding Claims 1 and 20, Hsieh disclsoes a semiconductor structure comprising:
a first bonding dielectric layer (Fig. 2, 212) located on a surface of a wafer (211);
a second bonding dielectric layer (215) located on the first bonding dielectric layer;
a device-containing region (molding similar to 170, Fig. 1 and containing chips 201-203) located on the second bonding dielectric layer; and
wherein at least one of the first bonding dielectric layer or the second bonding dielectric layer is a stress modulating pattern (221-1) containing bonding dielectric layer comprising a plurality of patterned structures (Fig. 2).
Hsieh does not disclose a device wafer located on the device-containing region. However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have included a device wafer on the device containing region. Hsieh notes that additional device layers and wafers can be included as seen in Fig. 14. Placing these layers over either side of the semiconductor package would have been an obvious design choice to one of ordinary skill in the art.
Regarding Claim 2, Hsieh makes obvious the semiconductor structure of Claim 1, wherein only the first bonding dielectric layer is the stress modulating pattern containing bonding dielectric layer (Fig. 2).
Regarding Claim 3, Hsieh makes obvious the semiconductor structure of Claim 2, wherein the plurality of patterned structures are entirely embedded in the first bonding dielectric layer, and are present on a topmost surface of the wafer (Fig. 2).
Regarding Claim 4, Hsieh makes obvious the semiconductor structure of Claim 2, wherein the plurality of patterned structures are embedded in both the first bonding dielectric layer and the wafer [0058].
Regarding Claims 5-7, Hsieh makes obvious the semiconductor structure of Claim 1, wherein only the second bonding dielectric layer is the stress modulating pattern containing bonding dielectric layer or wherein both the first bonding dielectric layer and the second bonding dielectric layer are stress modulating pattern containing bonding dielectric layers since the insulator layer 212 can comprise a multilayer [0025] and in such an embodiment first and second bonding dielectric layers would be part of a multilayer and have the modulating patterns within all or select layers.
Regarding Claim 8, Hsieh makes obvious the semiconductor structure of Claim 7, wherein the plurality of patterned structures that are present in the first bonding dielectric layer are entirely embedded in the first bonding dielectric layer, and are present on a topmost surface of the wafer (Fig. 2).
Regarding Claim 9, Hsieh makes obvious the semiconductor structure of Claim 7, wherein the plurality of patterned structures that are present in the first bonding dielectric layer are embedded in both the first bonding dielectric layer and the wafer [0058.
Regarding Claim 10, Hsieh makes obvious the semiconductor structure of Claim 7, wherein the plurality of patterned structures that are present in the second bonding dielectric layer are at least partially embedded in the second bonding dielectric layer, and are in contact with the device-containing region since the insulator layer 212 can comprise a multilayer [0025] and in such an embodiment first and second bonding dielectric layers would be part of a multilayer and have the modulating patterns within all or select layers.
Regarding Claim 11, Hsieh makes obvious the semiconductor structure of Claim 1, wherein the plurality of patterned structures are patterned metal structures [0062].
Regarding Claim 12, Hsieh makes obvious the semiconductor structure of Claim 1, wherein the plurality of patterned structures are patterned dielectric structures [0062].
Regarding Claim 13, Hsieh makes obvious the semiconductor structure of Claim 1, wherein the plurality of patterned structures are arranged in an orthogonal grid pattern (Figs. 6-8).
Regarding Claim 14, Hsieh makes obvious the semiconductor structure of Claim I, wherein the plurality of patterned structures are arranged in a polar grid pattern (Figs. 6-8).
Regarding Claim 15, Hsieh makes obvious the semiconductor structure of Claim 1, wherein the plurality of patterned structures are arrays of continuous or discontinuous lines, arranged with uniform or non-uniform density (Figs. 6-8).
Regarding Claim 16, Hsieh makes obvious the semiconductor structure of Claim 15, further comprising:
a backside interlayer dielectric material layer (1415, Fig. 14) located on device-containing region and the device wafer, wherein wiring and/or contact structures are embedded in the backside interlayer dielectric material layer.
Regarding Claim 17, Hsieh makes obvious the semiconductor structure of Claim 16, further comprising:
a solder pad located on a surface of the wiring and/or contact structures; and
a solder bump located on each solder pad (Fig. 14)
Regarding Claim 18, Hsieh makes obvious the semiconductor structure of Claim 1, wherein the device-containing region comprises at least one semiconductor device (Chips 201-203).
Regarding Claim 19, Hsieh makes obvious the semiconductor structure of Claim 1, wherein a bonding interface exists between the first bonding dielectric layer and the second bonding dielectric layer (Fig. 2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893
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