Prosecution Insights
Last updated: July 17, 2026
Application No. 18/084,275

EMBEDDED MEMORY FOR GLASS CORE PACKAGES

Final Rejection §103
Filed
Dec 19, 2022
Examiner
FERNANDES, ERROL V
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
2 (Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
691 granted / 811 resolved
+17.2% vs TC avg
Moderate +11% lift
Without
With
+11.0%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
15 currently pending
Career history
825
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
84.9%
+44.9% vs TC avg
§102
12.7%
-27.3% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 811 resolved cases

Office Action

§103
DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-10 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. US 2021/0098421 A1 in view of Deng et al. US 2020/0083153 A1. Regarding claims 1, 2 and 4-10, Wu discloses: An electronic package (Fig. 12 in view of Figs. 1-11), comprising: a package substrate (T1C); a first die and second die (330Cs from left to right 1st, 3rd or 5th) embedded in the package substrate; and a third die (200D, 200F or 200H) over the package substrate. Wu does not disclose: wherein the first die and the second die are entirely within a footprint of the third die from a plan view perspective. Deng discloses a publication from a similar field of endeavor in which: a first die (210A) and a second die (210B) are entirely within a footprint of a third die (210C) from a plan view perspective (Fig .2). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the package configuration of Deng with the semiconductor package of Wu to determine a smaller footprint package structure with high density interconnections incorporating trace interconnections between embedded die as required by design choice. (claim 2) Wu: para 0030. (claim 4) Wu: a pad (112); and an adhesive layer (438). (claims 5 and 6) Wu: para 0052; fiberglass resin core. (claim 7) Wu: a third die (200E or 200G); or a fourth die (330Cs from left to right 2nd or 4th). (claim 8) Wu: 330s shown with the same thickness. (claim 9) Wu: paras 0030 and 0098; function as bridge dies. (claim 10) Wu: para 0107; 300 coupled to a substrate board. Regarding claim 18, Wu discloses: A computing system (Fig. 12 in view of Figs. 1-11), comprising: a board (para 0107; 300 coupled to a substrate board); an electronic package coupled to the board (90), wherein the electronic package comprises: a package substrate (T1C); a first die and a second die (330Cs from left to right 1st, 3rd or 5th) embedded in the package substrate; and a third die (200D, 200F or 200H) over the package substrate. Wu does not disclose: wherein the first die is a first memory die and the second die is a second memory die; and wherein the first die and the second die are entirely within a footprint of the third die from a plan view perspective. Deng discloses a publication from a similar field of endeavor in which: wherein the first die is a first memory die and the second die is a second memory die (paras 0049-0052); and a first die (210A) and a second die (210B) are entirely within a footprint of a third die (210C) from a plan view perspective (Fig .2). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the package configuration of Deng with the semiconductor package of Wu to determine a smaller footprint package structure with high density interconnections incorporating trace interconnections between embedded die as required by design choice. Regarding claims 3, 19 and 20, although Wu does not specifically disclose ”(claim 3) wherein the memory die is an L3 memory cache; (claim 19) a display coupled to the second die; and (claim 20) wherein the computing system is part of a personal computer, a server, a mobile device, a tablet, or an automobile”, Wu provides ample evidence, in paras 0002, 0030, 0038 and 0040, that various components, die types and device packages can be used to perform a variety of functions. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the claimed die, connections and directives, based on the citations of Wu, since the provided specification is geared towards increasing integration density and miniaturization of semiconductor packages in general. Allowable Subject Matter Claims 11-17 are allowed. The following is an examiner’s statement of reasons for allowance: The prior art fails to teach or clearly suggest the limitations of claim 11 stating “a third die embedded in the package substrate, wherein the third die is entirely within a footprint of the first die from a plan view perspective; a fourth die embedded in the package substrate, wherein the fourth die is within the footprint of the first die and within a footprint of the second die; and a fifth die embedded in the package substrate, wherein the fifth die is entirely within the footprint of the first die from the plan view perspective”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on (571) 270-30423042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERROL V FERNANDES/Primary Examiner, AU 2893
Read full office action

Prosecution Timeline

Dec 19, 2022
Application Filed
Jul 25, 2023
Response after Non-Final Action
Jan 27, 2026
Non-Final Rejection mailed — §103
Apr 22, 2026
Response Filed
Jul 10, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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MODULAR SYSTEMS IN PACKAGES, AND ASSOCIATED DEVICES, SYSTEMS, AND METHODS
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Patent 12672575
SEMICONDUCTOR STRUCTURE AND METHOD FOR ARRANGING REDISTRIBUTION LAYER OF SEMICONDUCTOR DEVICE
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ELECTRONIC DEVICE
2y 6m to grant Granted Jun 30, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
96%
With Interview (+11.0%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 811 resolved cases by this examiner. Grant probability derived from career allowance rate.

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