Prosecution Insights
Last updated: April 19, 2026
Application No. 18/084,275

EMBEDDED MEMORY FOR GLASS CORE PACKAGES

Non-Final OA §102§103
Filed
Dec 19, 2022
Examiner
FERNANDES, ERROL V
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
96%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
667 granted / 786 resolved
+16.9% vs TC avg
Moderate +12% lift
Without
With
+11.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
28 currently pending
Career history
814
Total Applications
across all art units

Statute-Specific Performance

§103
58.7%
+18.7% vs TC avg
§102
36.7%
-3.3% vs TC avg
§112
4.0%
-36.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 786 resolved cases

Office Action

§102 §103
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, 4-12, 14 and 16-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. US 2021/0098421 A1. Regarding claims 1, 2 and 4-10, Wu discloses: An electronic package (Fig. 12 in view of Figs. 1-11), comprising: a package substrate (T1C); a first die (330Cs from left to right 1st, 3rd or 5th) embedded in the package substrate; and a second die (200D, 200F or 200H) over the package substrate, wherein the first die is entirely within a footprint of the second die. (claim 2) para 0030. (claim 4) a pad (112); and an adhesive layer (438). (claims 5 and 6) para 0052; fiberglass resin core. (claim 7) a third die (200E or 200G); or a fourth die (330Cs from left to right 2nd or 4th). (claim 8) 330s shown with the same thickness. (claim 9) paras 0030 and 0098; function as bridge dies. (claim 10) para 0107; 300 coupled to a substrate board. Regarding claims 11, 12, 14, 16 and 17, Wu discloses: An electronic package (Fig. 12 in view of Figs. 1-11), comprising: a package substrate (T1C) with a core, wherein the core comprises glass (para 0052; fiberglass resin core); a first die (200D, 200F or 200H) over the package substrate; a second die (200E or 200G) over the package substrate and adjacent to the first die; a third die (330Cs from left to right 1st, 3rd or 5th) embedded in the package substrate, wherein the third die is entirely within a footprint of the first die; and a fourth die (330Cs from left to right 2nd or 4th) embedded in the package substrate, wherein the fourth die is within the footprint of the first die and within a footprint of the second die. (claim 12) para 0038; processing die. (claim 14) para 0030. (claim 16) 330s shown with the same thickness. (claim 17) paras 0030 and 0098; function as bridge dies. Regarding claim 18, Wu discloses: A computing system (Fig. 12 in view of Figs. 1-11), comprising: a board (para 0107; 300 coupled to a substrate board); an electronic package coupled to the board (90), wherein the electronic package comprises: a package substrate (T1C); a first die (330Cs from left to right 1st, 3rd or 5th) embedded in the package substrate, wherein the first die is a memory die; and a second die (200D, 200F or 200H) over the package substrate, wherein the first die is entirely within a footprint of the second die. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 3, 13, 15, 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. US 2021/0098421 A1. Regarding claims 3, 13, 15, 19 and 20, although Wu does not specifically disclose ”(claim 3) wherein the memory die is an L3 memory cache; (claim 13) wherein the processing core is a graphics processing core; (claim 15) wherein the memory die is an L3 cache; (claim 19) a display coupled to the second die; and (claim 20) wherein the computing system is part of a personal computer, a server, a mobile device, a tablet, or an automobile”, Wu provides ample evidence, in paras 0002, 0030, 0038 and 0040, that various components, die types and device packages can be used to perform a variety of functions. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the claimed die, connections and directives, based on the citations of Wu, since the provided specification is geared towards increasing integration density and miniaturization of semiconductor packages in general. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERROL V FERNANDES/Primary Examiner, AU 2893
Read full office action

Prosecution Timeline

Dec 19, 2022
Application Filed
Jul 25, 2023
Response after Non-Final Action
Jan 16, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604781
PACKAGE STRUCTURE INCLUDING GUIDING PATTERNS
2y 5m to grant Granted Apr 14, 2026
Patent 12599043
SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Apr 07, 2026
Patent 12593738
FLIP CHIP PACKAGE FOR SEMICONDUCTOR DEVICES
2y 5m to grant Granted Mar 31, 2026
Patent 12588470
GLASS CARRIER STACKED PACKAGE ASSEMBLY METHOD
2y 5m to grant Granted Mar 24, 2026
Patent 12588554
Semiconductor Device and Method Forming Same
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
96%
With Interview (+11.6%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 786 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month