DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to the amendment filed 11/19/2025 in which claims 1, 2, and 5 were amended and claim 12 was cancelled.
Claims 1-11 remain pending with claims 8, 9, and 11 remaining withdrawn and claims 1-7 and 10 presented for examination.
Claim Objections
Claim 1 is objected to because of the following informalities: in lines 7, 9, and 11, “the first” should be amended to read –the plurality of first–. Appropriate correction is required.
Claim 6 is objected to because of the following informalities: in line 2, “the first” should be amended to read –the plurality of first–. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Omura et al (US 2002/0030237 and Omura hereinafter) in view of Kraft et al (US 2011/0204436 and Kraft hereinafter).
As to claims 1-4 and 10: Omura discloses [claim 1] a semiconductor device (Figs. 1-4), comprising: a first electrode (Fig. 2; 20; [0059]); a semiconductor part (comprising 11, 12, 13, and 14; [0056]-[0057]) located on the first electrode (20); a second electrode (Fig. 2; 21; [0059]) located in a plurality of first regions (Figs. 1 and 2; each first region is the area of the substrate/semiconductor part that extends between adjacent trenches 15 and extends to the edge of the substrate/semiconductor part along that same line and on which 21 is in direct contact, as shown in the inserted Fig. 1 below; [0060]) on the semiconductor part (comprising 11, 12, 13, and 14); a third electrode (Figs. 1, 3, and 4; portion of 23 on top of 22; [0060]) located in a second region (each second region is the area over each trench 15 and the area that extends to the edge of the substrate/semiconductor part along the same line as the trench 15 would extend and on which 23 is formed in and areas adjacent to 23 that are not covered by 21 (essentially, each first region would be, as shown in the inserted Fig. 1 below, the area of substrate/semiconductor part between adjacent trenches 15 and extending to the edge of the substrate/semiconductor part in a same manner as if the trenches 15 extended there and the second region would be the area over each trench 15 and extending to the edge of the substrate/semiconductor part in a manner as though each trench 15 extended there; [0060]) on the semiconductor part (comprising 11, 12, 13, and 14); an insulating member (comprising 16 and 18; [0058]) located in the semiconductor part (comprising 11, 12, 13, and 14) in the first and second regions (Figs. 1-4; 16 and 18 are formed in the defined first and second regions); a fourth electrode (19; [0058]) located in the insulating member (portion 18) in the first and second regions (Fig. 3; 19 is formed in the defined first and second regions); a fifth electrode (17; [0058]) located in the insulating member (portion 16) between the first electrode (20) and the fourth electrode (19) in the first and second regions (Fig. 3; 19 is formed in the defined first and second regions); and a conductive member (Fig. 3; vertical portion of 23 that penetrates 22; [0060]) located at least in the second region (as defined in the inserted Fig. 1 below), the conductive member (vertical portion of 23 that penetrates 22) being connected to the third (portion of 23 on top of 22) and fourth electrodes (19), wherein the insulating member (comprising 16 and 18), the fourth electrode (19) and the fifth electrode (17) extend in a third direction (the third direction is the horizontal or left to right direction in Figs. 1, 2, and 4 and in the inserted Fig. 1 below; as the insulating member and fourth and fifth electrodes are three dimensional objects, they extend in all directions, including the horizontal or left to right direction in the figures cited), the plurality of first regions are arranged in the third direction (as shown in the inserted Fig. 1 below, the first regions are arranged or spaced along the defined third direction), the second region is located between two of the plurality of first regions in the third direction (as shown in the inserted Fig. 1 below, a second region is between adjacent first regions in the defined third direction); [claim 2] wherein the semiconductor part (comprising 11, 12, 13, and 14) includes: a first semiconductor layer (12; [0057]) connected (electrically connected) to the first electrode (20), the first semiconductor layer (12) being of a first conductivity type (n-type; [0057]); a second semiconductor layer (13; [0057]) located on the first semiconductor layer (12), the second semiconductor layer (13) being of a second conductivity type (p-type; [0057]); and a third semiconductor layer (14; [0057]) located on a portion of the second semiconductor layer (13) and connected to the second electrode (21), the third semiconductor layer (14) being of the first conductivity type (n-type; [0057]), the fourth electrode (19) facing the second (13) and third (14) semiconductor layers via a portion (18) of the insulating member (comprising 16 and 18), the fifth electrode (17) facing the first semiconductor layer (12) via another portion (16) of the insulating member (comprising 16 and 18); [claim 4] wherein the first electrode (20) and the second electrode (21) are arranged in the first direction (vertical direction in Figs. 2 and 3); [claim 10] wherein the fourth electrode (19) and the fifth electrode (17) include silicon (17 and 19 can be polysilicon; [0072] and [0074]).
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Omura fails to expressly disclose [claim 1] where the conductive member is connected to the fifth electrode; [claim 3] wherein the conductive member includes a metal; [claim 4] wherein the conductive member extends through the fourth electrode in a first direction.
Omura disclose in [0097] that the gate electrode (fourth electrode) 19 can be connected to the buried electrode (fifth electrode) 17, but fails to expressly disclose how.
Kraft discloses in Fig. 2H and [0024] a vertical trench transistor means to connect a gate electrode (fourth electrode) 222 to a buried electrode (fifth electrode) 214 [claim 1] where the conductive member (Fig. 2H; vertical portion of 226B touching 222 and 214; [0016], [0020], and [0024]) is connected to the fifth electrode (214; [0016]); [claim 3] wherein the conductive member (Fig. 2H; vertical portion of 226B touching 222 and 214) includes a metal (226B can be a metal; [0024]); [claim 4] wherein the conductive member (vertical portion of 226B touching 222 and 214) extends through the fourth electrode (“extends through” is interpreted to be a product-by-process limitation as it implies that the conductive member is formed in a trench that is etched through the fourth electrode, however, the claim does not state that there are portions of the fourth electrode on both sides of the conductive member, the limitation only requires some direct contact between the conductive member and the fourth electrode; therefore, the conductive member of Kraft (vertical portion of 226B that touches 222 and 214) meets the claimed language although produced by a different process as the conductive member is formed to directly contact a portion of the fourth electrode) in a first direction (vertical direction).
Given the teachings of Kraft, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Omura by employing the well-known or conventional features of vertical transistor fabrication with a buried electrode, such as displayed by Kraft, by employing a conductive member comprising a metal to electrically connect the buried electrode and gate electrode together in order to eliminate the need for a high-quality interelectrode dielectric thereby reducing manufacturing time and costs while providing a low resistance material to connect the two electrodes ([0025] of Kraft).
Allowable Subject Matter
Claims 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: as to claim 5, the closest prior art, Omura, discloses wherein pluralities of each of the insulating member (comprising 16 and 18), the fourth electrode (19), the fifth electrode (17), and the conductive member (vertical portion of 23 that penetrates 22) are provided (Fig. 2 shows plural insulating members, fourth electrodes, and fifth electrodes; as to the conductive members, Figs. 1 and 4 imply that each trench 15 will have a conductive member to contact the gate electrode in each respective trench), each of the plurality of insulating members (comprising 16 and 18), each of the plurality of fourth electrodes (19), and each of the plurality of fifth electrodes (17) extend in the third direction (horizontal direction in inserted Fig. 1 below), and the plurality of fourth electrodes (19) have common connections (region where the portion of 23 that is coplanar and formed on 22 and the vertical portion of 23 that extends through 22 meet) with the third electrode (portion of 23 on top of 22) in the second region (second region is the area 23 is formed in and areas adjacent to 23 that are not covered by 21). Omura fails to expressly disclose where the plurality of fifth electrodes and the plurality of fourth electrodes have common connections with the third electrode. Kraft discloses where the plurality (see Fig. 3) of fifth electrodes (214) and the plurality of fourth electrodes (214) have common connections (region where the portion of 226B that is coplanar and formed on 224 and the vertical portion of 226B that extends through 224 meet) with the third electrode (portion of 226B on top of 224). Omura in view of Kraft fail to expressly disclose where the plurality of insulating members is arranged along a second direction, the plurality of fourth electrodes is arranged along the second direction, the plurality of fifth electrodes is arranged along the second direction, the second direction crosses a first direction in which the first electrode and the second electrode are arranged, where the third direction crosses the first and second directions.
Response to Arguments
Applicant's arguments filed 11/19/2025 have been fully considered but they are not persuasive.
In the remarks, applicant argues in substance that neither Omura nor Kraft disclose the amended limitations of claim 1 where the insulating member, the fourth electrode and the fifth electrode extend in a third direction, the plurality of first regions are arranged in the third direction, the second region is located between two of the plurality of first regions in the third direction. Omura does not disclose two first regions arranged in the third direction.
Examiner respectfully traverses applicant’s remarks. As shown in the inserted Fig. 1 above, the first regions, second regions, and the third direction can be defined such that there is a second region between adjacent first regions along the horizontal (third) direction when the first regions are arranged (or spaced apart from each other) in the horizontal (third) direction. Therefore, the claimed subject matter is disclosed by Omura. Namely, Omura discloses in Figs. 1-4 where the insulating member (comprising 16 and 18), the fourth electrode (19) and the fifth electrode (17) extend in a third direction (the third direction is the horizontal or left to right direction in Figs. 1, 2, and 4 and in the inserted Fig. 1 above; as the insulating member and fourth and fifth electrodes are three dimensional objects, they extend in all directions, including the horizontal or left to right direction in the figures cited), the plurality of first regions are arranged in the third direction (as shown in the inserted Fig. 1 above, the first regions are arranged or spaced along the defined third direction), the second region is located between two of the plurality of first regions in the third direction (as shown in the inserted Fig. 1 above, a second region is between adjacent first regions in the defined third direction).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
3/7/2026