DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 15 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In claim 15 ll. 10, the “dielectric layer beneath the first source or drain region and the second source or drain region” is not described in the instant specification.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 15 ll. 10-11, it is indefinite as to whether the “first source or drain region and the second source or drain region” refers to the first and second source and drain regions or the first and second semiconductor regions. For purposes of examination the second interpretation will be used. Claims 16-20 do not cure the deficiencies of claim 15.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-5, 7-10, 12-15, 17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lilak et al. (US 2021/0296315) (“Lilak”).
With regard to claim 1, fig. 1A-1B of Lilak discloses an integrated circuit comprising: a first semiconductor device 120A having a first semiconductor region 106A extending in a first direction (in and out of page in fig. 1A) from a first source 105A or drain region, and a first gate structure 113A extending in a second direction (left to right in fig. 1A) over the first semiconductor region 106A; a second semiconductor device 120B having a second semiconductor region 106B extending in the first direction (in and out of page in fig. 1A) from a second source 105B or drain region, and a second gate structure 113B extending in the second direction (left to right in fig. 1A) over the second semiconductor region 106B, the second source 10fB or drain region being adjacent to the first source 106A or drain region along the second direction (left to right in fig. 1A); a first conductive contact (contact under 105A in fig. 1A) on an underside of the first source 105A or drain region and a second conductive contact (contact under 105B, fig. 1A) on an underside of the second source 106B or drain region; and a dielectric wall (110 and portion of 101 under it) extending in the first direction (in and out of page in fig. 1A) between and contacting both the first semiconductor region 106A and the second 106B semiconductor region, and extending between both the first source 105A or drain region and the second source 105B or drain region, wherein the dielectric wall (110 and portion of 101 under it in fig. 1A) further extends in a third direction (top to bottom in fig. 1A) along at least an entire thickness of the first conductive contact (contact under 105A, fig. 1A) and the second conductive contact (contact under 105B, fig. 1A).
With regard to claim 2, figs. 1A-1B of Lilak discloses that the dielectric wall (110 and portion of 101 under it in fig. 1A) directly contacts a sidewall of the first conductive contact (contact under 105A) and a sidewall of the second conductive contact (contact under 105B).
With regard to claim 4, figs. 1A-1B of Lilak discloses comprising a first dielectric fill (right 103 in fig. 1B) on a topside of the first source 105A or drain region and a second dielectric fill (left 103 in fig. 1B) on a topside of the second source 105B or drain region, wherein the dielectric wall 110 extends in the third direction (bottom to top in fig. 1A) between the first dielectric fill (right 103 in fig. 1B) and the second dielectric fill (left 103 in fig. 1B).
With regard to claim 5, figs. 1A-1B of Lilak discloses a dielectric layer (101 on the outside edge in fig. 1A) adjacent to the first conductive contact (contact under 105A) and the second conductive contact (contact under 106B).
With regard to claim 7, figs. 1A-1B of Lilak discloses that the second direction (left to right) is substantially perpendicular to the first direction (in and out of page) and wherein the third direction (bottom to top) is substantially perpendicular to both the first (in and out of page) and second directions (left to right).
With regard to claims 8 and 20, figs. 1A-1B of Lilak discloses that a printed circuit board 2102, comprising the integrated circuit 2104.
With regard to claim 9, figs. 1A-1B and 21 of Lilak discloses an electronic device 2100, comprising: a chip package 2106 comprising one or more dies, at least one of the one or more dies (“integrated circuit die package”, par [0147]) comprising a first semiconductor device 120A having a first semiconductor region 106A extending in a first direction (in and out of page in fig. 1A) between a first source (closer 105A in fig. 1A) or drain region and a second source or drain region (further 105A fig. 1A), and a first gate structure 113A extending in a second direction (left to right in fig. 1A) over the first semiconductor region 106A; a second semiconductor device 120B having a second semiconductor region 106B extending in the first direction (in and out of fig. 1A) between a third source (closer 105B, fig. 1A) or drain region and a fourth source or drain region (further 105B, fig. 1A), and a second gate structure 113B extending in the second direction (left to right) over the second semiconductor region 106B; a first conductive contact (contact under 105A in fig. 1A) on an underside of the first source (closer 105A, fig. 1A) or drain region and a second conductive contact (contact under closer 105B in fig. 1A) on an underside of the third source (closer 105B) or drain region; and a dielectric wall 110 extending in the first direction (in and out of page) between and contacting both the first semiconductor region 106A and the second semiconductor region 106B, extending in the first direction (in and out of page) between the first source (closer 105A) or drain region and the third source (closer 105B) or drain region, and extending in the first direction (in and out of page) between the second source or drain region (further 105A) and the fourth source or drain region (further 105B), wherein the dielectric wall 110 further extends in a third direction (top to bottom, fig. 1A) along at least an entire thickness of the first conductive contact (contact under closer 105A, fig. 1A) and the second conductive contact (contact under closer 105B).
With regard to claim 10, figs. 1A-1B of Lilak discloses the dielectric wall (101 between contact) directly separates the first conductive contact (contact under 105A) from the second conductive contact (contact under 105B).
With regard to claim 12, figs. 1A-1B of Lilak discloses a first dielectric fill (right 103, fig. 1B) on a topside of the first source (closer 105A) or drain region and a second dielectric fill (left 103) on a topside of the third source (closer 105B) or drain region, wherein the dielectric wall 110 extends in the third direction (bottom to top) directly between the first dielectric fill (right 103, fig. 1B) and the second dielectric fill (left 103, fig. 1B).
With regard to claim 13, figs. 1A-1B of Lilak discloses that the first semiconductor region 105A comprises a plurality of first semiconductor nanosheets 105A and the second semiconductor region 105B comprises a plurality of second semiconductor nanosheets 105B.
With regard to claim 14, figs. 1A-1B of Lilak discloses that a printed circuit board 2102, wherein the chip package 2104 is coupled to the printed circuit board 2102.
With regard to claim 15, figs. 1A-1B of Lilak discloses that an integrated circuit comprising: a first semiconductor device 120A having a first semiconductor region 106A extending in a first direction (out to into the page) from a first source (closer 105A, fig. 1A) or drain region, and a first gate structure 113A extending in a second direction (left to right, fig. 1A) over the first semiconductor region 106A; a second semiconductor device 120B having a second semiconductor region 106B extending in the first direction (out to into the page) from a second source (closer 105B) or drain region, and a second gate structure 113B extending in the second direction (left to right) over the second semiconductor region 106B, the second source (closer 105B) or drain region being adjacent to the first source (closer 105A) or drain region along the second direction (left to right); a dielectric layer (101 on outside, fig.1A) beneath the first source (closer 105A) or drain region and the second source (closer 105B) or drain region; a first conductive contact (contact under 105A) extending through an entire thickness of the dielectric layer (outer edge 101) and contacting an underside of the first source (105A, “block of semiconductor”, par [0036])) or drain region, and a second conductive contact (contact under 105B) extending through the entire thickness of the dielectric layer (outer edge 101) and contacting an underside of the second source (closer 105B) or drain region; and a dielectric wall 110 extending in the first direction (in and out) between the first source (closer 105A) or drain region and the second source or drain region, wherein the dielectric wall further extends in a third direction between the first conductive contact and the second conductive contact.
With regard to claim 17, figs. 1A-1B of Lilak discloses comprising a first dielectric fill (right 103) on a topside of the first source (closer 105A) or drain region and a second dielectric fill (left 103) on a topside of the second source (closer 105B) or drain region, wherein the dielectric wall 110 extends in the third direction (bottom to top) directly between the first dielectric fill (right 103) and the second dielectric fill (left 103).
With regard to claim 19, figs. 1A-1B of Lilak discloses that the second direction (left to right) is substantially perpendicular to the first direction (in and out) and wherein the third direction (top to bottom) is substantially perpendicular to both the first (in and out) and second directions (left to right).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak et al. (US 2021/0296315) (“Lilak”) in view of You et al. (US 2023/0317810) (“You”).
With regard to claims 6 and 18, Lilak discloses that the dielectric wall has a width in the second direction between about 5 nm and about 30 nm.
However, fig. 1H of You discloses that the dielectric wall 300 has a width in the second direction between about 5 nm and about 30 nm (“15 nm”, par [0046).
Therefore, it would have been obvious to one of ordinary skill in the art to form the backbon of Lilak with a width of 15nm as taught in You in order to provide sufficient active area spacing. See par [0046] of You.
Allowable Subject Matter
Claims 3, 11, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/BENJAMIN TZU-HUNG LIU/Primary Examiner, Art Unit 2893