DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I in the reply filed on October 10, 2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7-8, 10, 12-13, 15-17, 20, 22, and 24-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Onodera (USPGPUB 20200204159, hereinafter “Onodera”) in view of Onodera.
Regarding Claim 1, Onodera teaches (Fig. 1) a three-dimensional (3-D) integrated circuit (IC) structure (1), but the embodiment seen in Fig. 1 of Onodera is silent with regards to structure including one or more 3-D IC dies embedded within a stack of one or more planar lamination layers
Onodera (Fig. 11) teaches a structure including one or more 3-D IC dies (70) embedded within a stack of one or more planar lamination layers (91, [0036], “Specifically, the laminated component 20 is disposed on the mounting surface 11, and includes a lower stage component 30 and an upper stage component 40”; a person of ordinary skill in the art would recognize an embodiment where one of the IC die 70, as seen in Fig. 11, would be embedded at least partially within planar lamination layer 91).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the layout scheme of Onodera into the device of Onodera in order to arrive at the expected result of arrive at a device layout which is able to support more IC components and open the doors for more complex devices with reasonable expectation of success.
Regarding Claim 2, Onodera in view of Onodera teaches (Fig. 1) the invention of claim 1, wherein the 3-D IC structure (1) includes a top surface (top surface of element 30 is a top surface included within IC structure 1, as element 30 is included within IC structure 1, and thus the top and bottom surfaces of element 30 would be top and bottom surfaces included within the IC structure) and a bottom surface (bottom surface of element 30) opposite the top surface, the 3-D IC structure further including:(a) one or more connection pads (50 on the top and 34 on the bottom of element 30) formed on at least one of the top surface and a bottom surface of the 3-D IC structure (1); and (b) at least one electronic, electromechanical, and/or electro-optical component (80) attached and electrically coupled to (the electro-optical component 80 is seen attached and coupled electrically to connection pad 80 as they are both electrically coupled to substrate component 10) at least one of the one or more connection pads (50).
Regarding Claim 3, Onodera in view of Onodera teaches the invention of claim 2, wherein at least one of the one or more 3-D IC dies (70) includes a plurality of contact die-pads (74, 73) on a first surface (bottom surface of die 70, upon which pad 73 is disposed) and on a second surface (top surface of die 70, upon which pad 74 is disposed) opposite the first surface .
Regarding Claim 4, Onodera in view of Onodera teaches the invention of claim 3, wherein the 3-D IC structure further includes at least one conductive path (conductive path is seen by wire 60 contact die-pad 74 too connection pad 50) connecting at least one of the plurality of contact die-pads (74) to at least one of the one or more connection pads (50).
Regarding Claim 7, Onodera in view of Onodera teaches (Fig. 1) the invention of claim 1, wherein at least one of the one or more 3-D IC dies (70) includes a plurality of contact die-pads (74, 73) on a first surface (top surface) and on a second surface (bottom surface) opposite the first surface (top surface).
Regarding Claim 8, Onodera in view of Onodera teaches (Figs. 1, 11) the invention of claim 7, wherein the at least one of the one or more 3-D IC dies comprises first and second two-dimensional (2-D) IC dies (340, 330) each having a substrate, wherein the first and second 2-D IC dies are bonded together (dies 340 and 330 are seen bonded together) such that the substrate of the first 2-D IC die faces the substrate of the second 2-D IC die (being center-aligned, it can be seen that the ).
Regarding Claim 10, Onodera in view of Onodera teaches the invention of claim 7, wherein the at least one of the one or more 3-D IC dies comprises first and second two-dimensional (2-D) IC dies (330, 340) each having a substrate and a substructure/superstructure formed on the substrate, wherein the first and second 2-D IC dies are bonded together (dies 340 and 330 are seen bonded together by bond pads) such that the substructure/superstructure of the first 2-D IC die faces the substrate of the second 2-D IC die (the dies 330 and 340 are seen vertically center-aligned and as such the substrate and the substructures of each of the dies are seen facing each other).
Regarding Claim 12, Onodera in view of Onodera teaches (Fig. 11) the invention of claim 7, wherein the at least one of the one or more 3-D IC dies (340, 330) comprises a substrate having a first surface (top surface) and a second surface (bottom surface) opposite the first surface (top surface), wherein the first surface is processed to form a combined substructure/superstructure on the first surface and the second surface is processed to form a combined substructure/superstructure on the second surface (The laminated component 320 is an example of a second laminated component, and has a laminated structure of a plurality of circuit components. Specifically, the laminated component 320 is disposed on the mounting surface 11, and includes a lower stage component 330 and an upper stage component 340).
Regarding Claim 13, Onodera in view of Onodera teaches (Fig. 1) the invention of claim 1, wherein the 3-D IC structure includes at least two 3-D IC dies (70, 40) horizontally spaced (the dies 70, 40 are seen horizontally spaced from each other) with respect to each other within the 3-D IC structure.
Regarding Claim 15, Onodera teaches (Fig. 1) a three-dimensional (3-D) integrated circuit (IC) structure (1) having a top surface (top surface of element 30 is a top surface included within IC structure 1) and a bottom surface (bottom surface of element 30) opposite the top surface (top surface of element 30), the 3-D IC structure including: wherein at least one of the one or more 3-D IC dies includes a plurality of contact die- pads (73, 74) on a first surface (bottom surface of die 70) and on a second surface (top surface of die 70) opposite the first surface; and (b) one or more connection pads (50 on the top and 34 on the bottom) formed on at least one of the top surface and a bottom surface of the 3-D IC structure.
The embodiment of Onodera as seen in Fig. 1 is silent with regards to (a) one or more 3-D IC dies embedded within a stack of one or more planar lamination layers.
The embodiment of Onodera as seen in Fig. 11 teaches (a) one or more 3-D IC dies (70) embedded within a stack of one or more planar lamination layers (91, [0036], “Specifically, the laminated component 20 is disposed on the mounting surface 11, and includes a lower stage component 30 and an upper stage component 40”),
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the layout scheme of Onodera into the device of Onodera in order to arrive at the expected result of arrive at a device layout which is able to support more IC components and open the doors for more complex devices with reasonable expectation of success.
Regarding Claim 16, Onodera in view of Onodera teaches (Figs. 1, 11) The invention of claim 15, wherein the 3-D IC structure further includes at least one conductive path (conductive wire 60 connecting the connection pad 50 to the contact die-pad 74) connecting at least one of the plurality of contact die-pads (74) to at least one of the one or more connection pads (50).
Regarding Claim 17, Onodera in view of Onodera teaches (Figs. 1, 11) the invention of claim 15, further including at least one electronic, electromechanical, and/or electro-optical component (80) attached and electrically coupled to at least one of the one or more connection pads (component 80 is seen attached and electrically coupled to connection pad 50).
Regarding Claim 20, Onodera in view of Onodera (Figs. 1 and 11) teaches the invention of Claim 15, wherein the at least one of the one or more 3-D IC dies comprises first and second two-dimensional (2-D) IC dies (340, 330) each having a substrate, wherein the first and second 2-D IC dies are bonded together (dies 340 and 330 are seen bonded together) such that the substrate of the first 2-D IC die faces the substrate of the second 2-D IC die (being center-aligned, it can be seen that the substrates of the dies are facing each other ).
Regarding Claim 22, Onodera in view of Onodera (Figs . 1, 11) teaches the invention of claim 15, wherein the at least one of the one or more 3-D IC dies comprises first and second two-dimensional (2-D) IC dies (330, 340) each having a substrate and a substructure/superstructure formed on the substrate, wherein the first and second 2-D IC dies are bonded together (dies 340 and 330 are seen bonded together by bond pads) such that the substructure/superstructure of the first 2-D IC die faces the substrate of the second 2-D IC die (the dies 330 and 340 are seen vertically center-aligned and as such the substrate and the substructures of each of the dies are seen facing each other).
Regarding Claim 24, Onodera in view of Onodera teaches the invention of claim 15, wherein the at least one of the one or more 3-D IC dies (340, 330) comprises a substrate having a first surface (top surface) and a second surface (bottom surface) opposite the first surface (top surface), wherein the first surface is processed to form a combined substructure/superstructure on the first surface and the second surface is processed to form a combined substructure/superstructure on the second surface (The laminated component 320 is an example of a second laminated component, and has a laminated structure of a plurality of circuit components. Specifically, the laminated component 320 is disposed on the mounting surface 11, and includes a lower stage component 330 and an upper stage component 340).
Regarding Claim 25, Onodera in view of Onodera teaches (Fig. 1) the invention of claim 15, wherein the 3-D IC structure includes at least two 3-D IC dies (dies 40, 70 are seen horizontally spaced with respect to each other) horizontally spaced with respect to each other within the 3-D IC structure.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Onodera in view of Onodera as applied to claim 2 above, and further in view of Sterling et al (US 4584074 A, hereinafter “Sterling”).
Regarding Claim 6, Onodera in view of Onodera teaches the invention of claim 2, wherein the at least one component (30) is a multi-layer ceramic capacitor including interdigitated electrically-isolated internal electrodes ([0042], “the lower stage component 30 may be an integrated circuit (IC) or an integrated passive device (IPD). The IPD is, for example, a device in which passive elements such as inductors or capacitors are integrated”; [0042], “the lower stage component 30 includes a substrate having piezoelectricity and an interdigital transducer (IDT) electrode formed on the substrate”), internal via- type main electrodes connected to respective sets of the internal electrodes, and connection pads located on a bonding surface of the multi-layer ceramic capacitor and connected to respective ones of the internal via-type main electrodes.
Onodera in view of Onodera is silent with regards to a device wherein the interdigitated capacitor is a multi-layer ceramic capacitor.
Sterling a device wherein the interdigitated capacitor is a multi-layer ceramic capacitor (Col 1, Lns 19-23, “It is usual to employ a multilayer structure when fabricating ceramic devices, e.g. capacitors, so that layers of ceramic are interleaved with layers of metal electrode in such a way that an interdigitated two-electrode component of high capacitance value is produced”).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the ceramic structure of Sterling into the device of Onodera in view of Onodera in order to arrive at the expected result of creating a device with the known benefit of temperature stability due to its ceramic material with reasonable expectation of success.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Onodera in view of Onodera as applied to claim 17 above, and further in view of Sterling.
Regarding Claim 19, Onodera in view of Onodera teaches the invention of claim 17, wherein the at least one component (30) is a multi-layer ceramic capacitor including interdigitated electrically-isolated internal electrodes ([0042], “the lower stage component 30 may be an integrated circuit (IC) or an integrated passive device (IPD). The IPD is, for example, a device in which passive elements such as inductors or capacitors are integrated”; [0042], “the lower stage component 30 includes a substrate having piezoelectricity and an interdigital transducer (IDT) electrode formed on the substrate”), internal via- type main electrodes connected to respective sets of the internal electrodes, and connection pads located on a bonding surface of the multi-layer ceramic capacitor and connected to respective ones of the internal via-type main electrodes.
Onodera is silent with regards to a device wherein the interdigitated capacitor is a multi-layer ceramic capacitor.
Sterling a device wherein the interdigitated capacitor is a multi-layer ceramic capacitor Col 1, Lns 19-23, “It is usual to employ a multilayer structure when fabricating ceramic devices, e.g. capacitors, so that layers of ceramic are interleaved with layers of metal electrode in such a way that an interdigitated two-electrode component of high capacitance value is produced”).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the ceramic structure of Sterling into the device of Onodera in order to arrive at the expected result of creating a device with the known benefit of temperature stability due to its ceramic material with reasonable expectation of success.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Onodera in view of Onodera as applied to claim 7 above, and further in view of Usui et al (USPGPUB 20040140551, hereinafter “Usui”).
Regarding Claim 11, Onodera in view of Onodera teaches the invention of claim 7, wherein the at least one of the one or more 3-D IC dies comprises first and second two-dimensional (2-D) dies each having a substrate (dies 70 and 40 are seen with a substructure of devices formed on their substrates, and substructures within those devices formed to constitute a superstructure), a substructure formed on the substrate, and a superstructure formed on the substructure, wherein the first and second 2-D IC dies are bonded together such that the substructure of the first 2-D IC die faces the substrate of the second 2-D IC die and
Onodera in view of Onodera is silent with regards to a device wherein the substrate of the first 2-D IC die is removed.
Usui teaches a device wherein the substrate of the first 2-D IC die is removed ([0015], “the configuration according to the present invention does not include a support substrate for supporting the interconnect line”).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the reduction of the substrate as seen in Usui into the device of Onodera in view of Onodera in order to arrive at the expected result of creating a device with a lower profile and reduced weight (see [0015] of Usui) with reasonable expectation of success.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Onodera in view of Onodera as applied to claim 15 above, and further in view of Usui.
Regarding Claim 23, Onodera in view of Onodera teaches the invention of claim 15, wherein the at least one of the one or more 3-D IC dies comprises first and second two-dimensional (2-D) dies each having a substrate (dies 70 and 40 are seen with a substructure of devices formed on their substrates, and substructures within those devices formed to constitute a superstructure), a substructure formed on the substrate, and a superstructure formed on the substructure, wherein the first and second 2-D IC dies are bonded together such that the substructure of the first 2-D IC die faces the substrate of the second 2-D IC die and
Onodera in view of Onodera is silent with regards to a device wherein the substrate of the first 2-D IC die is removed.
Usui teaches a device wherein the substrate of the first 2-D IC die is removed ([0015], “the configuration according to the present invention does not include a support substrate for supporting the interconnect line”).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the reduction of the substrate as seen in Usui into the device of Onodera in view of Onodera in order to arrive at the expected result of creating a device with a lower profile and reduced weight (see [0015] of Usui) with reasonable expectation of success.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR J LASASSO whose telephone number is (703)756-5668. The examiner can normally be reached M-F 8-5 EST.
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/V.J.L./Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898