DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention of Group I, Claims 1-5 and 11-20, in the reply filed on 03/09/2026 is acknowledged.
Claims 6-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/09/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 4-5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morita Tatsuo (JP 2018067730A).
Regarding claim 1, Morita discloses, as shown in Figures 7-15, an integrated circuit structure comprising:
a GaN device on or above a substrate (101), the GaN device comprising a source (113), a gate (112) and a drain (114); and
a silicon-based diode structure (118) or a silicon-based thin-film resistor (117) (page 29) above the substrate, the silicon-based diode structure or the silicon-based thin-film resistor over the GaN device in a region between the gate and the drain of the GaN device.
Regarding claim 2, Morita discloses the silicon-based diode structure or the silicon-based thin-film resistor comprises a silicon crystal layer.
Regarding claim 4, Morita discloses the silicon-based diode structure comprises doped regions in the silicon crystal layer
Regarding claim 5, Morita discloses further comprising contacts (A,K) to the GaN device and to the silicon-based diode structure or the silicon-based thin-film resistor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morita Tatsuo (JP 2018067730A).
Morita discloses the claimed invention including the integrated circuit structure as explained in the above rejection. Morita further discloses the crystal layer (of the diode) is formed on and connected to the GaN. Morita does not clearly disclose the silicon crystal layer is bonded to a dielectric, the dielectric layer above the GaN. However, Morita discloses, in Figure 12, a dielectric layer (140) is above the GaN. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the structure of Morita having the dielectric between the GaN device and the silicon crystal layer, such as taught by Figure 12 of Morita, in order to protect the GaN device from short-circuit.
Claim(s) 11-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morita Tatsuo (JP 2018067730A) in view of Jun et al. (US 2017/0077281).
Regarding claim 11, Morita discloses, as shown in Figures, a component including an integrated circuit structure comprising:
a GaN device on or above a substrate (101), the GaN device comprising a source (113), a gate (112) and a drain (114); and
a silicon-based diode structure (118) or a silicon-based thin-film resistor (117) (page 29) above the substrate, the silicon-based diode structure or the silicon-based thin-film resistor over the GaN device in a region between the gate and the drain of the GaN device.
Morita does not disclose the component couple to a board to form a computing device. However, Jun discloses a component couple to a board to form a computing device. Note [0037] and Figure 8 of Jun. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to couple the component of Morita to a board, such as taught by Jun et al. in order to integrate multiple devices into a computing device to perform the desired function.
Regarding claims 12 and 17, Morita and Jun et al. disclose the device further comprising: a memory (310,312) coupled to the board [0037].
Regarding claims 13 and 18, Morita and Jun et al. disclose the device further comprising: a communication chip coupled to the board [0037].
Regarding claims 14 and 19, Morita and Jun et al. disclose the device further comprising: a camera (336) coupled to the board [0037].
Regarding claims 15 and 20, Morita and Jun et al. disclose the component is a packaged integrated circuit die (302) [0036].
Regarding claim 16, Morita discloses, as shown in Figures, a component including an integrated circuit structure comprising:
a GaN device on or above a substrate (101), the GaN device comprising a source (113), a gate (112) and a drain (114); and
a silicon-based diode structure (118) or a silicon-based thin-film resistor (117) (page 29) above the substrate, the silicon-based diode structure or the silicon-based thin-film resistor over the GaN device in a region between the gate and the drain of the GaN device.
Morita does not disclose the component couple to a board to form a computing device. However, Jun discloses a component couple to a board to form a computing device. Note [0037] and Figure 8 of Jun. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to couple the component of Morita to a board, such as taught by Jun et al. in order to integrate multiple devices into a computing device to perform the desired function.
Note that the term “fabricated according to a method comprising” is method recitation in a device claimed. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Conclusion
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/HUNG K VU/ Primary Examiner, Art Unit 2897
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