DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings submitted on 12/20/2022 are being considered by the examiner.
Claim Objections
Claims 3, 8 and 13 are objected to because of the following informalities: missing periods at the end of the sentence. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5, 11-13, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. (US 20160380090 A1).
Regarding claim 1, Roberts disclose an integrated circuit structure, comprising: a GaN device (112) on or above a substrate (102), the GaN device (112) comprising a source (120), a gate (126) and a drain (122); ([0104], Fig. 4A)
Roberts does not explicitly disclose:
and a silicon-based clamp structure above substrate, the silicon-based clamp structure over the GaN device in a region that overlaps the source and the gate of the GaN device.
However, Roberts discloses:
and a silicon-based clamp structure (114) above substrate (112), the silicon-based clamp structure over the GaN device (112) in a region that overlaps the source (120) and the gate (126) of the GaN device (112). ([0110], inverted Fig. 4B)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Roberts to include a silicon-based clamp structure above substrate, the silicon-based clamp structure over the GaN device in a region that overlaps the source and the gate of the GaN device in order to have “improved electrical breakdown resistance and effective thermal dissipation compared to conventional GaN-on-Si device structures.” (Roberts, Abstract)
Regarding claim 2, Roberts disclose the integrated circuit structure of claim 1, wherein the GaN device (112) is a lateral GaN power device (per [0003]), or a vertical GaN power device.
Regarding claim 3, Roberts disclose the integrated circuit structure of claim 1, wherein the silicon-based clamp structure (114) comprises a silicon crystal layer (160, made of silicon nitride per [0110]), and wherein the silicon crystal layer (160) is bonded to a dielectric layer (130), the dielectric layer (130) above the GaN device (112). ([0102], inverted Fig. 4C)
Regarding claim 5, Roberts disclose the integrated circuit structure of claim 1, further comprising contacts (140) to the GaN device (112) and to the silicon-based clamp structure (114). ([0082], (Fig. 4C)
Regarding claim 11, Roberts disclose a method of fabricating an integrated circuit structure, the method comprising: forming a GaN device (112) on or above a substrate (102), the GaN device (112) comprising a source (120), a gate (126) and a drain (122); ([0104], Inverted Fig. 4A)
Roberts doesn’t explicitly disclose:
and forming a silicon-based clamp structure above substrate using a layer transfer process, the silicon-based clamp structure formed over the GaN device in a region that overlaps the source and the gate of the GaN device.
However, Roberts does disclose:
forming a silicon-based clamp structure (114) above substrate (102) using a layer transfer process (per [0008]), the silicon-based clamp structure (114) formed over the GaN device (112) in a region that overlaps the source (120) and the gate (126) of the GaN device (112). ([0110], Inverted Fig. 4B)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Roberts for forming a silicon-based clamp structure above substrate using a layer transfer process, the silicon-based clamp structure formed over the GaN device in a region that overlaps the source and the gate of the GaN device in order to have “improved electrical breakdown resistance and effective thermal dissipation compared to conventional GaN-on-Si device structures.” (Roberts, Abstract)
Regarding claim 12, Roberts disclose the method of claim 11, wherein the silicon-based clamp structure(114) comprises a silicon crystal layer (160, made of silicon nitride per [0110]). (Fig. 4B)
Regarding claim 13, Roberts disclose the method of claim 12, wherein the silicon crystal layer (160) is bonded to a dielectric layer (130), the dielectric layer (130) above the GaN device (112). ([0102], Fig. 4C)
Regarding claim 15, Roberts disclose the method of claim 11, further comprising forming contacts (140) to the GaN device (112) and to the silicon-based clamp structure (114). ([0082], Fig. 4C)
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. (US 20160380090 A1) as applied to claims 1 and 11 above respectively, and further in view of Lee et al. (US 20200295045 A1).
Regarding claim 4, Roberts disclose the integrated circuit structure of claim 1, wherein the silicon-based clamp structure (114) comprises a source (S) coupled to the source (120) of the GaN device (112),
Roberts does not disclose:
and wherein the silicon-based clamp structure comprises a drain coupled to the gate of the GaN device.
However, Lee discloses:
the silicon-based clamp structure (109) comprises a drain (unlabeled block connected by 401) coupled to the gate (G) of the GaN device (102). ([0055], Fig. 4)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Roberts and Lee for wherein the silicon-based clamp structure comprises a drain coupled to the gate of the GaN device because it “significantly reduces the parasitic resistance and inductance.” (Lee, [0056])
Regarding claim 14, Roberts disclose the method of claim 11, wherein the silicon-based clamp structure (114) comprises a source (S) coupled to the source (120) of the GaN device (112),
Roberts does not disclose:
and wherein the silicon-based clamp structure comprises a drain coupled to the gate of the GaN device.
However, Lee discloses:
the silicon-based clamp structure (109) comprises a drain (unlabeled block connected by 401) coupled to the gate (G) of the GaN device (102). ([0055], Fig. 4)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Roberts and Lee for wherein the silicon-based clamp structure comprises a drain coupled to the gate of the GaN device in order to “significantly reduces the parasitic resistance and inductance.” (Lee, [0056])
Claims 6-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. (US 20160380090 A1) in view of Casady et al. (US 20020149021 A1).
Regarding claim 6, Roberts disclose an integrated circuit structure, comprising: a device (112) on or above a substrate (102), the device (112) comprising a source (120), a gate (126) and a drain (122); ([0104], Fig. 4A) and a silicon-based clamp structure (114) above substrate (102), the silicon-based clamp structure (114) over the device (112) in a region that overlaps the source (120) and the gate (126) of the device (112). ([0110, inverted Fig. 4B)
Roberts does not disclose using SiC.
However, Casady discloses a SiC device (29) in ([0024], Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Roberts and Lee to use SiC since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Additionally, “SiC-SI isolated substrates using high-power-density vertical SiC power devices that are both much smaller and more thermally stable than silicon-based Smart Power Integrated Circuits (ICs).” (Casady, [0017])
Regarding claim 7, Casady discloses the integrated circuit structure of claim 6, wherein the SiC device (29) is a vertical SiC power device (per [0024]). (Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Casady for similar reasons as stated above.
Regarding claim 8, Roberts disclose the integrated circuit structure of claim 6, wherein the silicon-based clamp structure (114) comprises a silicon crystal layer (160, made of silicon nitride per [0110]), and wherein the silicon crystal layer (160) is bonded to a dielectric layer (130), the dielectric layer (130) above the device (112).
Roberts does not disclose using SiC.
However, Casady discloses a SiC device (29) in ([0024], Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Roberts and Lee to use SiC since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Additionally, “SiC-SI isolated substrates using high-power-density vertical SiC power devices that are both much smaller and more thermally stable than silicon-based Smart Power Integrated Circuits (ICs).” (Casady, [0017])
Regarding claim 10, Roberts disclose the integrated circuit structure of claim 6, further comprising contacts (140) to the device (112) and to the silicon-based clamp structure (114).
Roberts does not disclose using SiC.
However, Casady discloses a SiC device (29) in ([0024], Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Roberts and Lee to use SiC since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Additionally, “SiC-SI isolated substrates using high-power-density vertical SiC power devices that are both much smaller and more thermally stable than silicon-based Smart Power Integrated Circuits (ICs).” (Casady, [0017])
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. (US 20160380090 A1) in view of Casady et al. (US 20020149021 A1) as applied to claim 6 above, and further in view of Lee et al. (US 20200295045 A1).
Regarding claim 9, Roberts disclose the integrated circuit structure of claim 6, wherein the silicon-based clamp structure (114) comprises a source (S) coupled to the source (120) of the device (112),
Roberts does not disclose using SiC.
However, Casady discloses a SiC device (29) in ([0024], Fig. 2)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Roberts and Lee to use SiC since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Additionally, “SiC-SI isolated substrates using high-power-density vertical SiC power devices that are both much smaller and more thermally stable than silicon-based Smart Power Integrated Circuits (ICs).” (Casady, [0017])
Roberts in view of Casady do not disclose:
and wherein the silicon-based clamp structure comprises a drain coupled to the gate of the device.
However, Lee discloses:
the silicon-based clamp structure (109) comprises a drain (unlabeled block connected by 401) coupled to the gate (G) of the device (102). ([0055], Fig. 4)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Roberts, Casady and Lee for wherein the silicon-based clamp structure comprises a drain coupled to the gate of the device because it “significantly reduces the parasitic resistance and inductance.” (Lee, [0056])
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jun et al. (US 20170077281 A1) in view of Roberts et al. (US 20160380090 A1).
Regarding claim 16, Jun disclose a computing device, comprising: a board ([0036]); and a component (per [0036]) coupled to the board (per [0036]), the component (per [0036]) including an integrated circuit structure (302), comprising: a GaN device (100) on or above a substrate (140), the GaN device (100) comprising a source (160), a gate (155) and a drain (165); ([0030], Fig. 6)
Jun does not disclose:
and a silicon-based clamp structure above substrate, the silicon-based clamp structure over the GaN device in a region that overlaps the source and the gate of the GaN device.
However, Roberts discloses:
a silicon-based clamp structure (114) above substrate (102), the silicon-based clamp structure (114) over the GaN device (112) in a region that overlaps the source (120) and the gate (126) of the GaN device (112). ([0110, Fig. 4B)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Roberts to include a silicon-based clamp structure above substrate, the silicon-based clamp structure over the GaN device in a region that overlaps the source and the gate of the GaN device in order to have “improved electrical breakdown resistance and effective thermal dissipation compared to conventional GaN-on-Si device structures.” (Roberts, Abstract)
Regarding claim 17, Jun discloses the computing device of claim 16, further comprising: a memory (306) coupled to the board (per [0036]). ([0037], Fig. 8)
Regarding claim 18, Jun discloses the computing device of claim 16, further comprising: a communication chip (308) coupled to the board (per [0036]). (Fig. 8)
Regarding claim 19, Jun discloses the computing device of claim 16, further comprising: a camera (336) coupled to the board (per [0036]). ([0037], Fig. 8)
Regarding claim 20, Jun discloses the computing device of claim 16, wherein the component (per [0036]) is a packaged integrated circuit die (302). ([0036], Fig. 8)
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Saito et al. (US 20080277692 A1) discloses a GaN semiconductor device (22) and a clamp diode (21) in Fig. 5-10 but does not disclose all the limitations as required by the claim.
Conclusion
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/ASHLEY NICOLE BLACKWELL/
Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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