DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-21 are pending in this application. Claims 1, 7, 12 and 17 are amended in the amendment received 7/7/26.
Response to Arguments
Applicant's arguments filed 7/7/26 have been fully considered but are moot in view of the new ground(s) of rejection.
Information Disclosure Statement
An information disclosure statement has not been received. If the applicant is aware of any prior art or any other co-pending applications not already of record, he/she is reminded of his/her duty under 37 CFR 1.56 to disclose the same.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3-13 and 17-18 are rejected under pre-AIA 35 U.S.C. 102(a)(1) as being anticipated by Dutta et al. (US Patent Application Publication No 2021/0151428) hereinafter referred to as Dutta.
Per Claim 1 Dutta discloses a integrated circuit structure device (see fig. 6), comprising
a GaN device (210) on or above a substrate (214), the GaN device comprising a source (S), a gate (G) and a drain (D); (see figure 6) and
a silicon-based transistor structure (212) above substrate, the silicon-based transistor [0058] structure at a level above the gate of the GaN device in a region (region 204) outside of the GaN device (GaN/210 is in region (202); see figure 6), wherein there is no GaN device vertically beneath the silicon-based transistor. (as clearly shown in figure 6).
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Per Claim 3 Dutta discloses the device of claim 1, (see figure 6) including where the silicon-based transistor structure (212) comprises a silicon crystal layer (242). ([0053] teaches that (212) may be formed in the wafer (242) which is silicon (100)).
Per Claim 4 Dutta discloses the device of claim 3, (see figure 6) including where the silicon crystal layer (242) is bonded to a dielectric layer, the dielectric layer (244) above the GaN device (as in figure 6)
Per Claim 5 Dutta discloses the device of claim 1, (see figure 6) including where the silicon-based transistor structure comprises a source (254), a gate (258), and a drain (256).
Per Claim 6 Dutta discloses the device of claim 1, (see figure 6) including contacts (252) to the GaN device (252, left) and to the silicon-based transistor structure (252, right).
Per Claim 7 Dutta discloses a method of fabricating an integrated circuit structure device (see fig. 2), the method comprising
forming a GaN device (210) on or above a substrate (214), the GaN device comprising a source (S), a gate (G) and a drain (D); (see figure 6) and
forming a silicon-based transistor structure (212) above substrate using a layer transfer process [0061], the silicon-based transistor [0058] structure at a level above the gate of the GaN device in a region (region 204) outside of the GaN device (GaN/210 is in region (202); see figure 6), wherein there is no GaN device vertically beneath the silicon-based transistor. (as clearly shown in figure 6).
Per Claim 8 Dutta discloses the device of claim 7, (see figure 6) including where the silicon-based transistor structure (212) comprises a silicon crystal layer (242). ([0053] teaches that (212) may be formed in the wafer (242) which is silicon (100)).
Per Claim 9 Dutta discloses the device of claim 8, (see figure 6) including where the silicon crystal layer (242) is bonded to a dielectric layer, the dielectric layer (244) above the GaN device (as in figure 6).
Per Claim 10 Dutta discloses the device of claim 7, (see figure 6) including where the silicon-based transistor structure comprises a source (254), a gate (258), and a drain (256)
Per Claim 11 Dutta discloses the device of claim 7, (see figure 6) including forming contacts (252) to the GaN device (252, left) and to the silicon-based transistor structure (252, right).
Per Claim 12 Dutta discloses a computing device ([0024] describes that the RF front-end (100) typically includes electronic components such as control logic, switches, digital circuits, etc, and figure 1 shows that it includes memory and a controller. This is clearly a computing device, though that specific terminology is not used by Dutta) comprising: a board (PCB see [0055]); and a component (200) coupled to the board, the component (200) including an integrated circuit structure (see fig. 2), comprising
a GaN device (210) on or above a substrate (214), the GaN device comprising a source (S), a gate (G) and a drain (D); (see figure 6) and
a silicon-based transistor structure (212) above substrate, the silicon-based transistor [0058] structure at a level above the gate of the GaN device in a region (region 204) outside of the GaN device (GaN/210 is in region (202); see figure 6), wherein there is no GaN device vertically beneath the silicon-based transistor. (as clearly shown in figure 6).
Per Claim 13 Dutta discloses the device of claim 12, (see figure 6) including a memory (138) coupled to the board (shown in figure 1).
Per Claim 17 Dutta discloses a computing device ([0024] describes that the RF front-end (100) typically includes electronic components such as control logic, switches, digital circuits, etc, and figure 1 shows that it includes memory and a controller. This is clearly a computing device, though that specific terminology is not used by Dutta) comprising: a board (PCB see [0055]); and a component (200) coupled to the board, the component (200) including an integrated circuit structure (see fig. 2), the integrated circuit structure fabricated according to a method comprising:
forming a GaN device (210) on or above a substrate (214), the GaN device comprising a source (S), a gate (G) and a drain (D); (see figure 6) and
forming a silicon-based transistor structure (212) above substrate using a layer transfer process [0061], the silicon-based transistor [0058] structure at a level above the gate of the GaN device in a region (region 204) outside of the GaN device (GaN/210 is in region (202); see figure 6), wherein there is no GaN device vertically beneath the silicon-based transistor. (as clearly shown in figure 6).
The examiner notes that the limitations are "product-by-process" limitations (i.e. the integrated circuit structure fabricated according to a method comprising: forming a GaN device on or above a substrate, the GaN device comprising a source, a gate and a drain; and forming a silicon-based transistor structure above substrate using a layer transfer process, the silicon-based transistor structure formed at a level above the gate of the GaN device in a region outside of the GaN device). While product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Hirao, 190 USPQ 15 at 17(footnote 3). The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) See also in re Brown, 173 USPQ 685: In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324: In re Avery, 186 USPQ 116 in re Wertheim, 191 USPQ 90 (209 USPQ 254 does not deal with this issue); and In re Marosi et al, 218 USPQ 289 final product per se which must be determined in a "product by, all of" claim, and not the patentability of the process, and that an old or obvious product, whether claimed in "product by process" claims or not. Note that Applicant has the burden of proof in such cases, as the above case law makes clear.
Per Claim 18 Dutta discloses the device of claim 17, (see figure 6) including a memory (138) coupled to the board (shown in figure 1).
Claim Rejections - 35 USC § 103
Claims 14-16 and 19-21 are rejected under pre-AIA 35 U.S.C. 103 as being unpatentable over Dutta as above, and further in view of Trivedi et al. (US Patent Application Publication No 2021/0280683) hereinafter referred to as Trivedi.
Per Claim 14 Dutta discloses the device of claim 12, (see figure 6) including the board (shown in figure 1).
Dutta does not teach a communication chip coupled to the board.
Trivedi teaches an analogous device including a communication chip (1006) coupled to the board (see figure 18).
All of the component parts are known in Dutta and Trivedi. The only difference is the combination of the old elements into a single device, by using the communication chip of Trivedi in the device of Dutta. It would have been obvious to one having ordinary skill in the art at the time the invention was made to use the communication chip of Trivedi in the device of Dutta, since a person with ordinary skill has good reason to pursue the known options within his or her technical grasp. KSR International Co. v. Teleflex Inc., 550 U.S.--, 82 USPQ2d 1385 (2007).
Per Claim 15 Dutta discloses the device of claim 12, (see figure 6) including the board (shown in figure 1).
Dutta does not teach a camera coupled to the board
Trivedi teaches an analogous device including a camera [0147] coupled to the board. (see figure 18).
All of the component parts are known in Dutta and Trivedi. The only difference is the combination of the old elements into a single device, by using the camera of Trivedi in the device of Dutta. It would have been obvious to one having ordinary skill in the art at the time the invention was made to use the camera of Trivedi in the device of Dutta, since a person with ordinary skill has good reason to pursue the known options within his or her technical grasp. KSR International Co. v. Teleflex Inc., 550 U.S.--, 82 USPQ2d 1385 (2007).
Per Claim 16 Dutta discloses the device of claim 12, (see figure 6) including the board (shown in figure 1).
Dutta does not teach where the component is a packaged integrated circuit die
Trivedi teaches an analogous device including where the component is a packaged integrated circuit die [0182].
All of the component parts are known in Dutta and Trivedi. The only difference is the combination of the old elements into a single device, by using the packaged integrated circuit die of Trivedi in the device of Dutta. It would have been obvious to one having ordinary skill in the art at the time the invention was made to use the packaged integrated circuit die of Trivedi in the device of Dutta, since a person with ordinary skill has good reason to pursue the known options within his or her technical grasp. KSR International Co. v. Teleflex Inc., 550 U.S.--, 82 USPQ2d 1385 (2007).
Per Claim 19 Dutta discloses the device of claim 17, (see figure 6) including the board (shown in figure 1).
Dutta does not teach a communication chip coupled to the board.
Trivedi teaches an analogous device including a communication chip (1006) coupled to the board (see figure 18).
All of the component parts are known in Dutta and Trivedi. The only difference is the combination of the old elements into a single device, by using the communication chip of Trivedi in the device of Dutta. It would have been obvious to one having ordinary skill in the art at the time the invention was made to use the communication chip of Trivedi in the device of Dutta, since a person with ordinary skill has good reason to pursue the known options within his or her technical grasp. KSR International Co. v. Teleflex Inc., 550 U.S.--, 82 USPQ2d 1385 (2007).
Per Claim 20 Dutta discloses the device of claim 17, (see figure 6) including the board (shown in figure 1).
Dutta does not teach a camera coupled to the board
Trivedi teaches an analogous device including a camera [0147] coupled to the board. (see figure 18).
All of the component parts are known in Dutta and Trivedi. The only difference is the combination of the old elements into a single device, by using the camera of Trivedi in the device of Dutta. It would have been obvious to one having ordinary skill in the art at the time the invention was made to use the camera of Trivedi in the device of Dutta, since a person with ordinary skill has good reason to pursue the known options within his or her technical grasp. KSR International Co. v. Teleflex Inc., 550 U.S.--, 82 USPQ2d 1385 (2007).
Per Claim 21 Dutta discloses the device of claim 17, (see figure 6) including the board (shown in figure 1).
Dutta does not teach where the component is a packaged integrated circuit die
Trivedi teaches an analogous device including where the component is a packaged integrated circuit die [0182].
All of the component parts are known in Dutta and Trivedi. The only difference is the combination of the old elements into a single device, by using the packaged integrated circuit die of Trivedi in the device of Dutta. It would have been obvious to one having ordinary skill in the art at the time the invention was made to use the packaged integrated circuit die of Trivedi in the device of Dutta, since a person with ordinary skill has good reason to pursue the known options within his or her technical grasp. KSR International Co. v. Teleflex Inc., 550 U.S.--, 82 USPQ2d 1385 (2007).
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMI VALENTINE MILLER whose telephone number is (571)272-9786. The examiner can normally be reached on Monday-Thursday 7am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jami Valentine Miller/Primary Examiner, Art Unit 2818
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