DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-21 are pending in this application.
Drawings
There are no objections or rejections to the drawings.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
An information disclosure statement has not been received. If the applicant is aware of any prior art or any other co-pending applications not already of record, he/she is reminded of his/her duty under 37 CFR 1.56 to disclose the same.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-13 and 17-18 are rejected under pre-AIA 35 U.S.C. 102(a)(1) as being anticipated by Dutta et al. (US Patent Application Publication No 2021/0151428) hereinafter referred to as Dutta.
Per Claim 1 Dutta discloses a integrated circuit structure device (see fig. 2), comprising
a GaN device (210) on or above a substrate (214), the GaN device comprising a source (S), a gate (G) and a drain (D); (see figure 2) and
a silicon-based transistor structure (212) above substrate, the silicon-based transistor [0058] structure at a level above the gate of the GaN device in a region (region 204) outside of the GaN device (GaN/210 is in region (202); see figure 2).
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Per Claim 3 Dutta discloses the device of claim 1, (see figure 2) including where the silicon-based transistor structure (212) comprises a silicon crystal layer (242). ([0053] teaches that (212) may be formed in the wafer (242) which is silicon (100)).
Per Claim 4 Dutta discloses the device of claim 3, (see figure 2) including where the silicon crystal layer (242) is bonded to a dielectric layer, the dielectric layer (244) above the GaN device(as in figure 2)
Per Claim 5 Dutta discloses the device of claim 1, (see figure 2) including where the silicon-based transistor structure comprises a source (254), a gate (258), and a drain (256).
Per Claim 6 Dutta discloses the device of claim 1, (see figure 2) including contacts (252) to the GaN device (252, left) and to the silicon-based transistor structure (252, right).
Per Claim 7 Dutta discloses a method of fabricating an integrated circuit structure device (see fig. 2), the method comprising
forming a GaN device (210) on or above a substrate (214), the GaN device comprising a source (S), a gate (G) and a drain (D); (see figure 2) and
forming a silicon-based transistor structure (212) above substrate using a layer transfer process [0061], the silicon-based transistor [0058] structure at a level above the gate of the GaN device in a region (region 204) outside of the GaN device (GaN/210 is in region (202); see figure 2).
Per Claim 8 Dutta discloses the device of claim 7, (see figure 2) including where the silicon-based transistor structure (212) comprises a silicon crystal layer (242). ([0053] teaches that (212) may be formed in the wafer (242) which is silicon (100)).
Per Claim 9 Dutta discloses the device of claim 8, (see figure 2) including where the silicon crystal layer (242) is bonded to a dielectric layer, the dielectric layer (244) above the GaN device (as in figure 2).
Per Claim 10 Dutta discloses the device of claim 7, (see figure 2) including where the silicon-based transistor structure comprises a source (254), a gate (258), and a drain (256)
Per Claim 11 Dutta discloses the device of claim 7, (see figure 2) including forming contacts (252) to the GaN device (252, left) and to the silicon-based transistor structure (252, right).
Per Claim 12 Dutta discloses a computing device ([0024] describes that the RF front-end (100) typically includes electronic components such as control logic, switches, digital circuits, etc, and figure 1 shows that it includes memory and a controller. This is clearly a computing device, though that specific terminology is not used by Dutta) comprising: a board (PCB see [0055]); and a component (200) coupled to the board, the component (200) including an integrated circuit structure (see fig. 2), comprising
a GaN device (210) on or above a substrate (214), the GaN device comprising a source (S), a gate (G) and a drain (D); (see figure 2) and
a silicon-based transistor structure (212) above substrate, the silicon-based transistor [0058] structure at a level above the gate of the GaN device in a region (region 204) outside of the GaN device (GaN/210 is in region (202); see figure 2).
Per Claim 13 Dutta discloses the device of claim 12, (see figure 2) including a memory (138) coupled to the board (shown in figure 1).
Per Claim 17 Dutta discloses a computing device ([0024] describes that the RF front-end (100) typically includes electronic components such as control logic, switches, digital circuits, etc, and figure 1 shows that it includes memory and a controller. This is clearly a computing device, though that specific terminology is not used by Dutta) comprising: a board (PCB see [0055]); and a component (200) coupled to the board, the component (200) including an integrated circuit structure (see fig. 2), the integrated circuit structure fabricated according to a method comprising:
forming a GaN device (210) on or above a substrate (214), the GaN device comprising a source (S), a gate (G) and a drain (D); (see figure 2) and
forming a silicon-based transistor structure (212) above substrate using a layer transfer process [0061], the silicon-based transistor [0058] structure at a level above the gate of the GaN device in a region (region 204) outside of the GaN device (GaN/210 is in region (202); see figure 2).
The examiner notes that the limitations are "product-by-process" limitations (i.e. the integrated circuit structure fabricated according to a method comprising: forming a GaN device on or above a substrate, the GaN device comprising a source, a gate and a drain; and forming a silicon-based transistor structure above substrate using a layer transfer process, the silicon-based transistor structure formed at a level above the gate of the GaN device in a region outside of the GaN device). While product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Hirao, 190 USPQ 15 at 17(footnote 3). The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) See also in re Brown, 173 USPQ 685: In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324: In re Avery, 186 USPQ 116 in re Wertheim, 191 USPQ 90 (209 USPQ 254 does not deal with this issue); and In re Marosi et al, 218 USPQ 289 final product per se which must be determined in a "product by, all of" claim, and not the patentability of the process, and that an old or obvious product, whether claimed in "product by process" claims or not. Note that Applicant has the burden of proof in such cases, as the above case law makes clear.
Per Claim 18 Dutta discloses the device of claim 17, (see figure 2) including a memory (138) coupled to the board (shown in figure 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 14-16 and 19-21 are rejected under pre-AIA 35 U.S.C. 103 as being unpatentable over Dutta as above, and further in view of Trivedi et al. (US Patent Application Publication No 2021/0280683) hereinafter referred to as Trivedi.
Per Claim 14 Dutta discloses the device of claim 12, (see figure 2) including the board (shown in figure 1).
Dutta does not teach a communication chip coupled to the board.
Trivedi teaches an analogous device including a communication chip (1006) coupled to the board (see figure 18).
All of the component parts are known in Dutta and Trivedi. The only difference is the combination of the old elements into a single device, by using the communication chip of Trivedi in the device of Dutta. It would have been obvious to one having ordinary skill in the art at the time the invention was made to use the communication chip of Trivedi in the device of Dutta, since a person with ordinary skill has good reason to pursue the known options within his or her technical grasp. KSR International Co. v. Teleflex Inc., 550 U.S.--, 82 USPQ2d 1385 (2007).
Per Claim 15 Dutta discloses the device of claim 12, (see figure 2) including the board (shown in figure 1).
Dutta does not teach a camera coupled to the board
Trivedi teaches an analogous device including a camera [0147] coupled to the board. (see figure 18).
All of the component parts are known in Dutta and Trivedi. The only difference is the combination of the old elements into a single device, by using the camera of Trivedi in the device of Dutta. It would have been obvious to one having ordinary skill in the art at the time the invention was made to use the camera of Trivedi in the device of Dutta, since a person with ordinary skill has good reason to pursue the known options within his or her technical grasp. KSR International Co. v. Teleflex Inc., 550 U.S.--, 82 USPQ2d 1385 (2007).
Per Claim 16 Dutta discloses the device of claim 12, (see figure 2) including the board (shown in figure 1).
Dutta does not teach where the component is a packaged integrated circuit die
Trivedi teaches an analogous device including where the component is a packaged integrated circuit die [0182].
All of the component parts are known in Dutta and Trivedi. The only difference is the combination of the old elements into a single device, by using the packaged integrated circuit die of Trivedi in the device of Dutta. It would have been obvious to one having ordinary skill in the art at the time the invention was made to use the packaged integrated circuit die of Trivedi in the device of Dutta, since a person with ordinary skill has good reason to pursue the known options within his or her technical grasp. KSR International Co. v. Teleflex Inc., 550 U.S.--, 82 USPQ2d 1385 (2007).
Per Claim 19 Dutta discloses the device of claim 17, (see figure 2) including the board (shown in figure 1).
Dutta does not teach a communication chip coupled to the board.
Trivedi teaches an analogous device including a communication chip (1006) coupled to the board (see figure 18).
All of the component parts are known in Dutta and Trivedi. The only difference is the combination of the old elements into a single device, by using the communication chip of Trivedi in the device of Dutta. It would have been obvious to one having ordinary skill in the art at the time the invention was made to use the communication chip of Trivedi in the device of Dutta, since a person with ordinary skill has good reason to pursue the known options within his or her technical grasp. KSR International Co. v. Teleflex Inc., 550 U.S.--, 82 USPQ2d 1385 (2007).
Per Claim 20 Dutta discloses the device of claim 17, (see figure 2) including the board (shown in figure 1).
Dutta does not teach a camera coupled to the board
Trivedi teaches an analogous device including a camera [0147] coupled to the board. (see figure 18).
All of the component parts are known in Dutta and Trivedi. The only difference is the combination of the old elements into a single device, by using the camera of Trivedi in the device of Dutta. It would have been obvious to one having ordinary skill in the art at the time the invention was made to use the camera of Trivedi in the device of Dutta, since a person with ordinary skill has good reason to pursue the known options within his or her technical grasp. KSR International Co. v. Teleflex Inc., 550 U.S.--, 82 USPQ2d 1385 (2007).
Per Claim 21 Dutta discloses the device of claim 17, (see figure 2) including the board (shown in figure 1).
Dutta does not teach where the component is a packaged integrated circuit die
Trivedi teaches an analogous device including where the component is a packaged integrated circuit die [0182].
All of the component parts are known in Dutta and Trivedi. The only difference is the combination of the old elements into a single device, by using the packaged integrated circuit die of Trivedi in the device of Dutta. It would have been obvious to one having ordinary skill in the art at the time the invention was made to use the packaged integrated circuit die of Trivedi in the device of Dutta, since a person with ordinary skill has good reason to pursue the known options within his or her technical grasp. KSR International Co. v. Teleflex Inc., 550 U.S.--, 82 USPQ2d 1385 (2007).
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicants are directed to consider additional pertinent prior art included on the Notice of References Cited (PTOL 892) attached herewith.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMI VALENTINE MILLER whose telephone number is (571)272-9786. The examiner can normally be reached on Monday-Thursday 7am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jami Valentine Miller/Primary Examiner, Art Unit 2818
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