DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims presented have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,2,7-9,11-13,16,17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20210005593A1) in view of KANAMORI et al. (US20200203329A1).
Regarding claim 1, Annotated Fig.23 of Lee teaches a non-volatile memory device, comprising: a first semiconductor layer CELL (para.0052) that includes:
a first memory cell array STR1 (Fig.2, para.0052) that is disposed on a first cell region ML1 (para.0172) of the first semiconductor layer CELL, wherein the first memory cell array STR1 includes a first plurality of word lines WL1-WL4 (para.0047) stacked in a vertical direction and a first plurality of memory cells MC1-MC4 (para.0047) respectively coupled to the first plurality of word lines WL1-WL4;
a second memory cell array STR2 (Fig.2, para.0052) that is disposed on a second cell region ML2 (para.0172) of the first semiconductor layer CELL, wherein the second memory cell array STR2 includes a second plurality of word lines WL5-WL8 (para.0047) stacked in the vertical direction and a second plurality of memory cells MC5-MC8 (para.0047) respectively coupled to the second plurality of word lines WL5-WL8; and a first metal pad MBPD3/MBPD4 (para.0172); and a second semiconductor layer PERI (para.0172) that includes:
a first peripheral circuit (see annotated Fig.23) coupled to the first memory cell array STR1;
a second peripheral circuit (see annotated Fig.23) coupled to the second memory cell array STR2; and a second metal pad MBPD1/MBPD2 (para.0172), wherein the second semiconductor layer PERI is coupled, in the vertical direction, to the first semiconductor layer by the first metal pad MBPD3/MBPD4 and the second metal pad MBPD1/MBPD2 in a bonding manner,
wherein the first peripheral circuit includes:
a first peripheral circuit that overlaps the first cell region ML1 in the vertical direction,
a second circuit (see annotated Fig.23) that does not overlap the first cell region ML1 in the vertical direction,
wherein the second peripheral circuit includes:
a third circuit that (see annotated Fig.23) overlaps the second cell region ML2 in the vertical direction, and
a fourth circuit (see annotated Fig.23) that does not overlap the second cell region ML2 in the vertical direction.
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Lee does not teach wherein the first memory cell array and the second memory cell array are spaced apart from each other in a horizontal direction.
Fig.3 of KANAMORI teaches wherein memory cell arrays MCA1 and MCA2 may include first and second memory cell arrays MCA1 and MCA2 stacked vertically, and each of the first and second memory cell arrays MCA1 and MCA2 may be spaced apart from each other and disposed on the same plane; the first memory cell array and the second memory cell array can be spaced in a horizontal direction (para.0042).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first memory cell array and the second memory cell array are spaced apart from each other in a horizontal direction, as taught by KANAMORI, in order to provide a larger footprint for external electrical connections.
Regarding claim 2, Lee further teaches the non-volatile memory device of claim 1, wherein the first peripheral circuit (see annotated Fig.23) includes a first page buffer circuit 2393 (para.0157),
wherein the first circuit corresponds (see annotated Fig.23) to a portion of the first page buffer circuit 2393, wherein the second circuit (see annotated Fig.23) corresponds to another portion of the first page buffer circuit 2393,
wherein the second peripheral circuit (see annotated Fig.23) includes a second page buffer circuit (see annotated Fig.23),
wherein the third circuit (see annotated Fig.23) corresponds to a portion of the second page buffer circuit, and
wherein the fourth circuit (see annotated Fig.23) corresponds to another portion of the second page buffer circuit.
Regarding claim 7, Lee further teaches the non-volatile memory device of claim 2, wherein the first page buffer circuit 2393 (para.0157) includes a page buffer decoder 2394 (para.0159) configured to address and drive the first memory cell array STR1 (Fig.2, para.0052), and
wherein the second circuit (see annotated Fig.23) includes the page buffer decoder 2394.
Regarding claim 8, Lee further teaches the non-volatile memory device of claim 2, wherein the first peripheral circuit (see annotated Fig.23) further includes a first row decoder 2394 (para.0159),
wherein the first circuit (see annotated Fig.23) includes a portion of the first row decoder 2394,
wherein the second circuit (see annotated Fig.23) includes another portion of the first row decoder 2394, wherein the second peripheral circuit (see annotated Fig.23) further includes a second row decoder 2394,
wherein the third circuit (see annotated Fig.23) includes a portion of the second row decoder 2394, and wherein the fourth circuit (see annotated Fig.23) includes another portion of the second row decoder 2394.
Regarding claim 9, Lee further teaches the non-volatile memory device of claim 2, wherein the first semiconductor layer CELL (para.0146) further includes a row decoder 2394 (para.0159) coupled to the first plurality of word lines W1-W4 (para.0047), and
wherein the second circuit (see annotated Fig.23) overlaps the row decoder 2394 in the vertical direction.
Regarding claim 11, Lee further teaches the non-volatile memory device of claim 1, wherein the first peripheral circuit (see annotated Fig.23) includes a row decoder 2394 (para.0159) coupled to the first plurality of word lines W1-W4 (para.0047), wherein the first circuit corresponds to a portion of the row decoder 2394, and
wherein the second circuit (see annotated Fig.23) corresponds to another portion of the row decoder 2394.
Regarding claim 12, Lee further teaches the non-volatile memory device of claim 11, wherein the first semiconductor layer CELL (para.0146) further includes a page buffer circuit 2393 (para.0157) coupled to the first plurality of memory cells MC1-MC4 (para.0047) through a plurality of bit lines 2360c (para.0157), and
wherein the second circuit (see annotated Fig.23) overlaps the page buffer circuit 2393 in the vertical direction.
Regarding claim 13, Lee further teaches the non-volatile memory device of claim 1, wherein the second semiconductor layer PERI (para.0145) further includes a pad region in which a plurality of bonding pads MBPD1/MBPD2 (para.0172) are disposed, and wherein the pad region does not overlap the first cell region ML1 (para.0172) and the second cell region ML2 (para.0172).
Regarding claim 16, Lee further teaches the non-volatile memory device of claim 1, wherein the second semiconductor layer PERI (para.0145) further includes an external peripheral circuit 120 (para.0035) including a data input/output buffer (para.0035), and
wherein the external peripheral circuit 120 does not overlap the first cell region ML1 (para.0172) and the second cell region ML2 (para.0172).
Regarding claim 17, Lee further teaches the non-volatile memory device of claim 1, wherein the first peripheral circuit (see annotated Fig.23) includes a first page buffer circuit 2393 (para.0157) and a second page buffer circuit (see annotated Fig.23) that are coupled to the first memory cell array STR1 (para.0052),
wherein the first page buffer circuit 2393 completely overlaps the first cell region ML1 (para.0172) in the vertical direction, and wherein the second page buffer circuit partially overlaps the first cell region ML1 in the vertical direction.
Regarding claim 19, Lee further teaches the non-volatile memory device of claim 1, wherein the first peripheral circuit (see annotated Fig.23) includes a first page buffer circuit 2393 (para.0157) and a second page buffer circuit (see annotated Fig.23) that are coupled to the first memory cell array STR1 (para.0052), and
wherein the first page buffer circuit 2393 and the second page buffer circuit partially overlap the first cell region ML1 (para.0172) in the vertical direction.
Claims 10, 24 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20210005593A1) in view of Kim et al. (US 20220005820A1).
Regarding claim 10, Lee does not teach wherein the first semiconductor layer further includes a pass transistor circuit coupled to the first plurality of word lines,
wherein the first peripheral circuit further includes a row decoder coupled to the pass transistor circuit, and
wherein the second circuit overlaps the pass transistor circuit in the vertical direction.
Figs.1, 4C and 4D of Kim teach a memory device that includes a row decoder (X-DEC) 121. The row decoder (X-DEC) 121 may include a pass transistor circuit and a block switch circuit. The pass transistor circuit may include a plurality of pass transistor groups. The plurality of pass transistor groups may be coupled to the plurality of memory blocks BLK, respectively. Each pass transistor group may be coupled to a corresponding memory block BLK through a plurality of word lines WL (para.0031).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Kim’s pass transistor circuit, with pass transistors disposed in a plurality of columns in an extending direction of the word lines WL, in the teachings of Lee because as the number of the word lines WL increases due to a demand for high capacity, the number of pass transistors of the row decoder 121 is also increasing and thus the occupation area of the row decoder 121 is increasing (Kim, [para.0036]).
Regarding claim 24, Annotated Fig.23 of Lee teaches a non-volatile memory device, comprising:
a first semiconductor layer CELL (para.0146) that includes a cell region ML1 (para.0172) on which a memory cell array STR1 (para.0052) is disposed, and a first metal pad MBPD3/MBPD4 (para.0172), wherein the memory cell array STR1 includes a plurality of word lines WL1-WL4 (para.0047) stacked in a vertical direction and a plurality of memory cells MC1-MC4 (Fig.2, para.0047) respectively coupled to the plurality of word lines WL1-WL4; and
a second semiconductor layer PERI (para.0172) that includes a peripheral circuit region (see annotated Fig.23) on which a peripheral circuit (see annotated Fig.23) is disposed, and a second metal pad MBPD1/MBPD2 (para.0172), wherein the second semiconductor layer PERI is coupled, in the vertical direction, to the first semiconductor layer CELL by the first metal pad MBPD3/MBPD4 and the second metal pad MBPD1/MBPD2 (para.0172) in a bonding manner,
wherein the peripheral circuit region (see annotated Fig.23) includes a first peripheral circuit region (see annotated Fig.23) that overlaps the cell region ML1 in the vertical direction, and a second peripheral circuit region (see annotated Fig.23) that does not overlap the cell region ML1 in the vertical direction,
wherein an area of the peripheral circuit region (see annotated Fig.23) is greater than an area of the cell region ML1,
wherein the peripheral circuit further includes a row decoder 2394 (Fig.19, para.0159) connected to the plurality of word lines WL1-WL4,
wherein a portion of the row decoder 2394 is arranged in the first peripheral circuit region,
wherein another portion of the row decoder 2394 is arranged in the second peripheral circuit region (see annotated Fig.23).
Lee does not teach wherein the first semiconductor layer further includes a pass transistor circuit coupled to the plurality of word lines and overlapping the second peripheral circuit region in the vertical direction.
Figs.1, 4C and 4D of Kim teach a memory device that includes a row decoder (X-DEC) 121. The row decoder (X-DEC) 121 may include a pass transistor circuit and a block switch circuit. The pass transistor circuit may include a plurality of pass transistor groups. The plurality of pass transistor groups may be coupled to the plurality of memory blocks BLK, respectively. Each pass transistor group may be coupled to a corresponding memory block BLK through a plurality of word lines WL (para.0031).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Kim’s pass transistor circuit, with pass transistors disposed in a plurality of columns in an extending direction of the word lines WL, in the teachings of Lee because as the number of the word lines WL increases due to a demand for high capacity, the number of pass transistors of the row decoder 121 is also increasing and thus the occupation area of the row decoder 121 is increasing (Kim, [para.0036]).
Regarding claim 25, Annotated Fig.23 of Lee teaches the non-volatile memory device of claim 1, wherein the first semiconductor layer CELL (para.0146) further includes:
A third peripheral circuit (see annotated Fig.23) coupled to the first memory cell array STR1 (Fig.2, para.0052) and overlapping the first peripheral circuit (see annotated Fig.23) of the second semiconductor layer PERI (para.0172) in the vertical direction.
Allowable Subject Matter
Claims 3-6,18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The combination of prior arts US20210005593A1 and US20200203329A1 teaches the limitations of claims 1-13, 16-20 and 24 of which claims 3-6 and 18 depend on. However, the prior art fails to indicate the location of sensing latch, force latch and cache latch as disclosed in claims 3-6,18 and 20.
Prior Art
The prior arts made of record in the attached PTO-892 Form discuss similar inventive concept of the claimed invention. However, the prior arts fail to either singularly or in combination fail to anticipate or render obvious the limitations of claims 3-6, 18 and 20 regarding the location of the sensing latch, force latch and cache latch.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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