DETAILED ACTION
In view of the appeal brief filed on January 6, 2026, PROSECUTION IS HEREBY REOPENED. New grounds of rejection are set forth below.
To avoid abandonment of the application, appellant must exercise one of the following two options:
(1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113 (if this Office action is final); or,
(2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid.
A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing below:
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 11 is objected to because of the following informalities: on line 6, the term ‘first die’ should be ‘second die’; and on line 9, the term ‘first die’ should be ‘third die’. Appropriate correction is required. Claims 12-16 are also objected to due to their dependency.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7, 10-13, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Braunisch et al. (United States Patent Application Publication No. US 2010/0327424 A1, hereinafter “Braunisch”).
In reference to claim 1, Braunisch discloses a similar device. Figure 16 (the structure in the lower right corner: one bridge with four dies) in conjunction with figures 6-9 disclose a semiconductor package comprising a semiconductor package substrate (610, 710, 910). A multi-die interconnect bridge (540) is coupled to the package substrate (610, 710,910). Figure 16 (the structure in the lower right corner) shows a first die (upper left die in lower right corner structure in figure 16) over a first portion of the package substrate and over a first portion of the multi-die interconnect bridge (note darker die beneath all of the four dies); the first die (upper left die in lower right corner structure in figure 16) is electrically coupled to the multi-die interconnect bridge (p. 3, paragraph 35, p. 8, paragraph 77). A second die (upper right die in lower right corner structure in figure 16) is over a second portion of the package substrate and over a second portion of the multi-die interconnect bridge; the second die is electrically coupled to the multi-die interconnect bridge (p. 3, paragraph 35, p. 8, paragraph 77). A third die (lower right die in lower right corner structure in figure 16) is over a third portion of the package substrate and over a third portion of the multi-die interconnect bridge; the third die is electrically coupled to the multi-die interconnect bridge (p. 3, paragraph 35, p. 8, paragraph 77). The third die (lower right die in lower right corner structure in figure 16) is diagonally opposed to the first die (upper left die in lower right corner structure in figure 16) across the multi-die interconnect bridge. The third die (lower right die in lower right corner structure in figure 16) is electrically connected to the first die (upper left die in lower right corner structure in figure 16) by the multi-die interconnect bridge (540, p. 3, paragraph 35, p. 8, paragraph 77). A fourth die (lower left die in lower right corner structure in figure 16) is over a fourth portion of the package substrate and over a fourth portion of the multi-die interconnect bridge; the fourth die (lower left die in lower right corner structure in figure 16) is electrically coupled to the multi-die interconnect bridge (540, p. 3, paragraph 35, p. 8, paragraph 77).
Braunisch does not explicitly state that the third die (lower right die in lower right corner structure in figure 16) is directly electrically connected to the first die (upper left die in lower right corner structure in figure 16). However Braunisch discloses that using a bridge between two dies/dice provides the benefit of high-speed, high-density connectivity between them (p. 2, paragraph 28, p. 7, paragraphs 70-71, p. 8, paragraph 86) which is desirable in the art (p. 1, paragraph 2, p. 2, paragraph 25). In view of Braunisch, it would therefore be obvious to directly electrically connect the third die and the first die with the multi-die interconnect bridge.
With regard to claim 2, the first die (upper left die in lower right corner structure in figure 16) is directly electrically connected to the second die (upper right die in lower right corner structure in figure 16) by the multi-die interconnect bridge (540, p. 3, paragraph 35, p. 8, paragraph 77).
In reference to claim 3, the first die (upper left die in lower right corner structure in figure 16) is directly electrically connected to the fourth die (lower left die in lower right corner structure in figure 16) by the multi-die interconnect bridge (540, p. 3, paragraph 35, p. 8, paragraph 77).
In reference to claim 5, the first die (upper left die in lower right corner structure in figure 16) and the third die (lower right die in lower right corner structure in figure 16) have a same size.
With regard to claim 7, the first die (upper left die in lower right corner structure in figure 16), the second die (upper right die in lower right corner structure in figure 16), the third die (lower right die in lower right corner structure in figure 16), and the fourth die (lower left die in lower right corner structure in figure 16) all have a same size.
In reference to claim 10, the first die (upper left die in lower right corner structure in figure 16), the second die (upper right die in lower right corner structure in figure 16), the third die (lower right die in lower right corner structure in figure 16), and the fourth die (lower left die in lower right corner structure in figure 16) are coupled to a first side of the package substrate (610, 710, 910). A plurality of bumps (p. 2, paragraph 28) are coupled to a second side of the package substrate (610, 710, 910) with the second side being opposite to the first side.
In reference to claim 11, Braunisch discloses a method which meets the claim. Figure 16 (the structure in the lower right corner: one bridge with four dies) in conjunction with figures 6-9 disclose a method of fabricating a semiconductor package which comprises coupling a multi-die interconnect bridge (540) to a package substrate (610, 710,910). Figure 16 (the structure in the lower right corner) shows a first die (upper left die in lower right corner structure in figure 16) over a first portion of the package substrate and over a first portion of the multi-die interconnect bridge (note darker die beneath all of the four dies); the first die (upper left die in lower right corner structure in figure 16) is electrically coupled to the multi-die interconnect bridge (p. 3, paragraph 35, p. 8, paragraph 77). A second die (upper right die in lower right corner structure in figure 16) is over a second portion of the package substrate and over a second portion of the multi-die interconnect bridge; the second die is electrically coupled to the multi-die interconnect bridge (p. 3, paragraph 35, p. 8, paragraph 77). A third die (lower right die in lower right corner structure in figure 16) is over a third portion of the package substrate and over a third portion of the multi-die interconnect bridge; the third die is electrically coupled to the multi-die interconnect bridge (p. 3, paragraph 35, p. 8, paragraph 77). The third die (lower right die in lower right corner structure in figure 16) is diagonally opposed to the first die (upper left die in lower right corner structure in figure 16) across the multi-die interconnect bridge. The third die (lower right die in lower right corner structure in figure 16) is electrically connected to the first die (upper left die in lower right corner structure in figure 16) by the multi-die interconnect bridge (540, p. 3, paragraph 35, p. 8, paragraph 77). A fourth die (lower left die in lower right corner structure in figure 16) is over a fourth portion of the package substrate and over a fourth portion of the multi-die interconnect bridge; the fourth die (lower left die in lower right corner structure in figure 16) is electrically coupled to the multi-die interconnect bridge (540, p. 3, paragraph 35, p. 8, paragraph 77).
Braunisch does not explicitly state that the third die (lower right die in lower right corner structure in figure 16) is directly electrically connected to the first die (upper left die in lower right corner structure in figure 16). However Braunisch discloses that using a bridge between two dies/dice provides the benefit of high-speed, high-density connectivity between them (p. 2, paragraph 28, p. 7, paragraphs 70-71, p. 8, paragraph 86) which is desirable in the art (p. 1, paragraph 2, p. 2, paragraph 25). In view of Braunisch, it would therefore be obvious to directly electrically connect the third die and the first die with the multi-die interconnect bridge.
With regard to claim 12, the first die (upper left die in lower right corner structure in figure 16) is directly electrically connected to the second die (upper right die in lower right corner structure in figure 16) by the multi-die interconnect bridge (540, p. 3, paragraph 35, p. 8, paragraph 77).
In reference to claim 13, the first die (upper left die in lower right corner structure in figure 16) is directly electrically connected to the fourth die (lower left die in lower right corner structure in figure 16) by the multi-die interconnect bridge (540, p. 3, paragraph 35, p. 8, paragraph 77).
In reference to claim 16, the first die (upper left die in lower right corner structure in figure 16), the second die (upper right die in lower right corner structure in figure 16), the third die (lower right die in lower right corner structure in figure 16), and the fourth die (lower left die in lower right corner structure in figure 16) are coupled to a first side of the package substrate (610, 710, 910). A plurality of bumps (p. 2, paragraph 28) are coupled to a second side of the package substrate (610, 710, 910) with the second side being opposite to the first side.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Braunisch as applied to claim 1 above and further in view of Braunisch.
In reference to claim 4, fig. 16 of Braunisch shows that the fourth die (lower left die in lower right corner structure in figure 16) is diagonally opposed to the second die (upper right die in lower right corner structure in figure 16). Braunisch does not explicitly state that the fourth die (lower left die in lower right corner structure in figure 16) is directly electrically connected to the second die (upper right die in lower right corner structure in figure 16). However Braunisch discloses that using a bridge between two dies/dice provides the benefit of high-speed, high-density connectivity between them (p. 2, paragraph 28, p. 7, paragraphs 70-71, p. 8, paragraph 86) which is desirable in the art (p. 1, paragraph 2, p. 2, paragraph 25). In view of Braunisch, it would therefore be obvious to directly electrically connect the fourth die and the second die with the multi-die interconnect bridge.
Claims 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Braunisch in view of Tang et al. (United States Patent Application Publication No. US 2017/0062353 A1, hereinafter "Tang").
In reference to claim 6, Braunisch does not disclose that the first die (upper left die in lower right corner structure in figure 16) and the third die (lower right die in lower right corner structure in figure 16) have different sizes from one another. However Tang discloses implementing a semiconductor device using dies with different sizes and functions/circuitry (p. 9, paragraph 110). Tang discloses that devices with greater functionality and greater amounts of circuitry while being small in size is a known goal in the art (p. 1, paragraph 1). In view of the above, it would be obvious to implement dies with different sizes and functions for a device with greater functionality and greater amounts of circuitry.
With regard to claim 8, Braunisch does not disclose that the first die (upper left die in lower right corner structure in figure 16), the second die (upper right die in lower right corner structure in figure 16), the third die (lower right die in lower right corner structure in figure 16), and the fourth die (lower left die in lower right corner structure in figure 16) have different sizes from one another. However Tang discloses implementing a semiconductor device using dies with different sizes and functions/circuitry (p. 9, paragraph 110). Tang discloses that devices with greater functionality and greater amounts of circuitry while being small in size is a known goal in the art (p. 1, paragraph 1). In view of the above, it would be obvious to implement dies with different sizes and functions for a device with greater functionality and greater amounts of circuitry.
Claims 9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Braunisch in view of Guenin et al. (United States Patent Application Publication No. US 2006/0095639 A1, hereinafter "Guenin").
In reference to claim 9, Braunisch does not explicitly disclose using a second multi-die interconnect bridge coupled to the package substrate (610, 710, 910) such that the second multi-die interconnect bridge (540) is coupled to the first die (upper left die in lower right corner structure in figure 16) and the second die (upper right die in lower right corner structure in figure 16). However Guenin discloses the use of additional multi-die interconnect bridges in figures 4A-4D and 11A-11E; some bridges of which couple only two dies/chips together (note figures 4A and 11E). Guenin discloses that using additional multi-die interconnect bridges simplifies alignment, thermal management, and power distribution for the multi-chip module while simplifying its design (p. 6, paragraph 125, p. 2-3, paragraphs 55, 60-62) which are known goals in the art (p. 1, paragraphs 6-9, 21, p. 2-3, paragraphs 55, 60-62). In view of Guenin, it would therefore be obvious to couple a second multi-die interconnect bridge to the package substrate (610, 710, 910) such that the second multi-die interconnect bridge is coupled to the first die (upper left die in lower right corner structure in figure 16) and the second die (upper right die in lower right corner structure in figure 16) in the Braunisch structure.
In reference to claim 15, Braunisch does not explicitly disclose coupling a second multi-die interconnect bridge to the package substrate (610, 710, 910) such that the second multi-die interconnect bridge (540) is coupled to the first die (upper left die in lower right corner structure in figure 16) and the second die (upper right die in lower right corner structure in figure 16). However Guenin discloses the use of additional multi-die interconnect bridges in figures 4A-4D and 11A-11E; some bridges of which couple only two dies/chips together (note figures 4A and 11E). Guenin discloses that using additional multi-die interconnect bridges simplifies alignment, thermal management, and power distribution for the multi-chip module while simplifying its design (p. 6, paragraph 125, p. 2-3, paragraphs 55, 60-62) which are known goals in the art (p. 1, paragraphs 6-9, 21, p. 2-3, paragraphs 55, 60-62). In view of Guenin, it would therefore be obvious to couple a second multi-die interconnect bridge (540) to the package substrate (610, 710, 910) such that the second multi-die interconnect bridge is coupled to the first die (upper left die in lower right corner structure in figure 16) and the second die (upper right die in lower right corner structure in figure 16) in the method disclosed by Braunisch.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Braunisch as applied to claim 11 above and further in view of Braunisch.
In reference to claim 14, fig. 16 of Braunisch shows that the fourth die (lower left die in lower right corner structure in figure 16) is diagonally opposed to the second die (upper right die in lower right corner structure in figure 16). Braunisch does not explicitly state that the fourth die (lower left die in lower right corner structure in figure 16) is directly electrically connected to the second die (upper right die in lower right corner structure in figure 16). However Braunisch discloses that using a bridge between two dies/dice provides the benefit of high-speed, high-density connectivity between them (p. 2, paragraph 28, p. 7, paragraphs 70-71, p. 8, paragraph 86) which is desirable in the art (p. 1, paragraph 2, p. 2, paragraph 25). In view of Braunisch, it would therefore be obvious to directly electrically connect the fourth die and the second die with the multi-die interconnect bridge.
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Braunisch in view of Lin et al. (United States Patent Application Publication No. US 2011/0062575 A1, hereinafter "Lin").
In reference to claim 17, Braunisch discloses a similar structure. Figure 16 (the structure in the lower right corner: one bridge with four dies) in conjunction with figures 6-9 disclose a semiconductor package comprising a semiconductor package substrate (610, 710, 910). A multi-die interconnect bridge (540) is coupled to the package substrate (610, 710,910). Figure 16 (the structure in the lower right corner) shows a first die (upper left die in lower right corner structure in figure 16) over a first portion of the package substrate and over a first portion of the multi-die interconnect bridge (note darker die beneath all of the four dies); the first die (upper left die in lower right corner structure in figure 16) is electrically coupled to the multi-die interconnect bridge (p. 3, paragraph 35, p. 8, paragraph 77). A second die (upper right die in lower right corner structure in figure 16) is over a second portion of the package substrate and over a second portion of the multi-die interconnect bridge; the second die is electrically coupled to the multi-die interconnect bridge (p. 3, paragraph 35, p. 8, paragraph 77). A third die (lower right die in lower right corner structure in figure 16) is over a third portion of the package substrate and over a third portion of the multi-die interconnect bridge; the third die is electrically coupled to the multi-die interconnect bridge (p. 3, paragraph 35, p. 8, paragraph 77). The third die (lower right die in lower right corner structure in figure 16) is diagonally opposed to the first die (upper left die in lower right corner structure in figure 16) across the multi-die interconnect bridge. The third die (lower right die in lower right corner structure in figure 16) is electrically connected to the first die (upper left die in lower right corner structure in figure 16) by the multi-die interconnect bridge (540, p. 3, paragraph 35, p. 8, paragraph 77).
Braunisch does not explicitly state that the third die (lower right die in lower right corner structure in figure 16) is directly electrically connected to the first die (upper left die in lower right corner structure in figure 16). However Braunisch discloses that using a bridge between two dies/dice provides the benefit of high-speed, high-density connectivity between them (p. 2, paragraph 28, p. 7, paragraphs 70-71, p. 8, paragraph 86) which is desirable in the art (p. 1, paragraph 2, p. 2, paragraph 25). In view of Braunisch, it would therefore be obvious to directly electrically connect the third die and the first die with the multi-die interconnect bridge.
A fourth die (lower left die in lower right corner structure in figure 16) is over a fourth portion of the package substrate and over a fourth portion of the multi-die interconnect bridge; the fourth die (lower left die in lower right corner structure in figure 16) is electrically coupled to the multi-die interconnect bridge (540, p. 3, paragraph 35, p. 8, paragraph 77). The first die (upper left die in lower right corner structure in figure 16), the second die (upper right die in lower right corner structure in figure 16), the third die (lower right die in lower right corner structure in figure 16), and the fourth die (lower left die in lower right corner structure in figure 16) are coupled to a first side of the package substrate (610, 710, 910). A plurality of bumps (p. 2, paragraph 28) are coupled to a second side of the package substrate (610, 710, 910) with the second side being opposite to the first side.
Braunisch does not disclose that the semiconductor package substrate is coupled to a printed circuit board such that the semiconductor package is conductively coupled to it. However figure 2c of Lin discloses a semiconductor package substrate conductively coupled to a printed circuit board (52) by a plurality of solder balls (112) on its bottom surface. Lin discloses that mounting and conductively coupling a semiconductor package to a printed circuit board provides structural support (p. 3, paragraph 26) which is desirable in the art (p. 2, paragraph 23). In view of Lin, it would therefore be obvious to the couple the semiconductor package substrate of Braunisch to a printed circuit board such that the semiconductor package is conductively coupled to it.
With regard to claim 18, figures 6-9 and 16 of Braunisch disclose that the first die (upper left die in lower right corner structure in figure 16) is directly electrically connected to the second die (upper right die in lower right corner structure in figure 16) by the multi-die interconnect bridge (540 – fig. 609, p. 3, paragraph 35, p. 8, paragraph 77).
In reference to claim 19, figures 6-9 and 16 of Braunisch disclose that the first die (upper left die in lower right corner structure in figure 16) is directly electrically connected to the fourth die (lower left die in lower right corner structure in figure 16) by the multi-die interconnect bridge (540 – fig. 609, p. 3, paragraph 35, p. 8, paragraph 77).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Braunisch in view of Lin as applied to claim 17 above and further in view of Braunisch.
In reference to claim 20, fig. 16 of Braunisch shows that the fourth die (lower left die in lower right corner structure in figure 16) is diagonally opposed to the second die (upper right die in lower right corner structure in figure 16). Braunisch does not explicitly state that the fourth die (lower left die in lower right corner structure in figure 16) is directly electrically connected to the second die (upper right die in lower right corner structure in figure 16). However Braunisch discloses that using a bridge between two dies/dice provides the benefit of high-speed, high-density connectivity between them (p. 2, paragraph 28, p. 7, paragraphs 70-71, p. 8, paragraph 86) which is desirable in the art (p. 1, paragraph 2, p. 2, paragraph 25). In view of Braunisch, it would therefore be obvious to directly electrically connect the fourth die and the second die with the multi-die interconnect bridge.
Response to Arguments
Applicant’s arguments filed January 6, 2026, in the Appeal Brief have been fully considered. Applicant argues that Braunisch does not explicitly disclose that the third die and first die are directly electrically connected to each other. In view of these arguments, prosecution has been reopened to set forth a new ground of rejection under 35 U.S.C. 103. As detailed in the rejections above, while Braunisch may not explicitly show this direct connection in Figure 16, it would have been obvious to a person of ordinary skill in the art to directly connect them based on Braunisch’s own teachings regarding the benefits of high-speed, high-density connectivity (Braunisch, p. 2, para 28). Therefore, Applicant’s arguments are rendered moot by the new grounds of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30.
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/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights