DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claim(s) 1-2, 5-6 filed on 9/29/2026 have been fully considered for examination based on their merits. The previously presented claim(s) 3-4, and 7-12 have been considered. New Claim(s) 21-24 have been considered and entered.
Response to Arguments
Applicant’s arguments, see Remarks, pages 6-7, filed 07/06/2026, with respect to the rejection(s) of claim(s) 1-12 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of PARK and OKUDA.
Regarding Claim(s) 1 and 5. The Applicant argues (see Remarks, page 6) that KATO art fails to disclose or suggest the amended features to claims 1, and 5, now recites, “a dry film resist layer on the solder resist layer wherein the dry film resist layer defines a second section of the channel that the external via is formed within.” The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior-art of PARK teaches an electronic device having solder resist layer and dry film resist layer stacked and defines as first and second section of a channel. OKUDA teaches an electronic device, comprising a top layer placed on the portion of the conductor pad and made of gold material.
A typo error found in the Remarks, page 6, filed on 07/06/2026, wherein the Applicant mentioned, Claim 6 as amended, now recites similar to amended claim 1. However, the amended claims received on 07/06/2026, the amendment was with respect to an independent claim 5. The dependent claim 6 amended similar to claim 2 as entered for examination.
Regarding Claims 2-4, 6-12, and 21-24: The dependent claims 2-4, 6-12 and 21-24, follow similar arguments as Claims 1 and 5, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-5, 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hisashi Kato, (hereinafter KATO), US 20110284277 A1, in view of Jun-hyung Park et al, (hereinafter PARK), KR 20110029467 A, and Haruki Okuda et al, (hereinafter OKUDA), JP 2012074487 A.
Regarding Claim 1, KATO teaches an electronic device (Fig. 16, 10, IC chip mounted on the multilayer printed wiring board, [0024]) comprising:
a cored substrate (Fig. 16, 30, insulative substrate) including a conductor coating (Fig. 16, 34U, conductive circuit, [0036]) extending along at least one of a first major surface (annotated Figure 16) or a second major surface (annotated Figure 16);
a through via (Figs. 8/16, 36b, through-hole conductor, [0045]) extending through the cored substrate (Fig. 16, 30, insulative substrate) from the first major surface (annotated Figure 16) to the second major surface (annotated Figure 16), the through via (Figs. 8/16, 36b, through-hole conductor, [0045]) connected (annotated Figure 16) to the conductor coating (Fig. 16, 34U, conductive circuit, [0036]);
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an external via (Fig. 16, 160-1, third via conductor, [0169]) external (annotated Figure 16) to the cored substrate (Fig. 16, 30, insulative substrate), the external via (Fig. 16, 160-1, third via conductor, [0169]) connected (annotated Figure 16) to the conductor coating (Fig. 16, 34U, conductive circuit, [0036]);
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one or more dies (Fig. 16, 90, IC chip) connected to the external via (Fig. 16, 160-1, third via conductor, [0169]).
KATO does not explicitly disclose an electronic device comprising: a solder resist layer on the cored substrate, the solder resist layer defines a first section of a channel that the external via is formed within and insulates the external via; a dry film resist layer on the solder resist layer wherein the dry film resist layer defines a second section of the channel that the external via is formed within.
PARK teaches an electronic device (Fig. 3, semiconductor device) comprising:
a solder resist (Fig. 3, 30) layer on the cored substrate (Fig. 3, 10), the solder resist layer (Fig. 3, 30) defines a first section of a channel (annotated Figure 3) that the external via (Fig. 3, V, opening portion) is formed within and insulates the external via (Fig. 3, V, opening portion); a dry film resist layer (Fig. 3, 40) on the solder resist layer (Fig. 3, 30) wherein the dry film resist layer (Fig. 3, 40) defines a second section of the channel (annotated Figure 3) that the external via (Fig. 3, V, opening portion) is formed within.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified KATO to incorporate the teachings of PARK, such that an electronic device comprising: a solder resist layer on the cored substrate, the solder resist layer defines a first section of a channel that the external via is formed within and insulates the external via; a dry film resist layer on the solder resist layer wherein the dry film resist layer defines a second section of the channel that the external via is formed within. The above arrangement relates to a method for forming solder bumps that reduce process time, and process costs without causing alignment problems during exposure (PARK, Figure 3, 1st para of description on method for forming solder bump, page 2).
KATO as modified by PARK does not explicitly disclose an electronic device comprising: a top layer, the top layer including gold, the top layer extending along the conductor coating and only a portion of the solder resist layer.
OKUDA teaches an electronic device (Fig. 2, 100, semiconductor package) comprising: a top layer (Fig. 1C, 5, metal coating layer), the top layer (Fig. 1C, 5, metal coating layer) including gold (Fig. 1C, 5, the metal coating layer, 5 is formed, for example, in the order of a Ni layer and an Au layer, [0005]), the top layer (Fig. 1C, 5, metal coating layer) extending along the conductor coating (Fig. 1C, 2, conductor pad) and only a portion of the solder resist layer (Fig. 1C, 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have KATO as modified by PARK to incorporate the teachings of OKUDA, such that an electronic device comprising: a top layer, the top layer including gold, the top layer extending along the conductor coating and only a portion of the solder resist layer, so that the gold (Au) layer is provided on the Ni metal coated layer to prevent oxidation of the Ni layer surface until the solder join is completed (OKUDA, Figure 1C, [0005]).
Regarding Claim 3, KATO as modified by PARK and OKUDA teaches the electronic device of claim 1.
KATO further teaches the electronic device (Fig. 16, 10, IC chip mounted on the multilayer printed wiring board, [0024]), wherein the cored substrate (Fig. 16, 30, insulative substrate) includes glass (insulative substrate, 30 is preferred to contain a core material as glass cloth, [0045]).
Regarding Claim 4, KATO as modified by PARK and OKUDA teaches the electronic device of claim 1.
KATO further teaches the electronic device (Fig. 16, 10, IC chip mounted on the multilayer printed wiring board, [0024]), wherein the conductor coating (Fig. 16, 34U, conductive circuit, [0036]) includes copper (electrolytic copper plated-film, [0067-0068]).
Regarding Claim 5, KATO teaches an electronic device (Fig. 16, 10, IC chip mounted on the multilayer printed wiring board, [0024]) comprising:
a substrate (Fig. 16, 30, insulative substrate) including a conductor coating (Fig. 16, 34U, conductive circuit, [0036]);
a via (Figs. 8/16, 36b, through-hole conductor, [0045]) connected (annotated Figure 16) to the conductor coating (Fig. 16, 34U, conductive circuit, [0036]);
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one or more dies (Fig. 16, 90, IC chip) connected to the via (Fig. 16, 160-1, third via conductor, [0169]).
KATO does not explicitly disclose an electronic device comprising: a solder resist layer on the substrate, the solder resist layer defining a first section of a channel that the via is formed within and insulating the via during operation of the electronic device; a dry film resist layer on the solder resist layer wherein the dry film resist layer defines a second section of the channel that the via is formed within.
PARK teaches disclose an electronic device (Fig. 3, semiconductor device) comprising:
a solder resist (Fig. 3, 30) layer on the substrate (Fig. 3, 10), the solder resist layer (Fig. 3, 30) defining a first section of a channel (annotated Figure 3) that the via (Fig. 3, V, opening portion) is formed within and insulating the via (Fig. 3, V, opening portion); a dry film resist layer (Fig. 3, 40) on the solder resist layer (Fig. 3, 30) wherein the dry film resist layer (Fig. 3, 40) defines a second section of the channel (annotated Figure 3) that the via (Fig. 3, V, opening portion) is formed within.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified KATO to incorporate the teachings of PARK, such that an electronic device comprising: a solder resist layer on the cored substrate, the solder resist layer defines a first section of a channel that the external via is formed within and insulates the external via; a dry film resist layer on the solder resist layer wherein the dry film resist layer defines a second section of the channel that the external via is formed within. The above arrangement relates to a method for forming solder bumps that reduce process time, and process costs without causing alignment problems during exposure (PARK, Figure 3, 1st para of description on method for forming solder bump, page 2).
KATO as modified by PARK does not explicitly disclose an electronic device comprising: a top layer interproximal to the substrate and the via;
OKUDA teaches an electronic device (Fig. 2, 100, semiconductor package) comprising: a top layer (Fig. 1C, 5, metal coating layer) interproximal (annotated Figure 1C) to the substrate (Fig. 1C, 1, insulating resin layer) and the via Fig. 1C, 4, solder resist opening);
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have KATO as modified by PARK to incorporate the teachings of OKUDA, such that an electronic device comprising: a top layer interproximal to the substrate and the via, so that the a metal coating layer, 5 is generally used as a terminal portion structure for soldering (OKUDA, Figure 1C, [0005]).
Regarding Claim 10, KATO as modified by PARK and OKUDA teaches the electronic device of claim 5.
KATO further teaches the electronic device (Fig. 16, 10, IC chip mounted on the multilayer printed wiring board, [0024]), wherein the substrate (Fig. 16, 30, insulative substrate), is a cored substrate ([0037]), and wherein the cored substrate (Fig. 16, 30, insulative substrate) includes glass (insulative substrate, 30 is preferred to contain a core material as glass cloth, [0045]).
Regarding Claim 11, KATO as modified by PARK and OKUDA teaches the electronic device of claim 5.
KATO further teaches the electronic device (Fig. 16, 10, IC chip mounted on the multilayer printed wiring board, [0024]), wherein the conductor coating (Fig. 16, 34U, conductive circuit, [0036]) includes copper (electrolytic copper plated-film, [0067-0068]).
Regarding Claim 12, KATO as modified by PARK and OKUDA teaches the electronic device of claim 5.
KATO further teaches the electronic device (Fig. 16, 10, IC chip mounted on the multilayer printed wiring board, [0024]), wherein the via (Figs. 8/16, 36b, through-hole conductor, [0045]) connected includes copper (electrolytic copper-plated film covers through-hole conductor (36b), [0049], [0067-0068]).
Claim(s) 2, and 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over KATO, in view of PARK and OKUDA as applied to Claim 1, 3-5, 10-12 above, and further in view of E. Rouya eta al, (hereinafter ROUYA), Electrodeposition of metastable Au-Ni alloys, E. Rouya, G.R. Stafford, U. Bertocci, J.J. Mallett, R. Schad, M.R. Begley, R.G. Kelly, M.L. Reed, and G. Zangari, Journal of The Electrochemical Society, 157, 7, D396-D405, 2010; DOI: 10,1149/1.3421749.
Regarding Claim 2, KATO as modified by PARK and OKUDA teaches the electronic device of claim 1.
OKUDA further teaches the electronic device (Fig. 2, 100, semiconductor package), wherein the top layer (Fig. 1C, 5, metal coating layer) includes an electrolytically deposited layer (Fig. 1C, 5, metal coating layer; a Ni layer and an Au layer, by electroless nickel/displacement gold plating (ENIG) or electroless nickel/palladium/displacement gold plating (ENEPIG) processes [0012]).
Though OKUDA teaches the semiconductor package, wherein the metal coating layer, 5 is applied to the conductor pad, 2; the metal coating layer, 5 is further formed in the order of, for example, a Ni layer and an Au layer, by electroless nickel/displacement gold plating (ENIG) or electroless nickel/palladium/displacement gold plating (ENEPIG) processes [0012], KATO as modified by PARK and OKUDA does not explicitly disclose the electronic device, wherein the top layer includes an electrolytically deposited layer.
ROUYA teaches the electronic device (microelectronics packaging, [Page D396, Col. 1, Introduction, Last Line]), wherein the top layer includes an electrolytically deposited layer (the electrodeposition Au-Ni alloy films was carried out in a three-electrode, two-compartment prismatic cell; [Page D396, Col. 2, Experimental Paragraph, Third line from the last]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have KATO as modified by PARK and OKUDA to incorporate the teachings of ROUYA, such that the electronic device, wherein the top layer includes an electrolytically deposited layer, so that the electrodeposition of Au-Ni alloys from near-neutral sulfite-based electrolytes yielded the formation of a metastable structure and are comparable to other processes such as electrochemical or electroless deposition (ROUYA, [page D405, Col. 1, section on Conclusion]).
Regarding Claim 6, KATO as modified by PARK and OKUDA teaches the electronic device of claim 5.
OKUDA further teaches the electronic device (Fig. 2, 100, semiconductor package), wherein the top layer (Fig. 1C, 5, metal coating layer) includes an electrolytically deposited layer (Fig. 1C, 5, metal coating layer; a Ni layer and an Au layer, by electroless nickel/displacement gold plating (ENIG) or electroless nickel/palladium/displacement gold plating (ENEPIG) processes [0012]).
Though OKUDA teaches the semiconductor package, wherein the metal coating layer, 5 is applied to the conductor pad, 2; the metal coating layer, 5 is further formed in the order of, for example, a Ni layer and an Au layer, by electroless nickel/displacement gold plating (ENIG) or electroless nickel/palladium/displacement gold plating (ENEPIG) processes [0012], KATO as modified by PARK and OKUDA does not explicitly disclose the electronic device, wherein the top layer includes an electrolytically deposited layer.
ROUYA teaches the electronic device (microelectronics packaging, [Page D396, Col. 1, Introduction, Last Line]), wherein the top layer includes an electrolytically deposited layer (the electrodeposition Au-Ni alloy films was carried out in a three-electrode, two-compartment prismatic cell; [Page D396, Col. 2, Experimental Paragraph, Third line from the last]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have KATO as modified by PARK and OKUDA to incorporate the teachings of ROUYA, such that the electronic device, wherein the top layer includes an electrolytically deposited layer, so that the electrodeposition of Au-Ni alloys from near-neutral sulfite-based electrolytes yielded the formation of a metastable structure and are comparable to other processes such as electrochemical or electroless deposition (ROUYA, [page D405, Col. 1, section on Conclusion]).
Regarding Claim 7, KATO as modified by PARK, OKUDA and ROUYA teaches the electronic device of claim 6.
OKUDA further teaches the electronic device (Fig. 2, 100, semiconductor package), wherein the top layer (Fig. 1C, 5, metal coating layer) covers (annotated Figure 1D below) the conductor coating (Fig. 1C, 2, conductor pad).
Regarding Claim 8, KATO as modified by PARK, OKUDA and ROUYA teaches the electronic device of claim 7.
OKUDA further teaches the electronic device (Fig. 2, 100, semiconductor package), wherein the top layer (Fig. 1C, 5, metal coating layer) includes a flat layer (annotated Figure 1C) such that the top layer (Fig. 1C, 5, metal coating layer) does not extend upward along (annotated Figure 1C) the solder resist layer (Fig. 1C, 3).
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Regarding Claim 9 KATO as modified by PARK, OKUDA and ROUYA teaches the electronic device of claim 7.
OKUDA further teaches the electronic device (Fig. 2, 100, semiconductor package), the top layer (Fig. 1C, 5, metal coating layer) covers only a portion (annotated Figure 1D above) of the solder resist layer (Fig. 1C, 3).
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Claim(s) 21, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over KATO, in view of PARK and OKUDA as applied to Claim 1, 3-5, 10-12 above, and further in view of Takema Adachi et al, (hereinafter ADACHI), US 20220248531 A1.
Regarding Claim 21, KATO as modified by PARK and OKUDA teaches the electronic device of claim 1.
PARK further teaches the electronic device (Fig. 3, semiconductor device), wherein the dry film resist layer (Fig. 3, 40) extends along sides of and into (annotated Figure 3) the first section of the channel (annotated Figure 3).
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Though PARK teaches the electronic device, wherein the dry film resist layer (annotated Figure 3 above) into the first section of the channel, KATO as modified by PARK and OKUDA does not explicitly disclose the electronic device, wherein the dry film resist layer extends along sides of and into the first section of the channel.
ADACHI teaches the electronic device (Fig. 3, 100, wiring substrate), wherein the dry film resist layer (Fig. 3, 10b, metal film) extends along sides of and into (annotated Figure 3) the first section of the channel (annotated Figure 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have KATO as modified by PARK and OKUDA to incorporate the teachings of ADACHI, such that the electronic device, wherein the dry film resist layer extends along sides of and into the first section of the channel, so that the metal film, 10b, act as power feeding layer in the formation of other films such as plating film, 10c, conductor layers, 11 and 13 (ADACHI, [0072]).
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Regarding Claim 23, KATO as modified by PARK and OKUDA teaches the electronic device of claim 5.
PARK further teaches the electronic device (Fig. 3, semiconductor device), wherein the dry film resist layer (Fig. 3, 40) extends along sides of and into (annotated Figure 3) the first section of the channel (annotated Figure 3).
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Though PARK teaches the electronic device, wherein the dry film resist layer (annotated Figure 3 above) into the first section of the channel, KATO as modified by PARK and OKUDA does not explicitly disclose the electronic device, wherein the dry film resist layer extends along sides of and into the first section of the channel.
ADACHI teaches the electronic device (Fig. 3, 100, wiring substrate), wherein the dry film resist layer (Fig. 3, 10b, metal film) extends along sides of and into (annotated Figure 3) the first section of the channel (annotated Figure 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have KATO as modified by PARK and OKUDA to incorporate the teachings of ADACHI, such that the electronic device, wherein the dry film resist layer extends along sides of and into the first section of the channel, so that the metal film, 10b, act as power feeding layer in the formation of other films such as plating film, 10c, conductor layers, 11 and 13 (ADACHI, [0072]).
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Claim(s) 22, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over and further in view of Jong Hyun Lee et al, (hereinafter LEE), KR 20100128517 A, and Bryan D. Vogt et al, (hereinafter VOGT), Water distribution within immersed polymer films, Bryan D. Vogt, Christopher L. Soles, Vivek M. Prabhu, Sushi K. Satija, Eric K. Lin, and Wen-li Wu, Advances in Resist Technology and Processing XXII, edited by John L. Sturtevant, Proceedings of SPIE Vol. 5753 (SPIE, Bellingham, WA, 2005) 0277-786X/05/$15, doi: 10.1117/12.599746.
Regarding Claim 22, KATO as modified by PARK, OKUDA and ADACHI teaches the electronic device of claim 1.
KATO as modified by PARK, OKUDA and ADACHI does not explicitly disclose the electronic device, wherein the dry film resist layer has a hydrophilicity before curing.
LEE teaches the electronic device (Fig. 3, 1a, polymerase chain reaction chip), wherein the dry film resist layer (Figs. 2/3, 20a, DFR material) has a hydrophilicity (Fig. 1, since DFR is hydrophilic, it can easily bond with a glass wafer with any special treatment, [page 5 last line; and page 6, first line]) before curing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have KATO as modified by PARK, OKUDA and ADACHI to incorporate the teachings of LEE, such that the electronic device, wherein the dry film resist layer has a hydrophilicity before curing, so that it can easily bond with a glass wafer without any special treatment (LEE, [page 5 last line; and page 6, first line]).
KATO as modified by PARK, OKUDA, ADACHI and LEE does not explicitly disclose the electronic device, wherein the hydrophilicity allows the dry film resist layer to absorb a liquid and swell.
VOGT teaches the electronic device (immersion lithography tool, HMDS treated silicon wafers, [Abstract, page 31; conclusion, page 37]), wherein the hydrophilicity allows the dry film resist layer (photoresist films, [Conclusion, page 37]) to absorb a liquid (D2O absorption, [Methods, page 33]) and swell (Fig. 3(a) and 3(b), a total film thickness increases due to the absorption of D2O was observed as the film swelled to 386 Å; a greater extent of swelling is observed, as expected due to the presence of the more hydrophilic hydroxyl groups).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have KATO as modified by PARK, OKUDA and ADACHI to incorporate the teachings of VOGT, such that the electronic device, wherein the hydrophilicity allows the dry film resist layer to absorb a liquid and swell, so that the excess water at the interface also manifests itself as a thickness dependent swelling for thin films, allowing for observation of interfacial concentration heterogeneities (VOGT, [Conclusion, page 38]).
Regarding Claim 24, KATO as modified by PARK, OKUDA and ADACHI teaches the electronic device of claim 5.
KATO as modified by PARK, OKUDA and ADACHI does not explicitly disclose the electronic device, wherein the dry film resist layer has a hydrophilicity before curing.
LEE teaches the electronic device (Fig. 3, 1a, polymerase chain reaction chip), wherein the dry film resist layer (Figs. 2/3, 20a, DFR material) has a hydrophilicity (Fig. 1, since DFR is hydrophilic, it can easily bond with a glass wafer with any special treatment, [page 5 last line; and page 6, first line]) before curing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have KATO as modified by PARK, OKUDA and ADACHI to incorporate the teachings of LEE, such that the electronic device, wherein the dry film resist layer has a hydrophilicity before curing, so that it can easily bond with a glass wafer without any special treatment (LEE, [page 5 last line; and page 6, first line]).
KATO as modified by PARK, OKUDA, ADACHI and LEE does not explicitly disclose the electronic device, wherein the hydrophilicity allows the dry film resist layer to absorb a liquid and swell.
VOGT teaches the electronic device (immersion lithography tool, HMDS treated silicon wafers, [Abstract, page 31; conclusion, page 37]), wherein the hydrophilicity allows the dry film resist layer (photoresist films, [Conclusion, page 37]) to absorb a liquid (D2O absorption, [Methods, page 33]) and swell (Fig. 3(a) and 3(b), a total film thickness increases due to the absorption of D2O was observed as the film swelled to 386 Å; a greater extent of swelling is observed, as expected due to the presence of the more hydrophilic hydroxyl groups).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have KATO as modified by PARK, OKUDA and ADACHI to incorporate the teachings of VOGT, such that the electronic device, wherein the hydrophilicity allows the dry film resist layer to absorb a liquid and swell, so that the excess water at the interface also manifests itself as a thickness dependent swelling for thin films, allowing for observation of interfacial concentration heterogeneities (VOGT, [Conclusion, page 38]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 6093509 A – Figure 4
STATEMENT OF RELEVANCE – A hydrophilic swellable layer on an aluminum substrate; Example 59 shows the lithographic printing plate which are swollen by the measurement method.
US 8901431 B2 – Figure 8A
STATEMENT OF RELEVANCE – A cross sectional view schematically showing surroundings of an opening portion when a solder-resist layer is formed on a pad whose surface is roughened.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
