DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
No Information Disclosure Statement (IDS) has been filed.
Election/Restrictions
Applicant’s election without traverse of Invention 1, direct to Claims 1-12 in the reply filed 03/23/2026 is acknowledged and is under consideration.
Response to Amendment
The amendment with respect to the elected claims 1-12 filed on 03/23/2026 have been fully considered for examination based on their merits. The non-elected Claims 13-20 are withdrawn by the Applicant.
Specification Amendment
The amendment with respect to Specification filed on 03/23/2026 has been fully considered and entered.
Response to Arguments
Applicant elected Claims 1-12 (without traverse) in the Remarks filed on 03/23/2026 are considered for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hisashi Kato, (hereinafter KATO), US 20110284277 A1.
Regarding Claim 1, KATO teaches an electronic device (Fig. 16, 10, IC chip mounted on the multilayer printed wiring board, [0024]) comprising:
a cored substrate (Fig. 16, 30, insulative substrate) including a conductor coating (Fig. 16, 34U, conductive circuit, [0036]) extending along at least one of a first major surface (annotated Figure 16) or a second major surface (annotated Figure 16);
a through via (Figs. 8/16, 36b, through-hole conductor, [0045]) extending through the cored substrate (Fig. 16, 30, insulative substrate) from the first major surface (annotated Figure 16) to the second major surface (annotated Figure 16), the through via (Figs. 8/16, 36b, through-hole conductor, [0045]) connected (annotated Figure 16) to the conductor coating (Fig. 16, 34U, conductive circuit, [0036]);
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an external via (Fig. 16, 160-1, third via conductor, [0169]) external (annotated Figure 16) to the cored substrate (Fig. 16, 30, insulative substrate), the external via (Fig. 16, 160-1, third via conductor, [0169]) connected (annotated Figure 16) to the conductor coating (Fig. 16, 34U, conductive circuit, [0036]);
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a solder resist layer (Fig. 16, 70) on the cored substrate (Fig. 16, 30, insulative substrate), the solder resist layer (Fig. 16, 70) defines a channel that the external via (Fig. 16, 160-1, third via conductor, [0169]) is formed within and insulates (annotated Figure 16) the external via (Fig. 16, 160-1, third via conductor, [0169]);
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a top layer (Figs. 6D/16, 74, gold-plated layer, [0074]), the top layer including gold (Figs. 6D/16, 74, gold-plated layer, [0074]) to prevent oxidation (protective film, [0074]) and prepare the conductor coating (Fig. 16, 34U, conductive circuit, [0036]) to adhere to the external via (Fig. 16, 60-1, first via conductor, [0145]), the top layer (Figs. 6D/16, 74, gold-plated layer, [0074]) extending along the conductor coating (Fig. 16, 60-1, first via conductor, [0145]) and only a portion of the solder resist layer (Fig. 16, 70); and one or more dies (Fig. 16, 90, IC chip) connected to the external via (Fig. 16, 160-1, third via conductor, [0169]).
Regarding Claim 2, KATO teaches the electronic device (Fig. 16, 10, IC chip mounted on the multilayer printed wiring board, [0024]) of claim 1, wherein the top layer (Figs. 6D/16, 74, gold-plated layer, [0074]) includes an electrolytic layer (Figs. 6D/16, 74, electroless gold-plated layer, [0074]; Figs. 19C/21B, 2304/3301, electrolytic plated film is formed on electroless plated film, 2300 exposed from plating resist, 2304/3300, [0105], [0113]).
Regarding Claim 3, KATO teaches the electronic device (Fig. 16, 10, IC chip mounted on the multilayer printed wiring board, [0024]) of claim 1, wherein the cored substrate (Fig. 16, 30, insulative substrate) includes glass (insulative substrate, 30 is preferred to contain a core material as glass cloth, [0045]).
Regarding Claim 4, KATO teaches the electronic device (Fig. 16, 10, IC chip mounted on the multilayer printed wiring board, [0024]) of claim 1, wherein the conductor coating (Fig. 16, 34U, conductive circuit, [0036]) includes copper (electrolytic copper plated-film, [0067-0068]).
Regarding Claim 5, KATO teaches an electronic device (Fig. 16, 10, IC chip mounted on the multilayer printed wiring board, [0024]) comprising:
a substrate (Fig. 16, 30, insulative substrate) including a conductor coating (Fig. 16, 34U, conductive circuit, [0036]);
a via (Figs. 8/16, 36b, through-hole conductor, [0045]) connected (annotated Figure 16) to the conductor coating (Fig. 16, 34U, conductive circuit, [0036]);
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a solder resist layer (Fig. 16, 70) on the substrate (Fig. 16, 30, insulative substrate), the solder resist layer (Fig. 16, 70) defining a channel that the via (Figs. 8/16, 36b, through-hole conductor, [0045]) is formed within and insulating (annotated Figure 16) the via (Figs. 8/16, 36b, through-hole conductor, [0045]) during operation of the electronic device (Fig. 16, 10, IC chip mounted on the multilayer printed wiring board, [0024]);
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a top layer (Figs. 6D/16, 74, gold-plated layer, [0074]) interproximal (annotated Figure 16) to the substrate (Fig. 16, 30, insulative substrate) and the via (Figs. 8/16, 36b, through-hole conductor, [0045]); and one or more dies (Fig. 16, 90, IC chip) connected to the via (Figs. 8/16, 36b, through-hole conductor, [0045]).
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Regarding Claim 6, KATO teaches the electronic device (Fig. 16, 10, IC chip mounted on the multilayer printed wiring board, [0024]) of claim 5, wherein the top layer (Figs. 6D/16, 74, gold-plated layer, [0074]) includes an electrolytic layer (Figs. 6D/16, 74, electroless gold-plated layer, [0074]; Figs. 19C/21B, 2304/3301, electrolytic plated film is formed on electroless plated film, 2300 exposed from plating resist, 2304/3300, [0105], [0113]).
Regarding Claim 7, KATO teaches the electronic device (Fig. 16, 10, IC chip mounted on the multilayer printed wiring board, [0024]) of claim 6, wherein the top layer (Figs. 6D/16, 74, gold-plated layer, [0074]) covers (annotated Figure 16) the conductor coating (Figs. 6D/16, 34U, conductive circuit, [0036]).
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Regarding Claim 8, KATO teaches the electronic device (Fig. 16, 10, IC chip mounted on the multilayer printed wiring board, [0024]) of claim 7, wherein the top layer (Figs. 6D/16, 74, gold-plated layer, [0074]) includes a flat layer (Figs. 6D/16, 72, nickel-plated layer, [0074]) such that the top layer (Figs. 6D/16, 74, gold-plated layer, [0074]) does not extend upward along (annotated Figure 6D) the solder resist layer (Fig. 6D, 70).
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Regarding Claim 9, KATO teaches the electronic device (Fig. 16, 10, IC chip mounted on the multilayer printed wiring board, [0024]) of claim 7, wherein the top layer(Figs. 6D/16, 74, gold-plated layer, [0074]) covers only a portion (annotated Figure 6D) of the solder resist layer (Fig. 6D, 70).
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Regarding Claim 10, KATO teaches the electronic device (Fig. 16, 10, IC chip mounted on the multilayer printed wiring board, [0024]) of claim 5, wherein the substrate is a cored substrate (Fig. 16, 30, insulative substrate), and wherein the cored substrate includes glass (insulative substrate, 30 is preferred to contain a core material as glass cloth, [0045]).
Regarding Claim 11, KATO teaches the electronic device (Fig. 16, 10, IC chip mounted on the multilayer printed wiring board, [0024]) of claim 5, wherein the conductor coating (Fig. 16, 34U, conductive circuit, [0036]) includes copper (electrolytic copper plated-film, [0067-0068]).
Regarding Claim 12, KATO teaches the electronic device (Fig. 16, 10, IC chip mounted on the multilayer printed wiring board, [0024]) of claim 5, wherein the via (Figs. 8/16, 36b, through-hole conductor, [0045]) connected includes copper (electrolytic copper-plated film covers through-hole conductor (36b), [0049], [0067-0068]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220248531 A1 – Figures 5A
STATEMENT OF RELEVANCE – Surface of the conductor pattern is covered by the coating film (5) and the conductor pattern with surface roughness higher than the surface roughness of the surfaces of the wiring patterns (1b).
US 20220165695 A1 – Figure 1B
STATEMENT OF RELEVANCE – A cross-sectional illustration of the electronic package (100) after attachment of the die (105) to the package substrate (101) and the location of vias (131) within the package substrate (131).
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812 /CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812
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