DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 3/3/2026 is acknowledged.
Applicant amended claims 13 and 15; and cancelled claim 14.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 1/18/2022. It is noted, however, that applicant has not filed a certified copy of the 14/808494 application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2019/0006345) (hereafter Wang345), in view of Kim et al. (US 2020/0043945) (hereafter Kim), in further view of Wang et al. (US 2021/0343709) (hereafter Wang709).
Regarding claim 13, Wang345 discloses a semiconductor device, comprising:
a substrate 210 (Fig. 14C’, paragraph 0031);
active regions 230 (Figs. 14C’ and 14D, paragraph 0033) extending in a first horizontal direction (horizontal direction in Fig. 14D) on the substrate 210 (Fig. 14C’), wherein the active regions 230 (Figs. 14C’ and 14D) comprise a first active region (right portion of top 230 in Fig. 14D) and a second active region (right portion of bottom 230 in Fig. 14D) spaced apart from each other in a second horizontal direction (vertical direction in Fig. 14D) perpendicular to the first horizontal direction (horizontal direction in Fig. 14D), and a third active region (left portion of top 230 in Fig. 14D) and a fourth active region (left portion of bottom 230 in Fig. 14D) spaced apart from each other in the second horizontal direction (vertical direction in Fig. 14D);
gate structures 102 (Fig.14D, paragraph 0034) comprising a first gate structure (second 102 from the right corner of Fig. 14D), a second gate structure (third 102 from the right corner of Fig. 14D), a third gate structure (second 102 from the left corner of Fig. 14D), and a fourth gate structure (third 102 from the left corner of Fig. 14D), wherein the first gate structure (second 102 from the right corner of Fig. 14D) and the second gate structure (third 102 from the right corner of Fig. 14D) intersect the first active region (right portion of top 230 in Fig. 14D) and the second active region (right portion of bottom 230 in Fig. 14D) and are spaced apart from each other, and wherein the third gate structure (second 102 from the left corner of Fig. 14D) and the fourth gate structure (third 102 from the left corner of Fig. 14D) intersect the third active region (left portion of top 230 in Fig. 14D) and the fourth active region (left portion of bottom 230 in Fig. 14D) and are spaced apart from each other;
source/drain regions 250 (Fig. 14C’, paragraph 0034) comprising a first source/drain region (left 250 in Fig. 14C’) on the first active region (left 230 in Fig. 14C’) between (see Fig. 14D and 14C’, wherein left 250 (Fig. 14C’) formed between top portion of second 102 (Fig. 14D) and top portion of third 102 (Fig. 14D) from the right corner of Fig. 14D) the first gate structure (second 102 from the right corner of Fig. 14D) and the second gate structure (third 102 from the right corner of Fig. 14D), a second source/drain region (right 250 in Fig. 14C’) on the second active region (right 230 in Fig. 14C’) between (see Fig. 14D and 14C’, wherein right 250 (Fig. 14C’) formed between bottom portion of second 102 (Fig. 14D) and bottom portion of third 102 (Fig. 14D) from the right corner of Fig. 14D) the first gate structure (second 102 from the right corner of Fig. 14D) and the second gate structure (third 102 from the right corner of Fig. 14D), a third source/drain region (portion of 250 contacting top 230 between second 102 and third 102 from the left corner of Fig. 14D) on the third active region (left portion of top 230 in Fig. 14D) between the third gate structure (second 102 from the left corner of Fig. 14D) and the fourth gate structure (third 102 from the left corner of Fig. 14D), and a fourth source/drain region (portion of 250 contacting bottom 230 between second 102 and third 102 from the left corner of Fig. 14D) on the fourth active region (left portion of bottom 230 in Fig. 14D) between the third gate structure (second 102 from the left corner of Fig. 14D) and the fourth gate structure (third 102 from the left corner of Fig. 14D); and
a first isolation insulating pattern (right 1402 in Fig. 14D, paragraph 0073); and
a second isolation insulating pattern (left 1402 in Fig. 14D, paragraph 0073), wherein the first isolation insulating pattern 1402 (Fig. 14C’) is spaced apart from the first source/drain region (left 250 in Fig. 14C’) and the second source/drain region (right 250 in Fig. 14C’).
Wang345 does not disclose contact plugs comprising a first contact plug connected to the first source/drain region, a second contact plug connected to the second source/drain region, a third contact plug connected to the third source/drain region, and a fourth contact plug connected to the fourth source/drain region;
a first isolation insulating pattern between the first contact plug and the second contact plug; and
a second isolation insulating pattern between the third contact plug and the fourth contact plug, and wherein the second isolation insulating pattern contacts the third source/drain region and the fourth source/drain region.
Kim discloses contact plugs (612 and 614 in Fig. 2C, paragraph 0046) comprising a first contact plug (612 of C2 in Fig. 2C) connected to the first source/drain region (first 300 from the right corner of Fig. 2C, paragraph 0042), a second contact plug (614 of C2 in Fig. 2C) connected to the second source/drain region (second 300 from the right corner of Fig. 2C), a third contact plug (612 of C1 in Fig. 2C) connected to the third source/drain region (first 300 from the left corner of Fig. 2C), and a fourth contact plug (614 of C1 in Fig. 2C) connected to the fourth source/drain region (second 300 from the left corner of Fig. 2C);
a first isolation insulating pattern (400 of C2 in Fig. 2C, paragraph 0046) between the first contact plug (612 of C2 in Fig. 2C) and the second contact plug (614 of C2 in Fig. 2C); and
a second isolation insulating pattern (400 of C1 in Fig. 2C, paragraph 0046) between the third contact plug (612 of C1 in Fig. 2C) and the fourth contact plug (614 of C1 in Fig. 2C), and wherein the second isolation insulating pattern (400 of C1 in Fig. 2C) contacts the third source/drain region (first 300 from the left corner of Fig. 2C) and the fourth source/drain region (second 300 from the left corner of Fig. 2C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang345 to form contact plugs comprising a first contact plug connected to the first source/drain region, a second contact plug connected to the second source/drain region, a third contact plug connected to the third source/drain region, and a fourth contact plug connected to the fourth source/drain region; a first isolation insulating pattern between the first contact plug and the second contact plug; and a second isolation insulating pattern between the third contact plug and the fourth contact plug, and wherein the second isolation insulating pattern contacts the third source/drain region and the fourth source/drain region, as taught by Kim, since the cell contact 610 (Kim, Fig. 2C, paragraph 0051) may be separated into the NMOS contact 612 (Kim, Fig. 2C, paragraph 0051) and the PMOS contact 614 (Kim, Fig. 2C, paragraph 0051) by the insulation pattern 400 (Kim, Fig. 2C, paragraph 0051) in the cell area C, the power signal may be transferred to one of the NMOS contact 612 (Kim, Fig. 2C, paragraph 0051) and the PMOS contact 614 (Kim, Fig. 2C, paragraph 0051) such that the NMOS contact 612 (Kim, Fig. 2C, paragraph 0051) and the PMOS contact 614 (Kim, Fig. 2C, paragraph 0051) in the same cell area C (Kim, Fig. 2C, paragraph 0051) might not simultaneously receive the power signal from the same power rail 700 (Kim, Fig. 2C, paragraph 0051).
Wang345 and Kim do not disclose a bottommost surface of the first isolation insulating pattern is at a level higher than a level of a bottommost lower surface of the second isolation insulating pattern.
Wang709 discloses a bottommost surface of the first isolation insulating pattern 103 (Fig. 1C, paragraph 0035) is at a level higher (see Fig. 1C and paragraph 0035, wherein “height H2 can be greater than height H1 and distance D2 can greater than distance D1”) than a level of a bottommost lower surface of the second isolation insulating pattern 104 (Fig. 1C, paragraph 0035).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang345 in view of Kim to form a bottommost surface of the first isolation insulating pattern is at a level higher than a level of a bottommost lower surface of the second isolation insulating pattern, as taught by Wang709, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 15, Wang345 further discloses the semiconductor device of claim 13, wherein the first isolation insulating pattern (right 1402 in Fig. 14D) comprises a plurality of side surfaces (see Fig. 14D, wherein right 1402 having four sides: top surface, bottom surface, left surface, and right surface) having different slopes, and wherein the second isolation insulating pattern (left 1402 in Fig. 14D) comprises a plurality of side surfaces (top surface and bottom surface in Fig. 14D) having one slope (see Fig. 14D, wherein top surface and bottom surface of 1402 have horizontal surface).
Regarding claim 16, Wang345 (utilized different elements for a second isolation insulating pattern as applied in claim 13 in the above) discloses a semiconductor device, comprising:
a substrate 210 (Fig. 14C’, paragraph 0031);
active regions 230 (Figs. 14C’ and 14D, paragraph 0033) extending in a first horizontal direction (horizontal direction in Fig. 14D) on the substrate 210 (Fig. 14C’), wherein the active regions 230 (Figs. 14C’ and 14D) comprise a first active region (right portion of top 230 in Fig. 14D) and a second active region (right portion of bottom 230 in Fig. 14D) spaced apart from each other in a second horizontal direction (vertical direction in Fig. 14D) perpendicular to the first horizontal direction (horizontal direction in Fig. 14D), and a third active region (left portion of top 230 in Fig. 14D) and a fourth active region (left portion of bottom 230 in Fig. 14D) spaced apart from each other in the second horizontal direction (vertical direction in Fig. 14D);
gate structures 102 (Fig.14D, paragraph 0034) comprising a first gate structure (second 102 from the right corner of Fig. 14D), a second gate structure (third 102 from the right corner of Fig. 14D), a third gate structure (second 102 from the left corner of Fig. 14D), and a fourth gate structure (third 102 from the left corner of Fig. 14D), wherein the first gate structure (second 102 from the right corner of Fig. 14D) and the second gate structure (third 102 from the right corner of Fig. 14D) intersect the first active region (right portion of top 230 in Fig. 14D) and the second active region (right portion of bottom 230 in Fig. 14D) and are spaced apart from each other, and wherein the third gate structure (second 102 from the left corner of Fig. 14D) and the fourth gate structure (third 102 from the left corner of Fig. 14D) intersect the third active region (left portion of top 230 in Fig. 14D) and the fourth active region (left portion of bottom 230 in Fig. 14D) and are spaced apart from each other;
source/drain regions 250 (Fig. 14C’, paragraph 0034) comprising a first source/drain region (left 250 in Fig. 14C’) on the first active region (left 230 in Fig. 14C’) between (see Fig. 14D and 14C’, wherein left 250 (Fig. 14C’) formed between top portion of second 102 (Fig. 14D) and top portion of third 102 (Fig. 14D) from the right corner of Fig. 14D) the first gate structure (second 102 from the right corner of Fig. 14D) and the second gate structure (third 102 from the right corner of Fig. 14D), a second source/drain region (right 250 in Fig. 14C’) on the second active region (right 230 in Fig. 14C’) between (see Fig. 14D and 14C’, wherein right 250 (Fig. 14C’) formed between bottom portion of second 102 (Fig. 14D) and bottom portion of third 102 (Fig. 14D) from the right corner of Fig. 14D) the first gate structure (second 102 from the right corner of Fig. 14D) and the second gate structure (third 102 from the right corner of Fig. 14D), a third source/drain region (portion of 250 contacting top 230 between second 102 and third 102 from the left corner of Fig. 14D) on the third active region (left portion of top 230 in Fig. 14D) between the third gate structure (second 102 from the left corner of Fig. 14D) and the fourth gate structure (third 102 from the left corner of Fig. 14D), and a fourth source/drain region (portion of 250 contacting bottom 230 between second 102 and third 102 from the left corner of Fig. 14D) on the fourth active region (left portion of bottom 230 in Fig. 14D) between the third gate structure (second 102 from the left corner of Fig. 14D) and the fourth gate structure (third 102 from the left corner of Fig. 14D);
a first isolation insulating pattern (right 1402 in Fig. 14D, paragraph 0073); and
a second isolation insulating pattern (left 1402 and left 1002 in Fig. 14D, paragraph 0074), wherein the first isolation insulating pattern 1402 (Fig. 14C’) is spaced apart from the first source/drain region (left 250 in Fig. 14C’) and the second source/drain region (right 250 in Fig. 14C’); and
wherein the first isolation insulating pattern (right 1402 in Fig. 14D) and the second isolation insulating pattern (left 1402 and left 1002 in Fig. 14D) comprise different materials (see paragraph 0074, wherein “The isolation structure 1402 is formed from a material different from the material used to fabricate the dielectric structure 1002”) from each other.
Wang345 does not disclose contact plugs comprising a first contact plug connected to the first source/drain region, a second contact plug connected to the second source/drain region, a third contact plug connected to the third source/drain region, and a fourth contact plug connected to the fourth source/drain region;
a first isolation insulating pattern between the first contact plug and the second contact plug; and
a second isolation insulating pattern between the third contact plug and the fourth contact plug, and wherein the second isolation insulating pattern contacts the third source/drain region and the fourth source/drain region.
Kim discloses contact plugs (612 and 614 in Fig. 2C, paragraph 0046) comprising a first contact plug (612 of C2 in Fig. 2C) connected to the first source/drain region (first 300 from the right corner of Fig. 2C, paragraph 0042), a second contact plug (614 of C2 in Fig. 2C) connected to the second source/drain region (second 300 from the right corner of Fig. 2C), a third contact plug (612 of C1 in Fig. 2C) connected to the third source/drain region (first 300 from the left corner of Fig. 2C), and a fourth contact plug (614 of C1 in Fig. 2C) connected to the fourth source/drain region (second 300 from the left corner of Fig. 2C);
a first isolation insulating pattern (400 of C2 in Fig. 2C, paragraph 0046) between the first contact plug (612 of C2 in Fig. 2C) and the second contact plug (614 of C2 in Fig. 2C); and
a second isolation insulating pattern (400 of C1 in Fig. 2C, paragraph 0046) between the third contact plug (612 of C1 in Fig. 2C) and the fourth contact plug (614 of C1 in Fig. 2C), and wherein the second isolation insulating pattern (400 of C1 in Fig. 2C) contacts the third source/drain region (first 300 from the left corner of Fig. 2C) and the fourth source/drain region (second 300 from the left corner of Fig. 2C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang345 to form contact plugs comprising a first contact plug connected to the first source/drain region, a second contact plug connected to the second source/drain region, a third contact plug connected to the third source/drain region, and a fourth contact plug connected to the fourth source/drain region; a first isolation insulating pattern between the first contact plug and the second contact plug; and a second isolation insulating pattern between the third contact plug and the fourth contact plug, and wherein the second isolation insulating pattern contacts the third source/drain region and the fourth source/drain region, as taught by Kim, since the cell contact 610 (Kim, Fig. 2C, paragraph 0051) may be separated into the NMOS contact 612 (Kim, Fig. 2C, paragraph 0051) and the PMOS contact 614 (Kim, Fig. 2C, paragraph 0051) by the insulation pattern 400 (Kim, Fig. 2C, paragraph 0051) in the cell area C, the power signal may be transferred to one of the NMOS contact 612 (Kim, Fig. 2C, paragraph 0051) and the PMOS contact 614 (Kim, Fig. 2C, paragraph 0051) such that the NMOS contact 612 (Kim, Fig. 2C, paragraph 0051) and the PMOS contact 614 (Kim, Fig. 2C, paragraph 0051) in the same cell area C (Kim, Fig. 2C, paragraph 0051) might not simultaneously receive the power signal from the same power rail 700 (Kim, Fig. 2C, paragraph 0051).
Wang345 and Kim do not disclose a bottommost surface of the first isolation insulating pattern is at a level higher than a level of a bottommost lower surface of the second isolation insulating pattern.
Wang709 discloses a bottommost surface of the first isolation insulating pattern 103 (Fig. 1C, paragraph 0035) is at a level higher (see paragraph 0035, wherein “height H2 can be greater than height H1 and distance D2 can greater than distance D1”) than a level of a bottommost lower surface of the second isolation insulating pattern 104 (Fig. 1C, paragraph 0035).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Wang345 in view of Kim to form a bottommost surface of the first isolation insulating pattern is at a level higher than a level of a bottommost lower surface of the second isolation insulating pattern, as taught by Wang709, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 17, Wang345 further discloses the semiconductor device of claim 13, wherein the first isolation insulating pattern (right 1402 in Fig. 14D) is between the first source/drain region (portion of 250 contacting top 230 between second 102 and third 102 from the right corner of Fig. 14D) and the second source/drain region (portion of 250 contacting bottom 230 between second 102 and third 102 from the right corner of Fig. 14D), and wherein the second isolation insulating pattern (left 1402 in Fig. 14D) is between the third source/drain region (portion of 250 contacting top 230 between second 102 and third 102 from the left corner of Fig. 14D) and the fourth source/drain region (portion of 250 contacting bottom 230 between second 102 and third 102 from the left corner of Fig. 14D).
Allowable Subject Matter
Claims 1-12 and 18-20 are allowed. The following is an examiner’s statement of reasons for allowance: a closest prior art, Wang et al. (US 2019/0006345), discloses source/drain regions 250 (Fig. 14C’, paragraph 0034) comprising a first source/drain region (left 250 in Fig. 14C’) on the first active region (left 230 in Fig. 14C’) between (see Fig. 14D and 14C’, wherein left 250 (Fig. 14C’) formed between top portion of second 102 (Fig. 14D) and top portion of third 102 (Fig. 14D) from the right corner of Fig. 14D) the first gate structure (second 102 from the right corner of Fig. 14D) and the second gate structure (third 102 from the right corner of Fig. 14D), a second source/drain region (right 250 in Fig. 14C’) on the second active region (right 230 in Fig. 14C’) between (see Fig. 14D and 14C’, wherein right 250 (Fig. 14C’) formed between bottom portion of second 102 (Fig. 14D) and bottom portion of third 102 (Fig. 14D) from the right corner of Fig. 14D) the first gate structure (second 102 from the right corner of Fig. 14D) and the second gate structure (third 102 from the right corner of Fig. 14D), a third source/drain region (portion of 250 contacting top 230 between second 102 and third 102 from the left corner of Fig. 14D) on the third active region (left portion of top 230 in Fig. 14D) between the third gate structure (second 102 from the left corner of Fig. 14D) and the fourth gate structure (third 102 from the left corner of Fig. 14D), and a fourth source/drain region (portion of 250 contacting bottom 230 between second 102 and third 102 from the left corner of Fig. 14D) on the fourth active region (left portion of bottom 230 in Fig. 14D) between the third gate structure (second 102 from the left corner of Fig. 14D) and the fourth gate structure (third 102 from the left corner of Fig. 14D); a first isolation insulating pattern (right 1402 in Fig. 14D, paragraph 0073); and a second isolation insulating pattern (left 1402 in Fig. 14D, paragraph 0073) but fails to disclose contact plugs comprising a first contact plug connected to the first source/drain region, a second contact plug connected to the second source/drain region, a third contact plug connected to the third source/drain region, and a fourth contact plug connected to the fourth source/drain region; a first isolation insulating pattern between the first contact plug and the second contact plug; and a second isolation insulating pattern between the third contact plug and the fourth contact plug, wherein a first length in a vertical direction of the first isolation insulating pattern is smaller than a second length in the vertical direction of the second isolation insulating pattern, wherein the vertical direction is perpendicular to an upper surface of the substrate. Additionally, the prior art does not teach or suggest a semiconductor device, comprising: a first length in a vertical direction of the first isolation insulating pattern is smaller than a second length in the vertical direction of the second isolation insulating pattern, wherein the vertical direction is perpendicular to an upper surface of the substrate in combination with other elements of claim 1.
In addition, a closest prior art, Wang et al. (US 2019/0006345), discloses source/drain regions 250 (Fig. 14C’, paragraph 0034) comprising a first source/drain region (left 250 in Fig. 14C’) on the first active region (portion of AP on the left side of SDBR in Fig. 11A), a second source/drain region (right 250 in Fig. 14C’) on the second active region (right 230 in Fig. 14C’), a third source/drain region (portion of 250 contacting top 230 between second 102 and third 102 from the left corner of Fig. 14D) on the third active region (left portion of top 230 in Fig. 14D), and a fourth source/drain region (portion of 250 contacting bottom 230 between second 102 and third 102 from the left corner of Fig. 14D) on the fourth active region (left portion of bottom 230 in Fig. 14D); a first isolation insulating pattern (right 1402 in Fig. 14D, paragraph 0073); a second isolation insulating pattern (left 1402 in Fig. 14D, paragraph 0073) but fails to disclose contact plugs comprising a first contact plug connected to the first source/drain region, a second contact plug connected to the second source/drain region, a third contact plug connected to the third source/drain region, and a fourth contact plug connected to the fourth source/drain region; a first isolation insulating pattern between the first contact plug and the second contact plug; and a second isolation insulating pattern between the third contact plug and the fourth contact plug, wherein the first isolation insulating pattern has a side surface profile different from a side surface profile of the second isolation insulating pattern. Additionally, the prior art does not teach or suggest a semiconductor device, comprising: the first isolation insulating pattern has a side surface profile different from a side surface profile of the second isolation insulating pattern in combination with other elements of claim 18.
A closest prior art, Wang et al. (US 2019/0006345), discloses a semiconductor device, comprising: a substrate 210 (Fig. 14C’, paragraph 0031); active regions 230 (Figs. 14C’ and 14D, paragraph 0033) extending in a first horizontal direction (horizontal direction in Fig. 14D) on the substrate 210 (Fig. 14C’), wherein the active regions 230 (Figs. 14C’ and 14D) comprise a first active region (right portion of top 230 in Fig. 14D) and a second active region (right portion of bottom 230 in Fig. 14D) spaced apart from each other in a second horizontal direction (vertical direction in Fig. 14D) perpendicular to the first horizontal direction (horizontal direction in Fig. 14D), and a third active region (left portion of top 230 in Fig. 14D) and a fourth active region (left portion of bottom 230 in Fig. 14D) spaced apart from each other in the second horizontal direction (vertical direction in Fig. 14D); gate structures 102 (Fig.14D, paragraph 0034) comprising a first gate structure (second 102 from the right corner of Fig. 14D), a second gate structure (third 102 from the right corner of Fig. 14D), a third gate structure (second 102 from the left corner of Fig. 14D), and a fourth gate structure (third 102 from the left corner of Fig. 14D), wherein the first gate structure (second 102 from the right corner of Fig. 14D) and the second gate structure (third 102 from the right corner of Fig. 14D) intersect the first active region (right portion of top 230 in Fig. 14D) and the second active region (right portion of bottom 230 in Fig. 14D) and are spaced apart from each other in the first horizontal direction (horizontal direction in Fig. 14D), and the third gate structure (second 102 from the left corner of Fig. 14D) and the fourth gate structure (third 102 from the left corner of Fig. 14D) intersect the third active region (left portion of top 230 in Fig. 14D) and the fourth active region (left portion of bottom 230 in Fig. 14D) and are spaced apart from each other in the first horizontal direction (horizontal direction in Fig. 14D); source/drain regions 250 (Fig. 14C’, paragraph 0034) comprising a first source/drain region (left 250 in Fig. 14C’) on the first active region (left 230 in Fig. 14C’) between (see Fig. 14D and 14C’, wherein left 250 (Fig. 14C’) formed between top portion of second 102 (Fig. 14D) and top portion of third 102 (Fig. 14D) from the right corner of Fig. 14D) the first gate structure (second 102 from the right corner of Fig. 14D) and the second gate structure (third 102 from the right corner of Fig. 14D), a second source/drain region (right 250 in Fig. 14C’) on the second active region (right 230 in Fig. 14C’) between (see Fig. 14D and 14C’, wherein right 250 (Fig. 14C’) formed between bottom portion of second 102 (Fig. 14D) and bottom portion of third 102 (Fig. 14D) from the right corner of Fig. 14D) the first gate structure (second 102 from the right corner of Fig. 14D) and the second gate structure (third 102 from the right corner of Fig. 14D), a third source/drain region (portion of 250 contacting top 230 between second 102 and third 102 from the left corner of Fig. 14D) on the third active region (left portion of top 230 in Fig. 14D) between the third gate structure (second 102 from the left corner of Fig. 14D) and the fourth gate structure (third 102 from the left corner of Fig. 14D), and a fourth source/drain region (portion of 250 contacting bottom 230 between second 102 and third 102 from the left corner of Fig. 14D) on the fourth active region (left portion of bottom 230 in Fig. 14D) between the third gate structure (second 102 from the left corner of Fig. 14D) and the fourth gate structure (third 102 from the left corner of Fig. 14D); a first isolation insulating pattern (right 1402 in Fig. 14D, paragraph 0073); and a second isolation insulating pattern (left 1402 in Fig. 14D, paragraph 0073) but fails to teach contact plugs comprising a first contact plug connected to the first source/drain region, a second contact plug connected to the second source/drain region, a third contact plug connected to the third source/drain region, and a fourth contact plug connected to the fourth source/drain region; a first isolation insulating pattern between the first contact plug and the second contact plug; and a second isolation insulating pattern between the third contact plug and the fourth contact plug, wherein a first length in a vertical direction of the first isolation insulating pattern is smaller than a second length in the vertical direction of the second isolation insulating pattern, wherein the vertical direction is perpendicular to an upper surface of the substrate as the context of claim 1. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 2-12 depend on claim 1.
In addition, a closest prior art, Wang et al. (US 2019/0006345), discloses a semiconductor device, comprising: a substrate 210 (Fig. 14C’, paragraph 0031); active regions 230 (Figs. 14C’ and 14D, paragraph 0033) extending in a first horizontal direction (horizontal direction in Fig. 14D) on the substrate 210 (Fig. 14C’), wherein the active regions 230 (Figs. 14C’ and 14D) comprise a first active region (right portion of top 230 in Fig. 14D), a second active region (right portion of bottom 230 in Fig. 14D), a third active region (left portion of top 230 in Fig. 14D), and a fourth active region (left portion of bottom 230 in Fig. 14D) spaced apart from each other; source/drain regions 250 (Fig. 14C’, paragraph 0034) comprising a first source/drain region (left 250 in Fig. 14C’) on the first active region (portion of AP on the left side of SDBR in Fig. 11A), a second source/drain region (right 250 in Fig. 14C’) on the second active region (right 230 in Fig. 14C’), a third source/drain region (portion of 250 contacting top 230 between second 102 and third 102 from the left corner of Fig. 14D) on the third active region (left portion of top 230 in Fig. 14D), and a fourth source/drain region (portion of 250 contacting bottom 230 between second 102 and third 102 from the left corner of Fig. 14D) on the fourth active region (left portion of bottom 230 in Fig. 14D); a first isolation insulating pattern (right 1402 in Fig. 14D, paragraph 0073); a second isolation insulating pattern (left 1402 in Fig. 14D, paragraph 0073) but fails to teach contact plugs comprising a first contact plug connected to the first source/drain region, a second contact plug connected to the second source/drain region, a third contact plug connected to the third source/drain region, and a fourth contact plug connected to the fourth source/drain region; a first isolation insulating pattern between the first contact plug and the second contact plug; and a second isolation insulating pattern between the third contact plug and the fourth contact plug, wherein the first isolation insulating pattern has a side surface profile different from a side surface profile of the second isolation insulating pattern as the context of claim 18. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 19-20 depend on claim 18.
Response to Arguments
1. Applicant's arguments filed 03/03/2026 have been fully considered.
Applicant's arguments with respect to claims 13 and 15-17 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAMONT B KOO whose telephone number is (571)272-0984. The examiner can normally be reached 7:00 AM - 3:30 PM.
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813