DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in Korean Patent Application No. 10-2022-0032735, filed on 03/16/2022.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/27/2026 has been entered.
Response to Amendment
Applicant's amendments on 2/27/2026 have been reviewed and entered. Claims 1, 16, and 18 have been amended, claims 19-20 have been canceled, and claims 21-22 have been added as new claims by the Applicant. Claims 1-9, 16-18, and 21-22 remain for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1-9 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu (US 2022/0045096 A1) in view of Lee (US 2015/0340377 A1).
Regarding claim 1, Ryu teaches a three-dimensional (3D) semiconductor device (three-dimensional semiconductor memory device, Fig. 1, [0004] and [0040]) comprising:
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a memory block (semiconductor memory device between the first cutting line WLC1 and the second cutting line WLC2, Figs. 3 and 8, [0041]; the embodiment considered is shown in Fig. 8 which comprises three sub-cutting lines SLC1-3, however, no cross-section of the embodiment in Fig. 8 is provided. Therefore, Fig. 3 will be utilized as the cross-section by referring the sub-cutting lines SLC1, SLC2, and SLC3 in Fig. 8 as SLC0, SLC1, and SLC 2, respectively, as shown in Illustrative Fig. 1. Accordingly, SLC0 will be missing in the Fig. 3, but assumed to be there for the embodiment in Fig. 8, and will have the same cross-section as SLC2) including at least one stack structure (lower stacked structure BST and upper stacked structure UST, Illustrative Fig. 1, [0048] and [0050]) having at least one channel plug (first vertical structure VS1, Illustrative Fig. 1, [0062]: “The first vertical structure VS1 may be connected to the bit line BL … “, and therefore the first vertical structure VS1 is the channel plug), the stack structure including a first sub stack (lower stacked structure BST, Fig. 3, [0048]) and a second sub stack (upper stacked structure UST, Illustrative Fig. 1, [0050]) formed over the first sub stack (lower stacked structure BST, Illustrative Fig. 1) and the channel plug (first vertical structure VS1, Illustrative Fig. 1) penetrating the first and second sub stacks (lower stacked structure BST and upper stacked structure UST, Illustrative Fig. 1);
a first separation pattern (sub-cutting line SLC0 and second sub-cutting line SLC2, Illustrative Fig. 1, [0062]) formed in the second sub stack (upper stacked structure UST, Illustrative Fig. 1) of the memory block (semiconductor memory device between the first cutting line WLC1 and the second cutting line WLC2, Illustrative Fig. 1): and
a second separation pattern (second vertical structures VS2 and first sub-cutting line SLC1, Illustrative Fig. 1, [0062]: “… the second vertical structure VS2 may be a dummy vertical structure.”) formed through the first sub stack (lower stacked structure BST, Illustrative Fig. 1) and the second sub stack (upper stacked structure UST, Illustrative Fig. 1) of the memory block (semiconductor memory device between the first cutting line WLC1 and the second cutting line WLC2, Illustrative Fig. 1), the second separation pattern (second vertical structures VS2 (plug-type, see top view in Illustrative Fig. 1) and first sub-cutting line SLC1 (bar-type, see top view in Illustrative Fig. 1)) including a plug type insulation pattern (bottom portion of second vertical structures VS2 (below the first sub-cutting line SLC1) filled with insulating pattern 134, Illustrative Fig. 1, [0064]) positioned in the first sub stack (lower stacked structure BST, Illustrative Fig. 1) and a bar type insulation pattern (first sub-cutting line SLC1 comprising an insulating material, Illustrative Fig. 1, [0165]) positioned in the second sub stack (upper stacked structure UST, Illustrative Fig. 1) disposed on the plug type insulation pattern (bottom portion of second vertical structures VS2 (below the first sub-cutting line SLC1) filled with insulating pattern 134, Illustrative Fig. 1) and positioned in the second sub stack (upper stacked structure UST, Illustrative Fig. 1).
Ryu, however, does not teach that
the plug type insulation pattern has a structure different from a structure of the channel plug (In Ryu’s 3D semiconductor device, the plug type insulating pattern and channel plugs comprise identical layers with identical material compositions).
Lee, on the other hand, teaches a three-dimensional (3D) semiconductor device (vertical memory device, Figs. 1-3, [0035]) comprising individual memory blocks (first region IV, Figs. 1-3, [0039]) including at least one stack structure (comprising ground selection line (GSL) 226, word line 222, string selection line (SSL) 224, and first insulation patterns 115; Figs. 1 and 2B, [0051]: “Each of the GSL 226, the word line 222 and the SSL 224 may be at a single level ( e.g., one of each, each at a different height) or more than one level, and each of the first insulation layer patterns 115 may be interposed therebetween.”, Figs. 1-2, [0037]-[0040]) having at least one channel plug (comprising charge storage structure 160, channels 170, and second insulation layer pattern 180; Figs. 1-2, [0037]-[0040]), the stack structure (comprising ground selection line (GSL) 226, word line 222, string selection line (SSL) 224, and first insulation patterns 115; Fig. 2B) including a first sub stack (word line 222, GSL 226, and first insulation layer patterns 115 in between; Fig. 2B) and a second sub stack (SSL 224 and first insulation layer patterns 115 in between; Fig. 2B) formed over the first sub stack (word line 222, GSL 226, and first insulation layer patterns 115 in between; Fig. 2B) and the channel plug (comprising charge storage structure 160, channels 170, and second insulation layer pattern 180; Fig. 2B) penetrating the first and second sub stacks (GSL 226, word line 222, SSL 224, and first insulation patterns 115; Fig. 2B). Lee further discloses that the 3D semiconductor device also comprises a second separation pattern (isolation pattern 150, Figs. 2B and 3-4, [0056]) formed through the first sub stack (word line 222, GSL 226, and first insulation layer patterns 115 in between; Fig. 2B) and the second sub stack (SSL 224 and first insulation layer patterns 115 in between; Figs. 2B and 3-4) of the memory block (first region IV, Figs. 2B and 3), the second separation pattern (isolation pattern 150, Figs. 2B and 3-4) including a plug type insulation pattern (Figs. 3-4: extension portions 150a are plug-type) positioned in the first sub stack (word line 222, GSL 226, and first insulation layer patterns 115 in between; Figs. 2B and 3-4) and a bar type insulation pattern (Figs. 3-4: connection portions 150b are bar type, i.e. elongated towards third direction) disposed on the plug type insulation pattern (extension portions 150a, Figs. 2-4) and positioned in the second sub stack (SSL 224 and first insulation layer patterns 115 in between; Figs. 2B),
wherein the plug type insulation pattern (extension portions 150a, Figs. 2-4) has a structure ([0060]: “the isolation pattern 150 may include an insulation material, such as silicon oxide. In particular, the isolation pattern 150 may consist essentially of an insulation material.”) different from a structure of the channel plug (comprising charge storage structure 160, channels 170, and second insulation layer pattern 180; Figs. 1-2).
Lee further discloses that by having the extension portions made of an insulating material “coupling between the extension portions 150a and the adjacent channels 170 may be reduced
or prevented.” ([0060]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the structure of the plug type insulation pattern in the 3D semiconductor device of Ryu to be an insulator, as taught by Lee, to obtain the benefit of reducing or preventing the coupling between the plug type insulation pattern and channel plugs. Thus, the combination of Ryu and Lee meets all the limitations of claim 1.
Regarding claim 2, Ryu in view of Lee teaches the 3D semiconductor device of claim 1, wherein
The combination of Ryu and Lee further teaches that
the second separation pattern (second vertical structures VS2 and first sub-cutting line SLC1, Illustrative Fig. 1, [0062]) includes a plurality of the plug type insulation patterns (plurality of second vertical structures VS2 located under the first sub-cutting line SLC1 along the direction DR2 which became a single insulating structure after the modification of the 3D semiconductor device of Ryu according to Lee (see claim 1 rejection above); Illustrative Fig. 1),
wherein the plug type insulation patterns (second vertical structures VS2, Illustrative Fig. 1, [067]) are spaced apart with a set interval in between (Illustrative Fig. 1, top view: the second vertical structures VS2 are spaced at regular intervals), and
wherein each of the plug type insulation patterns (second (bottom) portion of the vertical structure VS2 below the first cutting line SLC1, Illustrative Fig. 1, [0061]-[0062]) are connected to the bar type insulation pattern (first sub-cutting line SLC1, Illustrative Fig. 1, [0062]: first sub-cutting line SLC1 is formed in the first (top) part of the vertical structure VS2).
Regarding claim 3, Ryu in view of Lee teaches the 3D semiconductor device of claim 1, wherein
Ryu further teaches that
the first sub stack (lower stacked structure BST, Illustrative Fig. 1, [0048]) comprises at least one first conductive layer (word lines WL0 to WLn, Illustrative Fig. 1, [0049]) and at least one first insulation layer (first inter-electrode insulating layer 120, Illustrative Fig. 1 (cross-section), [0049]) alternately stacked in a vertical direction (direction DR3, Illustrative Fig. 1: multiple conductive and insulation layers are stacked alternately),
wherein the second sub stack comprises (upper stacked structure UST, Illustrative Fig. 1, [0050]) at least second conductive layer (first upper metal lines SSL and second upper metal lines EL, Illustrative Fig. 1, [0050]) and at least one second insulation layer (first inter-electrode insulating layers 120, Illustrative Fig. 1, [0050]) alternately stacked in the vertical direction (direction DR3, Illustrative Fig. 1: multiple conductive and insulation layers are stacked alternately), and
wherein the second conductive layer (first upper metal lines SSL and second upper metal lines EL, Illustrative Fig. 1, [0050]) extending in a horizontal direction (direction DR1, Illustrative Fig. 1) is electrically isolated by the first separation pattern (sub-cutting line SLC0 and second sub-cutting line SLC2, Illustrative Fig. 1: from top view SLC0 and SLC2 interrupt the second conductive layer).
Regarding claim 4, Ryu in view of Lee teaches the 3D semiconductor device of claim 3, wherein
Lee further teaches that
the channel plug (first vertical structure VS1, Illustrative Fig. 1, [0062]) includes:
a first portion (first portion of the first vertical structure VS1, see Illustrative Fig. 1) formed in the first sub stack structure (lower stacked structure BST, Illustrative Fig. 1, [0048]); and
a second portion (second portion of the first vertical structure VS1, Illustrative Fig. 1) connected to the first portion (Illustrative Fig. 1, the first and second portions are parts of the same structure, and therefore connected), and formed in the second sub stack (upper stacked structure UST, Illustrative Fig. 1, [0050]).
Regarding claim 5, Ryu in view of Lee teaches the 3D semiconductor device of claim 4, wherein
Ryu further teaches that the second portion (first portion of the first vertical structure VS1, Illustrative Fig. 1) is at least partially overlapped with the first portion (second portion of the first vertical structure VS1, Illustrative Fig. 1: the second portion is directly above the first portion; therefore, the two portions overlap in top (plan) view).
Regarding claim 6, Ryu in view of Lee teaches the 3D semiconductor device of claim 3, wherein
Ryu further teaches that
the channel plugs (first vertical structures VS1, see Illustrative Fig. 2 which is a modified version of Ryu’s Fig. 8 according to claim 1, [0062]) are arranged in a matrix (Illustrative Fig. 2) having n rows (n is a natural number greater than 2) (Illustrative Fig. 2 shows 5 rows) and m columns (m is a natural number greater than 2) (Illustrative Fig. 2 shows 19 columns), and
a channel plug in a (m-1)th column (channel plug in the (m-1)th column, Illustrative Fig. 2) is arranged between an adjacent two channel plugs in a mth column (two channel plugs in the (m)th column, Illustrative Fig. 2: channel plug in the (m-1)th column is between the two channel plugs in the (m)th column in the DR2 direction).
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Regarding claim 7, Ryu in view of Lee teaches the 3D semiconductor device of claim 6, wherein
Ryu further teaches that
the bar type insulation pattern (first sub-cutting line SLC1, Illustrative Fig. 2, [0062]) is arranged between an adjacent two channel plugs in a (k± 1)th columns (1<k<m, k is a natural number) (Illustrative Fig. 2: the first sub-cutting line SLC1 is on the plugs in the kth column and between the plugs on the (k-1)th and (k+1)th columns).
Regarding claim 8, Ryu in view of Lee teaches the 3D semiconductor device of claim 1, wherein
Ryu further teaches a slit structure (second cutting line WLC2, Illustrative Fig. 2, [0058]) formed at an edge of the memory block (semiconductor device between the first cutting line WLC1 and the second cutting line WLC2, Illustrative Fig. 2, [0041]: the second cutting line WLC2 forms the right edge of the memory block),
wherein the slit structure (cutting lines WLC1 and WLC2, Illustrative Fig. 2) includes slit portions (first cutting line WLC1 and second cutting line WLC2 form slit portions at two edges of the device, Illustrative Fig. 2) parallel to a column direction (Illustrative Fig. 2: first and second cutting lines WLC1 and WLC2 are parallel to any of the columns),
wherein the first separation pattern (sub-cutting line SLC0 and second sub-cutting line SLC2, Illustrative Fig. 2, [0062]) includes at least two first separation patterns (sub-cutting line SLC0 and second sub-cutting line SLC2, Illustrative Fig. 2), and the first separation patterns (sub-cutting line SLC0 and second sub-cutting line SLC2, Illustrative Fig. 2) are arranged between the slit portions (between the first and second cutting lines WLC1 and WLC2, Illustrative Fig. 2) with an interval (Illustrative Fig. 2), and
wherein the second separation pattern (second vertical structures VS2 and first sub-cutting line SLC1, Illustrative Fig. 2) is arranged between the first separation patterns (sub-cutting line SLC0 and second sub-cutting line SLC2, Illustrative Fig. 2).
Regarding claim 9, Ryu in view of Lee teaches the 3D semiconductor device of claim 8, wherein
Ryu further teaches that
the first separation pattern (sub-cutting line SLC0 and second sub-cutting line SLC2, Illustrative Fig. 2) and the bar type insulation pattern of the second separation pattern (first sub-cutting line SLC1 comprising an insulating material, Illustrative Fig. 2) are parallel to the column direction (see Illustrative Fig. 2).
Regarding claim 21, Ryu in view of Lee teaches the 3D semiconductor device of claim 1,
the combination of Ryu and Lee (a 3D semiconductor device with the plug type insulating pattern is silicon oxide (see claim 1 rejection above)) further teaches a slit structure (first cutting line WLC1, Illustrative Fig. 2, [0041]) formed at an edge (left edge, Illustrative Fig. 2) of the memory block (semiconductor memory device between the first cutting line WLC1, Illustrative Fig. 2),
wherein the structure of the plug type insulating pattern (bottom portion of second vertical structures VS2 (below the first sub-cutting line SLC1) filled with insulating pattern 134, Illustrative Figs. 1-2, [0064]) is substantially same with a structure of the slit structure (first cutting line WLC1, Illustrative Fig. 2: both components are made of silicon oxide).
Regarding claim 22, Ryu in view of Lee teaches the 3D semiconductor device of claim 1, wherein
Ryu further teaches that
the memory block (semiconductor memory device between the first cutting line WLC1 and the second cutting line WLC2, Illustrative Fig. 1) includes a plurality of channel plugs (first vertical structures VS1, Illustrative Fig. 1),
the first separation pattern (sub-cutting line SLC0 and second sub-cutting line SLC2, Illustrative Fig. 1) is disposed between adjacent channel plugs (first vertical structures VS1, Illustrative Figs. 1-2) without contacting the channel plugs (first vertical structures VS1, Illustrative Figs. 1-2).
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2015/0340377 A1) in view of Ryu (US 2022/0045096 A1).
Regarding claim 16, Lee teaches a three-dimensional (3D) semiconductor device (vertical memory device, Figs. 1-3, [0035]) comprising:
a first sub stack (comprising word line 222, GSL 226, and first insulation layer patterns 115 in between; Fig. 2B, [0051]: “Each of the GSL 226, the word line 222 and the SSL 224 may be at a single level (e.g., one of each, each at a different height) or more than one level, and each of the first insulation layer patterns 115 may be interposed therebetween. In an example embodiments, the GSL 226 and the SSL 224 may be at one level (e.g., two of each at different heights), respectively, and the word line 222 may be at 4 levels between the GSL 226 and the SSL 217. However, the GSL 226 and the SSL 224 may be at two levels, and the word line 222 may be formed at 2, 8 or 16 levels.”, and accordingly the embodiment considered here, has at least two layers of each GSL 226 and SSL 224) including at least one first conductive layer (any of GSL 226 or word line 222, Fig. 2B, [0052]: “the plurality of gate electrodes 222, 224 and 226 may include a metal and/or a metal nitride with low electrical resistance (e.g., tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride and/or platinum.)”) and at least one first insulation layer (first insulation layer patterns 115, Fig. 2B) alternately stacked in a vertical direction (first direction, Fig. 2B);
a second sub stack (comprising SSL 224 and first insulation layer patterns 115 in between; Fig. 2B, [0051]) including at least one second conductive layer (SSL 224, Fig. 2B) and at least one second insulation layer (first insulation layer patterns 115; Fig. 2B) alternately stacked on the first sub stack (comprising word line 222, GSL 226, and first insulation layer patterns 115 in between; Fig. 2B) in the vertical direction (first direction, Fig. 2B);
slit structures (third insulation layer pattern 230, Figs. 1-2, [0038]-[0039]: “The substrate 100 may include a first region IV and a second region V. In some example embodiments, the first region IV may be a cell region where the channel 170 may be disposed, and the second region V may be a word line cut region that may separate the gate electrodes 222, 224 and 226. A plurality of first regions IV may be arranged in the second direction, and each of the first regions IV may extend in the third direction. The second region V may be arranged between the first regions IV, and the second region V may extend in the third direction.”, and accordingly, the embodiment considered here has multiple first regions IV. Therefore, the slit structures (third insulation layer pattern 230) are at both ends (left and right ends of Figs. 2A-B) of each cell region IV) extending through the first (comprising word line 222, GSL 226, and first insulation layer patterns 115 in between; Fig. 2B) and second (comprising SSL 224 and first insulation layer patterns 115 in between; Fig. 2B) sub stacks;
channel plugs (each channel plug comprising charge storage structure 160, channels 170, and second insulation layer pattern 180; Figs. 1-2, [0037]-[0040]) formed through the first sub stack (comprising word line 222, GSL 226, and first insulation layer patterns 115 in between; Figs. 1-2) and the second sub stack (comprising SSL 224 and first insulation layer patterns 115 in between; Figs. 1-2);
at least one first sub separation pattern (extension portions 150a of the isolation pattern 150, Figs. 2-4, [0056]) formed through the first sub stack (comprising word line 222, GSL 226, and first insulation layer patterns 115 in between; Figs. 2-4) to cut at least one first conductive layers (GSL 226 and word line 222, Figs. 1 and 2B), the first sub separation pattern (extension portions 150a of the isolation pattern 150, Figs. 3-4) having a cylindrical shape (Figs. 3-4); and
a second sub separation pattern (connection portion 150b of the isolation pattern 150, Figs. 2-4, [0056]) formed through the second sub stack (comprising SSL 224 and first insulation layer patterns 115 in between; Fig. 2B) to cut the at least one second conductive layer (SSL 224, Fig. 2B), the second sub separation pattern (connection portion 150b of the isolation pattern 150, Figs. 2-4) having a bar shape (Figs. 3-4: connection portion 150b has a bar shape), and the second sub separation pattern (connection portion 150b, Figs. 3-4) being contacted with the at least one first separation pattern (extension portions 150a, Figs. 3-4),
wherein the first (extension portions 150a, Figs. 1-2) and second sub separation patterns (connection portion 150b, Figs. 1-2) are arranged between the slit structures (third insulation layer pattern 230, Figs. 1-2: each first region IV has a third insulation layer pattern 230 on each of its left and right side), and a material constituting the first sub separation pattern (extension portions 150a, Figs. 2-4, [0060]: “silicon oxide”) and a material constituting the second sub separation pattern (connection portions 150b, Figs. 2-4, [0060]: “silicon oxide”) are substantially identical to each other (“silicon oxide”).
Lee, however, is silent on the material composition of the slit structures (third insulation layer pattern 230, Figs. 1-2), and therefore does not teach that
a material constituting the slit structure, a material constituting the first sub separation pattern and a material constituting the second sub separation pattern are substantially identical to each other.
Ryu, on the other hand, teaches an analogous 3D semiconductor device (three-dimensional semiconductor memory device, Fig. 1, [0004] and [0040]), wherein the slit structures (first cutting line WLC1 and second cutting line WLC2, Fig. 3, [0041]) comprises silicon oxide ([0059]: “Each of the first cutting line WLC1 and the second cutting line WLC2 may contain, e.g., at least one of silicon oxide, ...”).
Selection of a known material based on its suitability for its intended use supported a prima facie obviousness (see MPEP 2143). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have selected silicon oxide as the material of the slit structure in the 3D semiconductor device of Lee, as taught by Lee, to be able to obtain the predictable result of reliably isolating adjacent memory blocks. Considering that the first and second sub separation patterns in the 3D semiconductor device of Lee is also silicon oxide (see above), the combination of Lee and Ryu leads to a 3D semiconductor device wherein
a material constituting the slit structure, a material constituting the first sub separation pattern and a material constituting the second sub separation pattern are substantially identical to each other.
Regarding claim 17, Lee in view of Ryu teaches the 3D semiconductor device of claim 16, wherein
Lee further teaches that
the first sub separation pattern (extension portions 150a of the isolation pattern 150, Fig. 2A) is arranged between the channel plugs (each channel plug comprising charge storage structure 160, channels 170, and second insulation layer pattern 180; Fig. 2A).
Regarding claim 18, Lee in view of Ryu teaches the 3D semiconductor device of claim 16, wherein
The combination of Lee and Ryu (a 3D semiconductor device where the slit structures are also silicon oxide (see claim 16 rejection above)) further teaches that
a structure of the first sub separation pattern (extension portions 150a of the isolation pattern 150, Figs. 2A-B) is different from structures of the channel plugs (each channel plug comprising charge storage structure 160, channels 170, and second insulation layer pattern 180; Figs. 2A-B), and the structure of the first sub separation pattern (extension portions 150a of the isolation pattern 150, Figs. 2A-B) is same with structures of the slit structures (third insulation layer pattern 230, Figs. 2A-B; both structures are silicon oxide layers (see claim 16 rejection above)).
Response to Arguments
It has been acknowledged that the applicant amended claims 1, 16, and 18, canceled claims 19-20, and added claims 21-22 as new claims per response dated on 2/27/2026. Applicant's arguments with respect to claims have been fully considered.
The Examiner agrees with the Applicant that amended independent claims 1 and 16 have overcome the rejections based on Ryu (US 2022/0045096 A1) as set forth in the final office action mailed on 12/2/2025. However, independent claims 1 and 16 are now rejected under new grounds based on a new prior art, Lee (US 2015/0340377 A1), combined with Ryu. All the dependent claims are also rejected by the combination of Ryu and Lee.
For the purpose of compact prosecution, the Examiner notes, however, that incorporating limitations related to the shape of separation patterns/ channel plugs and/or emphasizing distinguishing features of the first separation pattern 126 might render independent claims 1 and 16 overcome their respective rejections.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cho (US 9,786,673 B1) teaches a memory device with separation patterns, which is relevant to all claims.
Lee (US 2014/0063890 A1) teaches a memory device with separation patterns, which is relevant to all claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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