Prosecution Insights
Last updated: April 19, 2026
Application No. 18/085,699

SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND METHOD FOR FABRICATING THE SAME

Non-Final OA §102§103
Filed
Dec 21, 2022
Examiner
SPALLA, DAVID C
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
89%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
703 granted / 836 resolved
+16.1% vs TC avg
Minimal +5% lift
Without
With
+4.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
18 currently pending
Career history
854
Total Applications
across all art units

Statute-Specific Performance

§103
47.7%
+7.7% vs TC avg
§102
34.4%
-5.6% vs TC avg
§112
8.6%
-31.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 836 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 12/21/2022 and 09/03/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 4, 6 and 7 are rejected under 35 U.S.C. 102(a(1) as being anticipated by US PG Pub 2016/0254347 to Tsuchiko et al (hereinafter Tsuchiko). Regarding Claim 1, Tsuchiko discloses a semiconductor substrate, comprising: a base substrate (802, Fig. 10E); a first epitaxial layer (804) on the base substrate, the first epitaxial layer having a first conductivity type [0055]; a second epitaxial layer (805) on the first epitaxial layer, the second epitaxial layer having the first conductivity type [0055]; a first well region (810) in the first epitaxial layer and the second epitaxial layer, the first well region having a second conductivity type different from the first conductivity type [0057]; and a second well region (810) in the first epitaxial layer and the second epitaxial layer, the second well region having the second conductivity type and being spaced apart from the first well region, wherein a doping concentration of the first epitaxial layer is greater than a doping concentration of the second epitaxial layer [0055], and wherein a depth of each of the first well region and the second well region is greater than a thickness of the second epitaxial layer (Fig. 10E). Regarding Claim 4, Tsuchiko discloses the semiconductor substrate as claimed in Claim 1, wherein a thickness of the first epitaxial layer is 0.1.mu.m to 2.0.mu.m [0055]. Regarding Claim 6, Tsuchiko discloses the semiconductor substrate as claimed in Claim 1, wherein the doping concentration of the first epitaxial layer is 1E.sup.16 cm.sup.-3 to 1E.sup.21 cm.sup.-3 [0055]. Regarding Claim 7, Tsuchiko discloses the semiconductor substrate as claimed in Claim 1, wherein the doping concentration of the second epitaxial layer is 1E.sup.11 cm.sup.-3 to 1E.sup.17 cm.sup-3. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Tsuchiko. Regarding Claim 5, Tsuchiko discloses the semiconductor substrate as claimed in Claim 1, wherein the thickness of the second epitaxial layer is 0.1.mu.m to 1.0.mu.m. However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the structure of Tsuchiko wherein the second epitaxial layer has a thickness in a range as claimed by Applicant since the range claimed by Applicant was within the working ranges of Tsuchiko as detailed in the references would have created a thick enough layer for the transistor structure formed by Tsuchiko. Regarding Claim 9, Tsuchiko discloses the semiconductor substrate as claimed in Claim 1, but does not disclose wherein the first conductivity type is a p-type, and the second conductivity type is an n-type. However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the structure of Tsuchiko wherein the first conductivity type is a p-type, and the second conductivity type is an n-type since such a limitations would merely require the reverse doping profiles to form a p-PTS vs a n-PTS (punch-through stopper) Allowable Subject Matter Claims 10-20 are allowed. Claims 2, 3 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 2 requires the semiconductor substrate as claimed in Claim 1 include the base substrate having the first conductivity type. Tsuchiko claims the opposite conductivity type. While conductivity types can be swapped within the art, it is not apparent from Tsuchiko that the substrate should have the same conductivity type as the epitaxial layers. Claim 3 depends on Claim 2 and is allowable for at least the reasons above. Claim 8 requires the wells be separated by 0.15.mu.m or less. The wells of Tsuchiko are not with a range claimed by Applicant and it would not have been obvious for them to be placed in such proximity. Claim 10 recites a semiconductor substrate, comprising: a base substrate having a first conductivity type; a first epitaxial layer on the base substrate, the first epitaxial layer having the first conductivity type; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having the first conductivity type; and a well region which extends from an upper surface of the second epitaxial layer toward the base substrate, the well region having a second conductivity type different from the first conductivity type, wherein a doping concentration of the first epitaxial layer is greater than a doping concentration of the second epitaxial layer, wherein a thickness of the first epitaxial layer is 0.1.mu.m to 2.0.mu.m, wherein a thickness of the second epitaxial layer is 0.1.mu.m to 1.0.mu.m, and wherein a depth of the well region is greater than the thickness of the second epitaxial layer. Claim 10 requires the base substrate have the first conductivity type. Tsuchiko claims the opposite conductivity type. While conductivity types can be swapped within the art, it is not apparent from Tsuchiko that the substrate should have the same conductivity type as the epitaxial layers. Claims 11-15 depend on Claim 10 and are allowable for at least the reasons above. Claim 16 recites a semiconductor device, comprising: a base substrate; a first epitaxial layer on the base substrate, the first epitaxial layer having a first conductivity type; a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having the first conductivity type; a first well region having a second conductivity type different from the first conductivity type, the first well region being in the first epitaxial layer and the second epitaxial layer; and a first element on the first well region, the first element including: active patterns sequentially stacked on the first epitaxial layer and spaced apart from each other, a gate electrode which intersects each of the active patterns and surrounds side surfaces of each of the active patterns, and a source/drain region connected to each of the active patterns and having the first conductivity type, on side surfaces of the gate electrode, wherein a doping concentration of the first epitaxial layer is greater than a doping concentration of the second epitaxial layer, and wherein a depth of the first well region is greater than a thickness of the second epitaxial layer. Claim 16 requires a first element on the first well region with the additional limitations required by Applicant on the first element. Tsuchiko does not disclose such a device being on the well and it is not apparent for such a device to be formed on the well. Claims 17-20 depend on Claim 17 and are allowable for at least the reasons of Claims 16. US Patent No. 11,456,373 (“Chan”), US PG 2021/0098454 (“Yang”), US PG Pub 2020/0006549 (“Sadovnikov”), US Patent No. 9,941,359 (“Mears”), US Patent No. 9,525,031 (“Yu”) are cited as further examples of relevant references in the art for comparison to Applicant’s invention. Yang, for example, uses a well region to form a first element similar to that claimed by Applicant. However, Yang does not for a second epitaxial layer over a first epitaxial layer having a lower doping amount of the same conductivity among other missing limitations. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID C SPALLA/ Primary Examiner, Art Unit 2893
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Prosecution Timeline

Dec 21, 2022
Application Filed
Mar 07, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
89%
With Interview (+4.7%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 836 resolved cases by this examiner. Grant probability derived from career allow rate.

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