Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1 rejected under 35 U.S.C. 103 as being unpatentable over Liao (CN 103515437) of record, in view of Tang (CN 108281436) of record.
Regarding Claim 1
FIG. 2 of Liao discloses a semiconductor memory device comprising: a semiconductor region including a first active region (104) for a first memory transistor (100) and a plurality of depressions for trench isolation (112); a plurality of insulating regions respectively provided at the depressions of the semiconductor region; a first gate electrode (122) that extends in a first direction from one to another of, among the plurality of insulating regions, a first insulating region and a second insulating region that are next to one another, the first gate electrode passing over the first active region; and a first gate insulation film provided between the first gate electrode and the first active region [0010], wherein: the first active region of the semiconductor region is provided between the first insulating region and the second insulating region; one of the first insulating region or the second insulating region includes an adjacent region and a distant region each located under the first gate electrode, wherein a thickness of the distant region is greater than a thickness of the adjacent region; the adjacent region is adjacent to the first active region under the first gate electrode; the distant region is adjacent to the adjacent region under the first gate electrode; the adjacent region is provided between the distant region and the first active region; the semiconductor region includes a first conductive region (126) and a second conductive region (126) provided between the first insulating region and the second insulating region (FIG. 4); and the first conductive region, the first active region and the second conductive region are arrayed in a second direction crossing the first direction.
With respect to “a semiconductor memory device”, statements in the preamble reciting the purpose or intended use of the claimed invention must be evaluated to determine whether the recited purpose or intended use results in a structural difference (or, in the case of process claims, manipulative difference) between the claimed invention and the prior art. If so, the recitation serves to limit the claim. See, e.g., In re Otto, 312 F.2d 937, 938, 136 USPQ 458, 459 (CCPA 1963). MPEP 2111.02. Since Tang discloses a substantially identical structure of Claim 1, the recitation “a semiconductor memory device” is treated as the purpose or intended use of the claimed invention.
Liao is silent with respect to the first gate insulation film includes an upper face portion that extends along an upper face of the first active region, a side face portion (39b) that extends along a side face of the first active region, and a corner portion at a boundary between the upper face portion and the side face portion”.
FIG. 4 of Tang discloses a similar semiconductor memory device, wherein the first gate insulation film (132) includes an upper face portion that extends along an upper face of the first active region, a side face portion that extends along a side face of the first active region, and a corner portion at a boundary between the upper face portion and the side face portion.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Liao, as taught by Tang. The ordinary artisan would have been motivated to modify Liao in the above manner for purpose of improving the device performance (Abstract of Tang).
Claims 1 and 7 rejected under 35 U.S.C. 103 as being unpatentable over Chen (U.S. Patent Pub. No. 2010/0230757), in view of Roy (U.S. Patent Pub. No. 2015/0214062) of record.
Regarding Claim 1
FIG. 14 of Chen discloses a semiconductor memory device comprising: a semiconductor region including a first active region for a first memory transistor (59) and a plurality of depressions for trench isolation (32, FIG. 6); a plurality of insulating regions (36) respectively provided at the depressions of the semiconductor region; a first gate electrode (58) that extends in a first direction from one to another of, among the plurality of insulating regions, a first insulating region (left) and a second insulating region (right) that are next to one another, the first gate electrode passing over the first active region; and a first gate insulation film (56) provided between the first gate electrode and the first active region, wherein: the first active region of the semiconductor region is provided between the first insulating region and the second insulating region; one of the first insulating region or the second insulating region includes an adjacent region and a distant region each located under the first gate electrode, wherein a thickness of the distant region is greater than a thickness of the adjacent region; the adjacent region is adjacent to the first active region under the first gate electrode; the distant region is adjacent to the adjacent region under the first gate electrode; the adjacent region is provided between the distant region and the first active region; the first gate insulation film includes an upper face portion that extends along an upper face of the first active region, a side face portion that extends along a side face of the first active region, and a corner portion at a boundary between the upper face portion and the side face portion;.
Chen is silent with respect to “the semiconductor region includes a first conductive region and a second conductive region provided between the first insulating region and the second insulating region; and the first conductive region, the first active region and the second conductive region are arrayed in a second direction crossing the first direction”.
FIG. 1 of Roy discloses a similar semiconductor memory device, wherein the semiconductor region includes a first conductive region (S) and a second conductive region (D) provided between the first insulating region (110) and the second insulating region; and the first conductive region, the first active region and the second conductive region are arrayed in a second direction crossing the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Chen, as taught by Roy. The ordinary artisan would have been motivated to modify Chen in the above manner for purpose of reducing the size of overall cell array ([0003] of Roy).
Regarding Claim 7
FIG. 1 of Roy discloses the adjacent region is one of: a structure that traverses the first gate electrode in a direction from one to the other of the first conductive region and the second conductive region, or a structure that extends from one of the first conductive region and the second conductive region and terminates directly under the first gate electrode.
Claims 1-6 rejected under 35 U.S.C. 103 as being unpatentable over Wang (U.S. Patent No. 10,431,308) of record, in view of Lee (U.S. Patent Pub. No. 2005/0051867).
Regarding Claim 1
FIG. 9 of Wang discloses a semiconductor memory device comprising: a semiconductor region including a first active region (912) for a first memory transistor and a plurality of depressions for trench isolation (930); a plurality of insulating regions respectively provided at the depressions of the semiconductor region; a first gate electrode (921) that extends in a first direction from one to another of, among the plurality of insulating regions, a first insulating region and a second insulating region that are next to one another, the first gate electrode passing over the first active region; and a first gate insulation film provided between the first gate electrode and the first active region, wherein: the first active region of the semiconductor region is provided between the first insulating region and the second insulating region; one of the first insulating region or the second insulating region includes an adjacent region and a distant region each located under the first gate electrode, wherein a thickness of the distant region is greater than a thickness of the adjacent region (FIG. 4); the adjacent region is adjacent to the first active region under the first gate electrode; the distant region is adjacent to the adjacent region under the first gate electrode; the adjacent region is provided between the distant region and the first active region; the semiconductor region includes a first conductive region (drain) and a second conductive region (source) provided between the first insulating region and the second insulating region; and the first conductive region, the first active region and the second conductive region are arrayed in a second direction crossing the first direction.
Wang is silent with respect to “the first gate insulation film includes an upper face portion that extends along an upper face of the first active region, a side face portion that extends along a side face of the first active region, and a corner portion at a boundary between the upper face portion and the side face portion”.
FIG. 2 of Lee discloses a similar semiconductor memory device, wherein: the first active region of the semiconductor region is provided between the first insulating region and the second insulating region; one of the first insulating region or the second insulating region includes an adjacent region and a distant region each located under the first gate electrode, wherein a thickness of the distant region is greater than a thickness of the adjacent region wherein the first gate insulation film (212) includes an upper face portion that extends along an upper face of the first active region (204), a side face portion that extends along a side face of the first active region, and a corner portion at a boundary between the upper face portion and the side face portion, the first gate electrode passing over the first active region; and wherein a thickness of the distant region is greater than a thickness of the adjacent region, each located under the first gate electrode.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Wang, as taught by Lee. The ordinary artisan would have been motivated to modify Wang in the above manner for purpose of improving transistor power consumption ([0006] of Lee).
Regarding Claim 2
FIG. 9 of Wang discloses the semiconductor region further includes a second active region for a second memory transistor that is provided between the first insulating region and the second insulating region; the semiconductor memory device further includes: a second gate electrode that extends in the first direction above the second active region and passes over the second active region, and a second gate insulation film provided between the second gate electrode and the second active region; the semiconductor region further includes a third conductive region provided between the first insulating region and the second insulating region; conductivity types of the first conductive region, the second conductive region and the third conductive region are different from a conductivity type of the first active region; the second conductive region, the first active region, the first conductive region, the second active region and the third conductive region are arrayed in this order in the second direction; the second conductive region and the third conductive region are connected to a reference potential line (B); and the first conductive region is shared by the first memory transistor and the second memory transistor and is connected to a metal wiring layer (W).
Regarding Claim 3
FIG. 4 of Wang discloses the thickness of the adjacent region of the first insulating region is smaller than the thickness of the distant region, and the second insulating region under the first gate electrode is thicker than the adjacent region of the first insulating region.
Regarding Claim 4
FIG. 4 of Wang discloses in the first insulating region and the second insulating region, the adjacent region is provided so as to sandwich the second active region, and the distant region is provided so as to sandwich the adjacent region and the second active region, and wherein, at both sides of the second insulating region, the thickness of the adjacent region is smaller than the thickness of the distant region.
Regarding Claim 5
FIG. 9 of Wang discloses the insulating regions include a third insulating region neighboring the second insulating region; the first insulating region, the second insulating region and the third insulating region are arrayed in this order in the first direction; the semiconductor region further includes a third active region for a third memory transistor; the first gate electrode extends in the first direction and passes over the third active region; the semiconductor memory device further includes a third gate insulation film provided between the first gate electrode and the third active region; the third insulating region includes an adjacent region and a distant region; the adjacent region of the third insulating region is adjacent to the first active region under the first gate electrode, the distant region of the third insulating region being adjacent to the adjacent region under the first gate electrode, and the adjacent region being provided between the distant region and the first active region; a thickness of the adjacent region of the third insulating region under the first gate electrode is smaller than a thickness of the distant region of the third insulating region; and the second insulating region under the first gate electrode is thicker than the adjacent region of the third insulating region. Mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See MPEP 2144.04
Regarding Claim 6
FIG. 9 of Wang discloses the insulating regions include a fourth insulating region neighboring the first insulating region; the semiconductor region further includes a fourth active region for a fourth memory transistor provided between the first insulating region and the fourth insulating region; the first gate electrode extends in the first direction and passes over the fourth active region; the semiconductor memory device further includes a fourth gate insulation film provided between the first gate electrode and the fourth active region; the first insulating region includes a further adjacent region that is adjacent to the fourth active region under the first gate electrode; the distant region of the first insulating region is provided under the first gate electrode between the adjacent region and the further adjacent region of the first insulating region; the further adjacent region is provided between the distant region and the fourth active region; and a thickness of the further adjacent region under the first gate electrode is smaller than a thickness of the distant region of the first insulating region. Mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See MPEP 2144.04
Claim 11 rejected under 35 U.S.C. 103 as being unpatentable over Harada (WO 2019048979) of record, in view of Wang, in view of Lee.
Regarding Claim 11
FIG. 9 of Harada discloses a semiconductor integrated circuit comprising a current source circuit (SOC) and a bias circuit (CS), wherein: the current source circuit includes at least one transistor (Tr51/Tr52); and the bias source is connected to the gate electrode and provides a voltage (OSP) to the gate electrode.
Harada is silent with respect to “the transistor including: a semiconductor region including a plurality of depressions for trench isolation, a plurality of insulating regions respectively provided at the depressions of the semiconductor region, the plurality of insulating regions including a first insulating region and a second insulating region that neighbor one another, an active region for the transistor that is provided between the first insulating region and the second insulating region, a gate electrode that extends in a first direction from one to another of the first insulating region and the second insulating region, the gate electrode passing over the active region, and a gate insulation film provided between the gate electrode and the active region; one of the first insulating region or the second insulating region includes an adjacent region and a distant region each located under the gate electrode, wherein a thickness of the distant region is greater than a thickness of the adjacent region; the adjacent region is adjacent to the active region under the gate electrode; the adjacent region is adjacent to the distant region under the gate electrode; the adjacent region is provided between the distant region and the active region under the gate electrode; the gate insulation film includes an upper face portion that extends along an upper face of the active region, a side face portion that extends along a side face of the active region, and a corner portion at a boundary between the upper face portion and the side face portion; the semiconductor region includes a first conductive region provided between the first insulating region and the second insulating region, and a second conductive region provided between the first insulating region and the second insulating region; the first conductive region, the active region and the second conductive region are arrayed in a second direction crossing the first direction; and the bias source is connected to the gate electrode and provides a voltage to the gate electrode”.
FIG. 9 of Wang discloses a similar semiconductor integrated circuit, comprising: a semiconductor region including a first active region (912) for a first memory transistor and a plurality of depressions for trench isolation (930); a plurality of insulating regions respectively provided at the depressions of the semiconductor region; a first gate electrode (921) that extends in a first direction from one to another of, among the plurality of insulating regions, a first insulating region and a second insulating region that are next to one another, the first gate electrode passing over the first active region; and a first gate insulation film provided between the first gate electrode and the first active region, wherein: the first active region of the semiconductor region is provided between the first insulating region and the second insulating region; one of the first insulating region or the second insulating region includes an adjacent region and a distant region each located under the first gate electrode, wherein a thickness of the distant region is greater than a thickness of the adjacent region (FIG. 4); the adjacent region is adjacent to the first active region under the first gate electrode; the distant region is adjacent to the adjacent region under the first gate electrode; the adjacent region is provided between the distant region and the first active region; the semiconductor region includes a first conductive region (drain) and a second conductive region (source) provided between the first insulating region and the second insulating region; and the first conductive region, the first active region and the second conductive region are arrayed in a second direction crossing the first direction, wherein the active region and the second conductive region are arrayed in a second direction crossing the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Harada, as taught by Wang. The ordinary artisan would have been motivated to modify Harada in the above manner for purpose of forming a memory array (Col. 1, Lines 9-15 of Wang).
Harada as modified by Wang is silent with respect to “the gate insulation film includes an upper face portion that extends along an upper face of the active region, a side face portion that extends along a side face of the active region, and a corner portion at a boundary between the upper face portion and the side face portion”.
FIG. 2 of Lee discloses a similar semiconductor memory device, wherein: the first active region of the semiconductor region is provided between the first insulating region and the second insulating region; one of the first insulating region or the second insulating region includes an adjacent region and a distant region each located under the first gate electrode, wherein a thickness of the distant region is greater than a thickness of the adjacent region wherein the first gate insulation film (212) includes an upper face portion that extends along an upper face of the first active region (204), a side face portion that extends along a side face of the first active region, and a corner portion at a boundary between the upper face portion and the side face portion, the first gate electrode passing over the first active region; and wherein a thickness of the distant region is greater than a thickness of the adjacent region, each located under the first gate electrode.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Harada, as taught by Lee. The ordinary artisan would have been motivated to modify Harada in the above manner for purpose of improving transistor power consumption ([0006] of Lee).
Pertinent Art
Pertinent art includes CN 100589254, CN 101060136, Hung (KR 20130035835). Koyama (U.S. Patent Pub. No. 2015/0263175) discloses the first gate insulation film (405) includes an upper face portion that extends along an upper face of the first active region, a side face portion that extends along a side face of the first active region, and a corner portion at a boundary between the upper face portion and the side face portion.
Response to Arguments
Applicant’s arguments with respect to Claims 1 and 11 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897