DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Response to Amendment
The amendment filed February 20, 2026 has been entered. Claims 1-5, 8, 10-15, 17-18, and 21-23 remain pending in this application. Claims 6-7, 9, 16, and 19-20 have been previously cancelled at applicant’s request. Claims 1-2 and 14-15 have been amended. No claims have been added. No new matter has been added.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 5, 8, 10-15, 17-18, and 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 11,329,836 B1 to Toshiaki Kirihata, et al. (hereafter Kirihata) in view of US 2016/0148664 A1 to to Yoshikazu Katoh, et al. (hereafter Katoh) and further in view of Barker, Elaine, et al.: NIST SP 800-90C (2nd Draft) Recommendation for Random Bit Generator (RBG) Constructions, April 2016. Also referenced is Turan, Meltam, et al.: NIST SP 800-90B, Recommendation for the Entropy Sources Used for Random Bit Generation, January 2018 (Hereafter Turan). Although Turan will be referenced separately for clarity, it is incorporated in its entirety into Barker (Barker, §1 Lines 267-69) and will therefore otherwise be treated as a single source.
Regarding Amended Independent Claim 1, Kirihata discloses a method comprising:
allocating a number of native memory cells (Allocating a set of memory cells: Kirihata, col.2:4-5) in a memory device (A memory device: Kirihata, Figure 1), wherein
the number of native memory cells have not been programmed or written to since fabrication (The memory cells retain different Vt due to variations in manufacturing, suggesting they have not been programmed or written to: Kirihata, col.3:65-4:3);
obtaining a binary entropy string (Generating a physically unclonable function: Kirihata, col.4:62-64)
comprising a first plurality of binary bits using variations of native threshold voltages (VT) of the number of native memory cells as a first entropy source (Using the initial value of digital data at power-on to generate a digital ID: Kirihata, col.4:21-34), further including:
reading the number of native cells to generate the first plurality of binary bits (Reading the memory cells to generate the digital ID data: Kirihata, col.4:21-34), wherein the native VT of the number of native cells are not altered before reading (Disclosing that no user data is written to the plurality of non-volatile memory cells before reading: Kirihata, col.3:65-4:3); and
mathematically manipulating the binary entropy string
to generate a Unique Digital Signature (UDS) for the memory device (For creating a Physically Unclonable Function: Kirihata, col.4:62-64)).
Kirihata does not explicitly disclose a preliminary step of determining a UDS array voltage located at a median for a distribution of VT for the number of native memory cells. Katoh, however, discloses determining a UDS array voltage (VgUDS) located at a median for a distribution of VT for the number of native memory cells (Determining a median value for the unprogrammed memory cells: Katoh, ¶[0215]). Katoh teaches that determining a median threshold voltage and comparing that median voltage to a random distribution of threshold voltages can be used to create a unique and random digital ID for each non-volatile memory device (Katoh, ¶[0175]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the median voltage threshold of Katoh with the charge gate PUF generation method of Kirihata, with a reasonable expectation of success. Both inventions are well known in the field of generating unique and random digital IDs and the combination of known inventions with predictable results is obvious and not patentable.
Kirihata does not disclose mathematically manipulating the binary entropy string using a Hash-based Message Authentication Code (HMAC) technique. Barker, however, teaches mathematically manipulating the binary entropy string using a Hash-based Message Authentication Code (HMAC) technique (Teaching using a HMAC technique to condition entropy bits: Barker, §7.5.1).
Use of an additional HMAC conditioning technique reduces bias in the entropy-source output and distribute entropy across a bitstring, reduces the length of the bitstring and compresses the entropy into a smaller bitstring, and ensures the availability of full-entropy bits (Barker, §5.3.5). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the Hash-based Message Authentication Code of Barker with the charge gate PUF generation of Kirihata, with a reasonable expectation of success. Both inventions are well known in the field of PUF generation and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Claim 2, Katoh discloses the method of claim 1, wherein obtaining a binary entropy string comprises:
determining for each of the number of native memory cells whether it has a VT above the VgUDS (Comparing each of the memory cells to the reference voltage: Katoh, ¶[0084]); and
assigning each of the number of native memory cells having a VT above the VgUDS a first binary bit value, and each of the remaining number of native memory cells a second binary bit value (Separating the memory cells based on a reference threshold voltage: Katoh, ¶[0084]; Further assigning these cells one of two binary values: Katoh, ¶[0083]).
Regarding Claim 5, Katoh discloses the method of claim 2 wherein:
the first binary bit value is '0' and the second binary bit value is '1' (Selectively assigning one value from two values to each of a plurality of memory cells: Katoh, ¶[0083]), and
wherein obtaining the binary entropy string results in a string of binary digits approximately equal to the number of native memory cells (Each of the multiple memory cells translated into one of two binary values, resulting in a binary entropy string wherein the number of digits is approximately equal to the number of cells: Katoh, ¶[0084]), and
having random pattern of an approximately equal number of '1's and '0's (Using the median value of the plurality of Voltage Thresholds as the binarization reference value, thereby generating an approximately equal number of '1's and '0's: Katoh, ¶[0085]) .
Regarding Claim 8, Kirihata and Barker disclose the method of claim 1 further comprising
concatenating the binary entropy string (Teaching concatenating entropy bits from multiple entropy sources: Barker, §5.3.4)
with a binary number comprising a second plurality of binary bits obtained from a second entropy source (Teaching the concatenated string coming from a second entropy source: Barker, §7.5.2), and wherein
mathematically manipulating the binary entropy string using a HMAC technique to generate the UDS comprises mathematically manipulating a result of the concatenation using the HMAC technique to generate the UDS (Teaching using a HMAC technique to condition entropy bits: Barker, §7.5.1).
Regarding Claim 10, Kirihata and Barker disclose the method of claim 8 wherein:
a number of bits in the first plurality of binary bits is greater than a number of bits in the second plurality of binary bits (It is inherently required the number of bits generated by the claimed method exceeds the number of the second plurality of bits. If the second plurality of bits constituted the majority, the claimed method would cease to be the primary entropy source: Barker, §10.3.2.1; See also: Turan, §3.1.6, disclosing that additional vetted entropy sources used to supplement a primary entropy source will not be credited in evaluation testing.)
Regarding Claim 11, Kirihata and Barker disclose the method of claim 8 wherein:
the second entropy source comprises a True Random Number Generator (TRNG) in the memory device (Teaching using a Non-deterministic random bit generator, defined as a TRNG, as a second entropy source; Barker §6, Lines 627-35).
Regarding Claim 12, Kirihata discloses the method of claim 1 wherein
the number of native memory cells comprise a contiguous block of address space in the memory device (Disclosing the native memory cells comprising a contiguous block of space: Kirihata, Figure 2 and Kirihata, col.5:50-63).
Regarding Claim 13, Kirihata discloses the method of claim 1 wherein
the memory device is a non-volatile memory device (The memory cells described as NFETs: Kirihata, col.3:39-41).
Regarding Amended Independent Claim 14, Kirihata discloses a memory device comprising:
an array of memory cells (Allocating a set of memory cells: Kirihata, col.2:4-5)
including a number of native memory cells allocated as a first entropy source (Disclosing an array of memory cells, including a set of unmodified memory cells as a first entropy source: Kirihata, col.5:25-32),
wherein the native memory cells have not been programmed or written to since fabrication (The memory cells retain different Vt due to variations in manufacturing, suggesting they have not been programmed or written to: Kirihata, col.3:65-4:3) and
wherein each of the number of native memory cells includes a non-volatile memory (NVM) transistor having a charge-trapping gate stack (The memory cells being field effect transistors having charge trapping gates: Kirihata, col.5:29-30 and Kirihata, Figure 1); and
a microcontroller (A microcontroller: Kirihata, col.3:3)
operable to execute algorithms to:
determining a UDS array voltage (VgUDS) located at a median for a distribution of VT for the number of native memory cells (Determining a median value for the unprogrammed memory cells: Katoh, ¶[0215]);
obtain a binary entropy string comprising a first plurality of binary bits using variations of the NVM transistors (Obtaining a random string comprising binary bits using variations of Vt in NVM transistors: Kirihata, col.4:21-34) of the number of native memory cells (Disclosing that no user data is written to the plurality of non-volatile memory cells before reading: Kirihata, col.3:65-4:3); and
mathematically manipulate a result of the binary entropy string using a Hash- based Message Authentication Code (HMAC) technique to generate a unique digital signature (UDS) for the memory device (Teaching using a HMAC technique to condition entropy bits: Barker, §7.5.1).
Katoh teaches that by determining a median threshold voltage and comparing that median voltage to a random distribution of threshold voltages can be used to create a unique and random digital ID for each non-volatile memory device (Katoh, ¶[0175]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the median voltage threshold of Katoh with the charge gate PUF generation method of Kirihata, with a reasonable expectation of success. Both inventions are well known in the field of generating unique and random digital IDs and the combination of known inventions with predictable results is obvious and not patentable.
Use of an additional HMAC conditioning technique reduces bias in the entropy-source output and distribute entropy across a bitstring, reduces the length of the bitstring and compresses the entropy into a smaller bitstring, and ensures the availability of full-entropy bits (Barker, §5.3.5). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the Hash-based Message Authentication Code of Barker with the charge gate PUF generation of Kirihata, with a reasonable expectation of success. Both inventions are well known in the field of PUF generation and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Claim 15, Kirihata discloses the memory device of claim 14 wherein:
the algorithm to obtain the binary entropy string comprises steps including
reading the NVM transistors (Reading the memory cells to generate the digital ID data: Kirihata, col.4:21-34) of the number of native memory cells applied with the VgUDS versus a reference current (I0), and (Separating the memory cells based on current flow: Kirihata, col.4:27-30).
assigning each of the number of native memory cells having a resultant drain current (Id) less than I0 as having a VT above the VgUDS (Separating the remaining memory cells based on the current flow due to Vt: Kirihata, col.4:26-31) and
assigning the memory cell a first binary bit value, and each of the remaining number of native memory cells a second binary bit value (Disclosing assigning these cells one of two binary values: Kirihata, col.4:31-34).
Regarding Claim 17, Kirihata and Barker disclose the memory device of claim 14 further comprising
a second entropy source in the memory device,
wherein the microcontroller is further operable to execute an algorithm operable to concatenate the binary entropy string with a binary number comprising a second plurality of binary bits obtained from the second entropy source (Teaching concatenating entropy bits from multiple entropy sources; Barker, §5.3.4), and
wherein the algorithm to mathematically manipulate the binary entropy string using a HMAC technique is operable to mathematically manipulate a result of the concatenation using the HMAC technique to generate the UDS (Teaching using a HMAC technique to condition entropy bits: Barker, §7.5.1).
Barker recommends the use of a combination of multiple Random Bit Generator (RBG) sources: if the strength of one RBG is superior to another; if the RBGs are based on different principles, thereby increasing assurance; or the RBGs are from different implementers or different modules, in order to improve assurance (Barker, §11.1, Lines 1804-11).
Regarding Claim 18, Barker discloses the memory device of claim 17 wherein:
the second entropy source comprises a True Random Number Generator (TRNG) in the memory device (Teaching using a Non-deterministic random bit generator, defined as a TRNG, as a second entropy source; Barker §6, Lines 627-35).
Regarding Claim 21, Kirihata discloses the method of claim 1, but fails to disclose the further limitations of Claim 21. Katoh, however, discloses a method as in Claim 1, further comprising:
storing the UDS for the memory device in a secure storage location (Storing the UDS ; and
accessing the UDS for the memory device only from the secure storage location,
wherein the number of native cells are not read during the accessing the UDS (Disclosing the generating cells may be the same as or different from the key storage unit cells: Katoh, ¶[0341]).
Regarding Claim 22, Kirihata discloses the method of claim 1, wherein
the number of native cells each includes a non-volatile memory (NVM) transistor having a charge-trapping gate stack (The memory cells being field effect transistors having charge trapping gates: Kirihata, col.5:29-30 and Kirihata, Figure 1).
Regarding Claim 23, Kirihata discloses the memory device of claim 14 but fails to disclose the further limitations of Claim 23. Katoh, however, discloses a memory device as in Claim 14, wherein the microcontroller is further operable to execute algorithms to:
store the UDS for the memory device in a secure location (Generating the digital ID data and shifting it to a secure storage location: Katoh, ¶[0245]); and
access the UDS for the memory device only from the secure location,
wherein the number of native cells are not read during the access of the UDS (Disclosing the generating cells may be the same as or different from the key storage unit cells: Katoh, ¶[0341]).
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 11,329,836 B1 to Toshiaki Kirihata, et al. (hereafter Kirihata), US 2016/0148664 A1 to to Yoshikazu Katoh, et al. (hereafter Katoh), and Barker, Elaine, et al.: NIST SP 800-90C (2nd Draft) Recommendation for Random Bit Generator (RBG) Constructions, April 2016 in view of US 11,209,993 to Yuki Fujita, et al. (hereafter Fujita).
Regarding Claim 3, Katoh and Kirihata discloses the method of claim 2 but fails to disclose the new limitations of Claim 3. Fujita, however, teaches a method wherein determining the VgUDS comprises:
• applying to gates of the number of native memory cells an array voltage (Vg) equal to an initial voltage (Vinit) selected to produce in all of the number of native memory cells drain currents (Id) lower than a reference current (I0); increasing the array voltage (Vg) by a predetermined voltage (delta) and reading each of the number of native memory cells at an incremented array voltage (Vg+delta) by comparing a resulting drain current to the reference current (I0) (Teaching identifying the median voltage threshold by starting with an initial voltage, applying it to each of the circuits in an array, measuring the number of a first bit value, and modifying the test voltage to seek the median value: Fujita, 7:27-35);
• repeating increasing the array voltage (Vg) and reading each of the number of native memory cells until the incremented array voltage (Vg+delta) results in half of the number of native memory cells having drain currents (Id) higher than the reference current (I0) (Teaching calculating central threshold voltage by iteratively incrementing an initial test voltage until reaching approximate parity in bits: Fujita, 7:31-34; See Also Fujita, Figure 5C); and
• setting the VgUDS equal to last incremented array voltage (Vg+delta) (Teaching recording the final step of the iteration as the central threshold voltage: Fujita, 7:34-35).
Fujita teaches determining this median threshold voltage on a set of previously programmed memory cells. By precisely locating the median threshold value, even when applied to prior programmed cells, the natural random variation between cells is unpredictable, uncontrollable, and unique to specific physical factors, allowing for the generation of a secure PUF (Fujita, 5:6-16).
It would have been obvious to one of ordinary skill in the art, before the effective date of this application, that using this method of identification of a precise median threshold voltage, when applied to unprogrammed native memory cells of Katoh, would provide the same benefit of allowing for the generation of a secure PUF by taking advantage of the natural random variation between cells, which is unpredictable, uncontrollable, and unique to specific physical factors.
Katoh and Fujita are related to non-volatile memory cells, particularly reading native unmodified circuits and using those reads to generate a secure PUF. Therefore, it would have been obvious to one having reasonable knowledge of the art, prior to the effective filing date of this application, to combine the median threshold identification method of Fujita with the PUF generation method of Katoh in order to effectively and reliably generate a secure PUF by making use of the natural random variation between cells, which is unpredictable, uncontrollable, and unique to specific physical factors.
Regarding Claim 4, Katoh discloses the method of claim 3 wherein determining for each of the number of native memory cells whether it has a VT above the VgUDS comprises:
applying to gates of the number of native memory cells an array voltage (Vg) equal to the VgUDS (Applying an electric pulse of predetermined voltage to a variable memory element: Katoh, ¶[0078])
reading the number of native memory cells with the VgUDS applied to gates thereof by
comparing the drain current of each of the number of native memory cells to the reference current (I0) (Comparing the resistance value of a variable memory element when compared to an established reference resistance: Katoh, ¶[0078]; In a non-volatile memory cell, there is an inherent relationship between reading the current between cell source and drain and measuring the resistance between the same points. A low or non-existent current flow is equivalent to having a high resistance for an equivalent voltage difference across the points, as given by the equation Voltage Difference (V) = Current (I) * Resistance (R). Using this equation, it can be seen that the inverse scenario, wherein a high current reading is inherently equivalent to a low resistance, also holds true.); and
identifying each of the number of native memory cells having drain currents less than the reference current (I0) as having a VT above the VgUDS (Identifying each of the memory cells as having a voltage threshold above the predetermined test voltage: Katoh, ¶[0078]).
Response to Arguments
Applicant's arguments filed February 20, 2026 have been fully considered but they are not persuasive.
Regarding Claim 1 and the substantially similar arguments regarding Claim 14, Applicant argues Kirihata fails to disclose determining a VgUDS located at a median for a distribution of VT for the number of native memory cells and instead generates a PUF string one bit at a time by direct comparison of two cells to each other (Applicant’s Remarks, p.10 ¶2). This is a piecemeal analysis of the prior art. While Kirihata is concerned with the generation of a PUF string, doing so by generation and comparison to a median threshold voltage is taught in Katoh. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant further attempts to differentiate Katoh from the present invention, arguing the present invention determines the PUF from native (unmodified) memory cells while Katoh derives the PUF from cells that have been twice modified, once when the cells are subject to a forming stress and second when the cells are read (Applicant’s Remark, p.11 ¶1- p.12 ¶1). This is an improperly narrow reading of the text.
As for the forming stress, there is no reason to treat the forming stress as anything other than a step in the manufacturing process. It is not a step regularly performed by the end user or during standard operation of the device. It is a forming, i.e. a manufacturing, step, intended to initialize the memory cells to a state where the resistance value of the cells may be meaningfully read (Katoh, ¶[0116]). Any memory device will be subject to any manner of stresses during the manufacture process. Applicant’s specification describes these inherent stresses as “variations in production processes of the memory array that cause minor variations in physical and electrical characteristics of devices in the memory cells.” (Specification, ¶[0028]).
Similarly, suggesting that reading the designated cells constitutes a modification is unrealistically narrow. Comparison of the threshold voltage of a memory cell to a reference voltage is the very definition of reading and required in the process described, both in Katoh and the present invention. ”Briefly, a non-volatile memory array is characterized or sensed by applying a fixed voltage on the word lines connecting to the memory/control gates of each row of memory cells; and measuring the output current or drain current of each non- volatile memory cell.” (Specification, ¶[0039]). If ‘applying a fixed voltage to a memory cell and measuring the output current’ suffices as a read for Katoh, it must also suffice for the present invention. If not, not. In either case, Katoh must necessarily be interpreted to the same scope as the present invention.
Examiner agrees that ‘increasing the speed of generating the digital ID and increasing the resistance to side channel attacks,’ is insufficient motivation to combine the median Voltage threshold of Katoh with the overall PUF architecture of Kirihata. However, Katoh also teaches that determining a median threshold voltage and comparing that median voltage to a random distribution of threshold voltages can be used to create a unique and random digital ID for each non-volatile memory device (Katoh, ¶[0175]).
Therefore, Applicant’s arguments have been carefully considered but are not persuasive. Applicant's response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 4,531,203 to Fujio Masuoka: Description of an Electrically Erasable Non-Volatile Memory Cell, including limitations and reading therefrom.
US 9,666,292 to Kyung-Run Kim: Describing identifying a median voltage threshold of a system.
Rosulek, Mike: (January 3, 2021). "Chapter 11: Hash Functions" (PDF). The Joy of Cryptography. pp. 204–205: Describing scenarios such as simulating a SALT function by concatenating inputs from multiple RNGs.
H. Krawczyk; M. Bellare; R. Canetti: (February 1997). HMAC: Keyed-Hashing for Message Authentication. Network Working Group. doi:10.17487/RFC2104. RFC 2104. Informational. Updated by RFC 6151: Describing applying a Hash-based Message Authentication Code (HMAC) during an encryption step.
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/CHRISTOPHER LANE REECE/ Examiner, Art Unit 2824
/JEROME LEBOEUF/ Primary Examiner, Art Unit 2824 - 03/06/2026