DETAILED ACTION
This correspondence is in response to the communications received 01/06/2026. Claims 3 and 11 have been amended. Claims 1-13 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment to claim 1 overcomes the objection outlined in the previous Office Action. The objection is withdrawn.
Response to Arguments
Applicant's arguments filed 01/06/2026 have been fully considered but they are not persuasive.
Applicant asserts that Lee et al. (US 8,629,538 B2, hereinafter “Lee”) in combination with Yoshida et al. (US 9,583,407 B2, hereinafter “Yoshida”), Betsuda et al. (US 8,232,709 B2, hereinafter “Betsuda”), Hable et al. (US 9,585,241 B2, hereinafter “Hable”), and Gowda et al. (US 10,186,477 B2, hereinafter “Gowda”) fails to disclose “wherein the patterned region is partially overlapped with the second conductive layer along a first direction where the ceramic board and the second conductive layer are arranged”.
However, as presented in the previous Office Action, Hable teaches a patterned region “second metal layer 106F” (col. 12, lines 29-30). As seen in Fig. 9 of Hable, 106F extends horizontally along most of the length of “ceramic carrier 102F” (col. 12, lines 27-28) beyond the left and right edges of “chip 702” (col. 12, line 25), therefore when combined with the system of Lee, 106F of Hable would at least partially overlap “first metal layer 123” (col. 4, lines 58-59) of Lee, which is a second conductive layer, along the vertical direction where “first substrate 110” (col. 4, line 20) and 123 of Lee are arranged. Thus, the rejection is maintained.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a ceramic substrate structure ("ceramic substrate structure 1"), comprising:
a ceramic board ("ceramic board 10") having a first surface ("top surface 110") and a second surface ("bottom surface 120") opposite to each other (as seen in Fig. 1, 110 and 120 are opposite to each other), wherein each of the first surface and the second surface is a single surface extending continuously (as seen in Fig. 1, 110 and 120 are each a single surface extending continuously);
a first conductive layer ("first conductive layer 20") mounted on the first surface of the ceramic board (as seen in Fig. 1, 20 is mounted on 110);
a second conductive layer ("second conductive layer 30") mounted on the first surface of the ceramic board (as seen in Fig. 1, 30 is mounted on 110), wherein the second conductive layer is adjacent to the first conductive layer (as seen in Fig. 1, 30 is adjacent to 20), and the first conductive layer and the second conductive layer have different thicknesses (as seen in Fig. 1, 20 and 30 have different thicknesses); and
a heat dissipation layer ("heat dissipation layer 40") mounted on the second surface of the ceramic board (as seen in Fig. 1, 40 is mounted on 120), wherein the heat dissipation layer comprises a first heat dissipation portion ("first heat dissipation portion 410") and a second heat dissipation portion ("second heat dissipation portion 420"), the first heat dissipation portion corresponds to the first conductive layer (as seen in Fig. 4, 410 corresponds to 20), the second heat dissipation portion corresponds to the second conductive layer (as seen in Fig. 4, 420 corresponds to 30), and the second heat dissipation portion has a patterned region ("patterned region 421");
wherein the patterned region is partially overlapped with the second conductive layer along a first direction where the ceramic board and the second conductive layer are arranged (see Fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-10, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 8,629,538 B2, hereinafter “Lee”) in view of Yoshida et al. (US 9,583,407 B2, hereinafter “Yoshida”) in view of Betsuda et al. (US 8,232,709 B2, hereinafter “Betsuda”) in view of Hable et al. (US 9,585,241 B2, hereinafter “Hable”) in view of Gowda et al. (US 10,186,477 B2, hereinafter “Gowda”).
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Regarding claim 1, Fig. 1 of Lee discloses a ceramic substrate structure (together “first substrate 110”, col. 4, line 20, “second metal layer 121”, col. 4, lines 64-65, and “first metal layer 123”, col. 4, lines 58-59, form a ceramic substrate structure as “first substrate 110 may be a ceramic substrate”, col. 4, lines 20-21), comprising:
a ceramic board (as discussed above, 110 is a ceramic substrate) having a first surface and a second surface opposite to each other (“110 may have one surface and the other surface. One surface means an ‘upper [surface]’, and the other surface means a ‘lower surface’, based on FIG. 1”, col. 4, lines 14-16, the upper and lower surfaces are first and second surfaces respectively, and as seen in Fig. 1, the upper surface and the lower surface of 110 are opposite to each other), wherein each of the first surface and the second surface is a single surface extending continuously (as seen in Fig. 1, the upper surface and the lower surface of 110 are each a single surface extending continuously);
a first conductive layer (“second metal layer 121”, col. 4, lines 64-65) mounted on the first surface of the ceramic board (as seen in Fig. 1, 121 is mounted on the top surface of 110);
a second conductive layer (“first metal layer 123”, col. 4, lines 58-59) mounted on the first surface of the ceramic board (as seen in Fig. 1, 123 is mounted on the top surface of 110), wherein the second conductive layer is adjacent to the first conductive layer (as seen in Fig. 1, 123 is adjacent to 121).
Lee fails to disclose “the first conductive layer and the second conductive layer have different thicknesses; and
a heat dissipation layer mounted on the second surface of the ceramic board, wherein the heat dissipation layer comprises a first heat dissipation portion and a second heat dissipation portion, the first heat dissipation portion corresponds to the first conductive layer, the second heat dissipation portion corresponds to the second conductive layer, and the second heat dissipation portion has a patterned region;
wherein the patterned region is partially overlapped with the second conductive layer along a first direction where the ceramic board and the second conductive layer are arranged.”
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However, in a similar field of endeavor, Fig. 2 of Yoshida teaches the first conductive layer (“circuit pattern 3 (third conductor layer)”, col. 3, line 33, 3 of Yoshida is equivalent to 121 of Lee) and the second conductive layer (“circuit pattern 2 (second conductor layer)”, col. 3, lines 32-33, 2 of Yoshida is equivalent to 123 of Lee) have different thicknesses (as seen in Fig. 2, 3 and 2 have different thicknesses, furthermore, “disposing the semiconductor chip 1 on the mounting region 3M thicker than the circuit pattern 2 allows an enhanced capability of heat radiation, and particularly a reduced transient thermal resistance, compared to a case where mounting region 3M is as thick as the circuit pattern 2”, col 5, lines 41-46. since “first semiconductor chips 161” of Lee “may include a silicon controlled rectifier (SCR), a power transistor, an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor (MOS) transistor, a power rectifier, a power regulator, an inverter, a converter, or a high power semiconductor chip or diode including a combination thereof, but is not particularly limited thereto”, Lee, col. 6, lines 56-62, after substitution, 161 of Lee which is a high power device would then benefit from the additional cooling capabilities of the larger 3 of Yoshida).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “the first conductive layer and the second conductive layer have different thicknesses” as taught by Yoshida in the system of Lee for the purpose of improving the heat dissipation capabilities of specific conductive layers.
Lee in combination with Yoshida fails to disclose “a heat dissipation layer mounted on the second surface of the ceramic board, wherein the heat dissipation layer comprises a first heat dissipation portion and a second heat dissipation portion, the first heat dissipation portion corresponds to the first conductive layer, the second heat dissipation portion corresponds to the second conductive layer, and the second heat dissipation portion has a patterned region;
wherein the patterned region is partially overlapped with the second conductive layer along a first direction where the ceramic board and the second conductive layer are arranged.”
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However, in a similar field of endeavor, Fig. 3B of Betsuda teaches a heat dissipation layer (“copper reverse metallic component 14”, col. 19, lines 28-29, “the heat generated by the semiconductor light-emitting elements 13 is efficiently radiated to the partition sheet 21a through the reverse metallic component 14”, col. 12, lines 25-27, 14 therefore dissipates heat generated by 13 to 21a) mounted on the second surface of the ceramic board (as seen in Fig. 3B, 14 is mounted on the “back surface 11B”, col. 14, line 48, of “ceramic insulating base 11”, col. 14, line 49 where 11 of Betsuda is equivalent to 110 of Lee), wherein the heat dissipation layer comprises a first heat dissipation portion and a second heat dissipation portion (“respective blocks 14a, 14b, 14c, which configure the reverse metallic component 14”, col. 14, lines 53-55, 14b is a first heat dissipation portion, 14a is a second heat dissipation portion), the first heat dissipation portion corresponds to the first conductive layer (as seen in Fig. 3B, 14b corresponds to “pad 12b”, col. 15, line 12, where 12b is a portion of “copper obverse metallic component 12”, col. 10, line 59, 12b of Betsuda is equivalent to 121 of Lee), the second heat dissipation portion corresponds to the second conductive layer (as seen in Fig. 3B, 14a corresponds to 12a, 12a of Betsuda is equivalent to 123 of Lee).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a heat dissipation layer mounted on the second surface of the ceramic board, wherein the heat dissipation layer comprises a first heat dissipation portion and a second heat dissipation portion, the first heat dissipation portion corresponds to the first conductive layer, the second heat dissipation portion corresponds to the second conductive layer” as taught by Betsuda in the system of Lee in combination with Yoshida for the purpose of isolating heat dissipation from each semiconductor device to improve cooling performance by mitigating thermal energy passing between devices.
Lee in combination with Yoshida and Betsuda fails to disclose “the second heat dissipation portion has a patterned region;
wherein the patterned region is partially overlapped with the second conductive layer along a first direction where the ceramic board and the second conductive layer are arranged.”
Gowda teaches the use of plural heat sinks in an electronic package. Further, Gowda teaches that some devices have higher power heat dissipation demands than other devices. For this reason, Gowda teaches that an enhanced heat sink is used to address the higher power heat dissipation needs. The Gowda reference is disclosed merely to teach this concept that plural heat sinks with different heat dissipating capacities can be used in an electronic package.
The enhancement, whether it be varied thickness (texture) or larger overall thickness are known to be used when a package has a high heat producing device, to remove excess heat so the device can maintain operational temperature, so as to not reduce service lifetime. At the same time, low heat producing devices only require a basic thinner heat sink to keep them at required temperatures.
Gowda does not teach the particular heat sink enhancement as claimed, but the following secondary reference does teach this feature.
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In a similar field of endeavor, Fig. 9 of Hable teaches the second heat dissipation portion (“second metal layer 106F”, col. 12, lines 29-30, where 106F of Hable is equivalent to 14a of Betsuda) has a patterned region (as seen in Fig. 9, 106F has a patterned region on the bottom surface comprising “a plurality of trenches (or recesses or slots) 108”, col. 6, lines 28-29, where “the plurality of trenches (or recesses, slots, and the like) 108 may be formed into the second side 122 of the second metal layer 106 by at least one of the group of trench forming methods, wherein the group of trench forming methods may include or consist of: etching (e.g. dry and wet etching), plasma etching, laser ablation, mechanical sawing, milling, and the like”, col. 6, lines 43-49, 106F and 108F are duplicates of 106 and 108, furthermore, forming trenches as a cooling structure provides “a power electronic substrate having an improved heat dissipation behavior. The improved heat dissipation may be achieved by forming into or over at least one of the metallized sides of the substrate a cooling structure. The cooling structure may be formed in order to achieve an increased surface on this side of the substrate for improving heat dissipation”, col. 3, lines 13-19, thus 106F of Hable could be substituted for 14a of Betsuda in order to further enhance the heat dissipation capability. Hable further teaches the “PinFin structure 110”, col. 6, line 33, as an example of potentially patterning geometries for a patterned region);
wherein the patterned region is partially overlapped with the second conductive layer along a first direction where the ceramic board and the second conductive layer are arranged (as seen in Fig. 9, 106F extends horizontally along most of the length of “ceramic carrier 102F”, col. 12, lines 27-28, beyond the left and right edges of “chip 702”, col. 12, line 25, therefore when combined with the system of Lee, 106F of Hable would at least partially overlap 123 of Lee along the vertical direction where 110 and 123 of Lee are arranged).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “the second heat dissipation portion has a patterned region;
wherein the patterned region is partially overlapped with the second conductive layer along a first direction where the ceramic board and the second conductive layer are arranged” as taught by Hable in the system of Lee in combination with Yoshida and Betsuda for the purpose of providing “a power electronic substrate having an improved heat dissipation behavior. The improved heat dissipation may be achieved by forming into or over at least one of the metallized sides of the substrate a cooling structure. The cooling structure may be formed in order to achieve an increased surface on this side of the substrate for improving heat dissipation” (col. 3, lines 13-19) where “semiconductor device 44 is a high power device” (Gowda, col. 10, lines 44-45) and thus requires “a heat sink, such as heat sink 66 is coupled to conducting slab 60 via a thermal interface layer 112 to provide additional heat transfer for semiconductor device 44” (Gowda, col. 10, lines 45-48).
Regarding claim 2, Fig. 1 of Lee in combination with Fig. 2 of Yoshida, Fig. 3B of Betsuda, Fig. 9 of Hable, and Gowda disclose the ceramic substrate structure according to claim 1, Fig. 2 of Yoshida further discloses wherein the first conductive layer has greater thickness than the second conductive layer (as seen in Fig. 2, and discussed previously, 3 has a greater thickness than 2).
Regarding claim 4, Fig. 1 of Lee in combination with Fig. 2 of Yoshida, Fig. 3B of Betsuda, Fig. 9 of Hable, and Gowda disclose the ceramic substrate structure according to claim 1, Fig. 9 of Hable further discloses wherein the patterned region is one or more blind holes, one or more trenches or one or more through holes (as seen in Fig. 9, 106F includes “trenches 108F”, col. 11, 49-50, further, “PinFin structure 110 may be formed over the second side 122 of the second metal 106”, col. 8, lines 6-7, where “each element of the PinFin structure 110 may have a footprint. The footprint may be at least one of the group of geometrical footprint shapes, wherein the group of geometrical footprint shapes may include or consist of: a circle, a square, a rectangle, a rhombus, a trapezoidal, a parallelogram, a triangle, an ellipse, a pentagon, a hexagon, a heptagon, an octagon, a nonagon, a polygon, and the like”, col. 8, lines 25-31).
Regarding claim 5, Fig. 1 of Lee in combination with Fig. 2 of Yoshida, Fig. 3B of Betsuda, Fig. 9 of Hable, and Gowda disclose the ceramic substrate structure according to claim 1, Fig. 3B of Betsuda further discloses wherein the ceramic board and the second conductive layer are arranged along the first direction (as seen in Fig. 3B, 12a and 11 are arranged along the vertical direction which is a first direction) and the patterned region corresponds to the second conductive layer in the first direction (after substation of 106F of Hable for 14a of Betsuda, 12a of Betsuda corresponds to 106F of Hable in the vertical direction).
Regarding claim 6, Fig. 1 of Lee in combination with Fig. 2 of Yoshida, Fig. 3B of Betsuda, Fig. 9 of Hable, and Gowda disclose the ceramic substrate structure according to claim 1, Fig. 3B of Betsuda further discloses wherein a volume ratio of the second heat dissipation portion to the second conductive layer is from 0.5 to 2 (“The ratio of volume of the reverse metallic component to the obverse metallic component is preferably set close to 100% in a range of 50% to 120%”, col. 6, lines 44-46, where the reverse metallic component is 14a of Betsuda or 106F of Hable after substitution and the obverse metallic component is 12a of Betsuda, See MPEP 2131.03. "[W]hen, as by a recitation of ranges or otherwise, a claim covers several compositions, the claim is ‘anticipated’ if one of them is in the prior art." Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985) (citing In re Petering, 301 F.2d 676, 682, 133 USPQ 275, 280 (CCPA 1962)) (emphasis in original) (Claims to titanium (Ti) alloy with 0.6-0.9% nickel (Ni) and 0.2-0.4% molybdenum (Mo) were held anticipated by a graph in a Russian article on Ti-Mo-Ni alloys because the graph contained an actual data point corresponding to a Ti alloy containing 0.25% Mo and 0.75% Ni and this composition was within the claimed range of compositions.). "If the prior art discloses a point within the claimed range, the prior art anticipates the claim." UCB, Inc. v. Actavis Labs. UT, Inc., 65 F.4th 679, 687, 2023 USPQ2d 448 (Fed. Cir. 2023).).
Regarding claim 7, Fig. 1 of Lee in combination with Fig. 2 of Yoshida, Fig. 3B of Betsuda, Fig. 9 of Hable, and Gowda disclose the ceramic substrate structure according to claim 6, Fig. 3B of Betsuda further discloses wherein the volume ratio of the second heat dissipation portion to the second conductive layer is from 0.8 to 1.2 (as discussed above, the volume ratio of 106F of Hable to 12a of Betsuda is between 50% to 120% or 0.5 to 1.2. Paragraph [0023] of the instant application’s specification does not disclose any criticality to the claimed volume ratio. Betsuda teaches “A heat capacity difference between the obverse metallic component and the reverse metallic component caused by a volume is increased when the ratio of volume is less than 50%, thus it becomes difficult to prevent warping of the insulating base”, col. 6, lines 46-50. The entire range of 0.8 to 1.2 would perform the same function of preventing warping of the insulating base. Because there is no allegation of criticality and no evidence demonstrating a difference across the range, Betsuda discloses the claimed range with sufficient specificity. See MPEP section 2131.03.II. ClearValue Inc. v. Pearl River Polymers Inc., 668 F.3d 1340, 101 USPQ2d 1773 (Fed. Cir. 2012)).).
Regarding claim 8, Fig. 1 of Lee discloses a power module (“power module package 100”), comprising:
a ceramic substrate structure (together “first substrate 110”, col. 4, line 20, “second metal layer 121”, col. 4, lines 64-65, and “first metal layer 123”, col. 4, lines 58-59, form a ceramic substrate structure, as “first substrate 110 may be a ceramic substrate”, col. 4, lines 20-21), comprising:
a ceramic board (as discussed above, 110 is a ceramic substrate) having a first surface and a second surface opposite to each other (“110 may have one surface and the other surface. One surface means an ‘upper [surface]’, and the other surface means a ‘lower surface’, based on FIG. 1”, col. 4, lines 14-16, the upper and lower surfaces are first and second surfaces respectively, and as seen in Fig. 1, the upper surface and the lower surface of 110 are opposite to each other), wherein each of the first surface and the second surface is a single surface extending continuously (as seen in Fig. 1, the upper surface and the lower surface of 110 are each a single surface extending continuously); and
a first conductive layer (“second metal layer 121”, col. 4, lines 64-65) mounted on the first surface of the ceramic board (as seen in Fig. 1, 121 is mounted on the top surface of 110);
a second conductive layer (“second metal layer 121”, col. 4, lines 64-65) mounted on the first surface of the ceramic board (as seen in Fig. 1, 123 is mounted on the top surface of 110), wherein the second conductive layer is adjacent to the first conductive layer (as seen in Fig. 1, 123 is adjacent to 121).
a power semiconductor device (“first semiconductor chip 161 may include a silicon controlled rectifier (SCR), a power transistor, an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor (MOS) transistor, a power rectifier, a power regulator, an inverter, a converter, or a high power semiconductor chip or diode including a combination thereof, but is not particularly limited thereto.”, col. 5, lines 56-62) mounted on the first conductive layer (as seen in Fig. 1, 161 is on 121); and
a gate driver (“second semiconductor chip 163 may include a low power semiconductor chip for controlling the above-mentioned high power semiconductor chip, for example, a control device for controlling the driving of a power device.”, col. 5, lines 63-67, as 161 may include a transistor with a gate, control of the transistor would necessitate 163 driving the gate of the transistor) mounted on the second conductive layer (as seen in Fig. 1, 163 is on 123);
Lee fails to disclose “the first conductive layer and the second conductive layer have different thicknesses;
a heat dissipation layer mounted on the second surface of the ceramic board, wherein the heat dissipation layer comprises a first heat dissipation portion and a second heat dissipation portion, the first heat dissipation portion corresponds to the first conductive layer, the second heat dissipation portion corresponds to the second conductive layer, and the second heat dissipation portion has a patterned region;
wherein the patterned region is partially overlapped with the second conductive layer along a first direction where the ceramic board and the second conductive layer are arranged.”
However, in a similar field of endeavor, Fig. 2 of Yoshida teaches the first conductive layer (“circuit pattern 3 (third conductor layer)”, col. 3, line 33, 3 of Yoshida is equivalent to 121 of Lee) and the second conductive layer (“circuit pattern 2 (second conductor layer)”, col. 3, lines 32-33, 2 of Yoshida is equivalent to 123 of Lee) have different thicknesses (as seen in Fig. 2, 3 and 2 have different thicknesses, furthermore, “disposing the semiconductor chip 1 on the mounting region 3M thicker than the circuit pattern 2 allows an enhanced capability of heat radiation, and particularly a reduced transient thermal resistance, compared to a case where mounting region 3M is as thick as the circuit pattern 2”, col 5, lines 41-46. since “first semiconductor chips 161” of Lee “may include a silicon controlled rectifier (SCR), a power transistor, an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor (MOS) transistor, a power rectifier, a power regulator, an inverter, a converter, or a high power semiconductor chip or diode including a combination thereof, but is not particularly limited thereto”, Lee, col. 6, lines 56-62, after substitution, 161 of Lee which is a high power device would then benefit from the additional cooling capabilities of the larger 3 of Yoshida).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “the first conductive layer and the second conductive layer have different thicknesses” as taught by Yoshida in the system of Lee for the purpose of improving the heat dissipation capabilities of specific conductive layers.
Lee in combination with Yoshida fails to disclose “a heat dissipation layer mounted on the second surface of the ceramic board, wherein the heat dissipation layer comprises a first heat dissipation portion and a second heat dissipation portion, the first heat dissipation portion corresponds to the first conductive layer, the second heat dissipation portion corresponds to the second conductive layer, and the second heat dissipation portion has a patterned region;
wherein the patterned region is partially overlapped with the second conductive layer along a first direction where the ceramic board and the second conductive layer are arranged.”
However, in a similar field of endeavor, Fig. 3B of Betsuda teaches a heat dissipation layer (“copper reverse metallic component 14”, col. 19, lines 28-29, “the heat generated by the semiconductor light-emitting elements 13 is efficiently radiated to the partition sheet 21a through the reverse metallic component 14”, col. 12, lines 25-27, 14 therefore dissipates heat generated by 13 to 21a) mounted on the second surface of the ceramic board (as seen in Fig. 3B, 14 is mounted on the “back surface 11B”, col. 14, line 48, of “ceramic insulating base 11”, col. 14, line 49 ,where 11 of Betsuda is equivalent to 110 of Lee), wherein the heat dissipation layer comprises a first heat dissipation portion and a second heat dissipation portion (“respective blocks 14a, 14b, 14c, which configure the reverse metallic component 14”, col. 14, lines 53-55, 14b is a first heat dissipation portion, 14a is a second heat dissipation portion), the first heat dissipation portion corresponds to the first conductive layer (as seen in Fig. 3B, 14b corresponds to “pad 12b”, col. 15, line 12, where 12b isa portion of “copper obverse metallic component 12”, col. 10, line 59, 12b of Betsuda is equivalent to 121 of Lee), the second heat dissipation portion corresponds to the second conductive layer (as seen in Fig. 3B, 14a corresponds to 12a, 12a of Betsuda is equivalent to 123 of Lee).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a heat dissipation layer mounted on the second surface of the ceramic board, wherein the heat dissipation layer comprises a first heat dissipation portion and a second heat dissipation portion, the first heat dissipation portion corresponds to the first conductive layer, the second heat dissipation portion corresponds to the second conductive layer” as taught by Betsuda in the system of Lee in combination with Yoshida for the purpose of isolating heat dissipation from each semiconductor device to improve cooling performance by mitigating thermal energy passing between devices.
Lee in combination with Yoshida and Betsuda fails to disclose “the second heat dissipation portion has a patterned region;
wherein the patterned region is partially overlapped with the second conductive layer along a first direction where the ceramic board and the second conductive layer are arranged.”
Gowda teaches the use of plural heat sinks in an electronic package. Further, Gowda teaches that some devices have higher power heat dissipation demands than other devices. For this reason, Gowda teaches that an enhanced heat sink is used to address the higher power heat dissipation needs. The Gowda reference is disclosed merely to teach this concept that plural heat sinks with different heat dissipating capacities can be used in an electronic package.
The enhancement, whether it be varied thickness (texture) or larger overall thickness are known to be used when a package has a high heat producing device, to remove excess heat so the device can maintain operational temperature, so as to not reduce service lifetime. At the same time, low heat producing devices only require a basic thinner heat sink to keep them at required temperatures.
Gowda does not teach the particular heat sink enhancement as claimed, but the following secondary reference does teach this feature.
In a similar field of endeavor, Fig. 9 of Hable teaches the second heat dissipation portion (“second metal layer 106F”, col. 12, lines 29-30, 106F of Hable is equivalent to 14a of Betsuda) has a patterned region (as seen in Fig. 9, 106F has a patterned region on the bottom surface comprising “a plurality of trenches (or recesses or slots) 108”, col. 6, lines 28-29, where “the plurality of trenches (or recesses, slots, and the like) 108 may be formed into the second side 122 of the second metal layer 106 by at least one of the group of trench forming methods, wherein the group of trench forming methods may include or consist of: etching (e.g. dry and wet etching), plasma etching, laser ablation, mechanical sawing, milling, and the like”, col. 6, lines 43-49, 106F and 108F are duplicates of 106 and 108, furthermore, forming trenches as a cooling structure provides “a power electronic substrate having an improved heat dissipation behavior. The improved heat dissipation may be achieved by forming into or over at least one of the metallized sides of the substrate a cooling structure. The cooling structure may be formed in order to achieve an increased surface on this side of the substrate for improving heat dissipation”, col. 3, lines 13-19, thus 106F of Hable could be substituted for 14a of Betsuda in order to further enhance the heat dissipation capability. Hable further teaches the “PinFin structure 110”, col. 6, line 33, as an example of potentially patterning geometries for a patterned region).
wherein the patterned region is partially overlapped with the second conductive layer along a first direction where the ceramic board and the second conductive layer are arranged (as seen in Fig. 9, 106F extends horizontally along most of the length of “ceramic carrier 102F”, col. 12, lines 27-28, beyond the left and right edges of “chip 702”, col. 12, line 25, therefore when combined with the system of Lee, 106F of Hable would at least partially overlap 123 of Lee along the vertical direction where 110 and 123 of Lee are arranged).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “the second heat dissipation portion has a patterned region;
wherein the patterned region is partially overlapped with the second conductive layer along a first direction where the ceramic board and the second conductive layer are arranged” as taught by Hable in the system of Lee in combination with Yoshida and Betsuda for the purpose of providing “a power electronic substrate having an improved heat dissipation behavior. The improved heat dissipation may be achieved by forming into or over at least one of the metallized sides of the substrate a cooling structure. The cooling structure may be formed in order to achieve an increased surface on this side of the substrate for improving heat dissipation” (col. 3, lines 13-19) where “semiconductor device 44 is a high power device” (Gowda, col. 10, lines 44-45) and thus requires “a heat sink, such as heat sink 66 is coupled to conducting slab 60 via a thermal interface layer 112 to provide additional heat transfer for semiconductor device 44” (Gowda, col. 10, lines 45-48).
Regarding claim 9, Fig. 1 of Lee in combination with Fig. 2 of Yoshida, Fig. 3B of Betsuda, Fig. 9 of Hable, and Gowda disclose the power module according to claim 8, Fig. 2 of Lee further discloses wherein the ceramic board, the second conductive layer and the gate driver are arranged along the first direction (as seen in Fig. 1, 110, 123, and 163 are arranged along the vertical direction which is a first direction), and the patterned region corresponds to the gate driver in the first direction (after substitution of 14 of Betsuda into Lee, and substitution of 106F of Hable for 14a of Betsuda, 106F of Hable corresponds to 163 of Lee in the vertical direction as both would be aligned in the vertical direction on opposite sides of 110 of Lee).
Regarding claim 10, Fig. 1 of Lee in combination with Fig. 2 of Yoshida, Fig. 3B of Betsuda, Fig. 9 of Hable, and Gowda disclose the power module according to claim 8, Fig. 9 of Hable further discloses wherein the patterned region is one or more blind holes, one or more trenches or one or more through holes (as seen in Fig. 9, 106F includes “trenches 108F”, col. 11, 49-50, further, “the PinFin structure 110 may be formed over the second side 122 of the second metal 106”, col. 8, lines 6-7, where “each element of the PinFin structure 110 may have a footprint. The footprint may be at least one of the group of geometrical footprint shapes, wherein the group of geometrical footprint shapes may include or consist of: a circle, a square, a rectangle, a rhombus, a trapezoidal, a parallelogram, a triangle, an ellipse, a pentagon, a hexagon, a heptagon, an octagon, a nonagon, a polygon, and the like”, col. 8, lines 25-31).
Regarding claim 12, Fig. 1 of Lee in combination with Fig. 2 of Yoshida, Fig. 3B of Betsuda, Fig. 9 of Hable, and Gowda disclose the power module according to claim 8, Fig. 3B of Betsuda further discloses wherein a volume ratio of the second heat dissipation portion to the second conductive layer is from 0.5 to 2 (“The ratio of volume of the reverse metallic component to the obverse metallic component is preferably set close to 100% in a range of 50% to 120%”, col. 6, lines 44-46, where the reverse metallic component is 14a of Betsuda or 106F of Hable after substitution and the obverse metallic component is 12a of Betsuda, See MPEP 2131.03. "[W]hen, as by a recitation of ranges or otherwise, a claim covers several compositions, the claim is ‘anticipated’ if one of them is in the prior art." Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985) (citing In re Petering, 301 F.2d 676, 682, 133 USPQ 275, 280 (CCPA 1962)) (emphasis in original) (Claims to titanium (Ti) alloy with 0.6-0.9% nickel (Ni) and 0.2-0.4% molybdenum (Mo) were held anticipated by a graph in a Russian article on Ti-Mo-Ni alloys because the graph contained an actual data point corresponding to a Ti alloy containing 0.25% Mo and 0.75% Ni and this composition was within the claimed range of compositions.). "If the prior art discloses a point within the claimed range, the prior art anticipates the claim." UCB, Inc. v. Actavis Labs. UT, Inc., 65 F.4th 679, 687, 2023 USPQ2d 448 (Fed. Cir. 2023).).
Regarding claim 13, Fig. 1 of Lee in combination with Fig. 2 of Yoshida, Fig. 3B of Betsuda, Fig. 9 of Hable, and Gowda disclose the power module according to claim 12, Fig. 3B of Betsuda further discloses wherein the volume ratio of the second heat dissipation portion to the second conductive layer is from 0.8 to 1.2 (as discussed above, the volume ratio of 106F of Hable to 12a of Betsuda is between 50% to 120% or 0.5 to 1.2. Paragraph [0023] of the instant application’s specification does not disclose any criticality to the claimed volume ratio. Betsuda teaches “A heat capacity difference between the obverse metallic component and the reverse metallic component caused by a volume is increased when the ratio of volume is less than 50%, thus it becomes difficult to prevent warping of the insulating base”, col. 6, lines 46-50. The entire range of 0.8 to 1.2 would perform the same function of preventing warping of the insulating base. Because there is no allegation of criticality and no evidence demonstrating a difference across the range, Betsuda discloses the claimed range with sufficient specificity. See MPEP section 2131.03.II. ClearValue Inc. v. Pearl River Polymers Inc., 668 F.3d 1340, 101 USPQ2d 1773 (Fed. Cir. 2012)).).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893