DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/28/2026 was filed after the mailing date of the non-final rejection on 4/10/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Status
Previous action: claims 1, 3, 4, 6 through 11 and 13 rejected, 5 and 12 objected, 14 through 20 allowed
Present action: claims 1, 3, 4, 6 through 11 and 13 rejected, 5 and 12 objected, 14 through 20 allowed
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 6, 7, 8, 9, 10, 11, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 2021/0391315) in view of Mizutani (US 2021/0035965)
Regarding claim 1.
Zhang teaches:
A semiconductor device comprising:
a first substrate structure (fig 1b:102; [para 0039]) including a substrate (fig 1b:101; [para 0040]), circuit elements (fig 1b:108; [para 0040]) on the substrate (fig 1b:101; [para 0040]), and first bonding metal layers (fig 1b:111; [para 0043]) on the circuit elements (fig 1b:108; [para 0040]);
and a second substrate structure (fig 1b:104; [para 0039]) disposed directly on the first substrate structure (fig 1b:102; [para 0039]), the second substrate structure (fig 1b:104; [para 0039]) electrically connected to the first substrate structure (fig 1b:102; [para 0039]), wherein the second substrate structure (fig 1b:104; [para 0039]) includes: a plate layer (fig 1b:120,122; [para 0053]) comprising a conductive material ([para 0039]);
gate electrodes (fig 1b:116; [para 0047]) stacked below the plate layer (fig 1b:120,122,134; [para 0053]) and spaced apart from each other in a first direction (fig 1b:Y) that is perpendicular to a lower surface of the plate layer (fig 1b:120,122,134; [para 0053]);
channel structures (fig 1b:124; [para 0047]) passing through the gate electrodes (fig 1b:116; [para 0047]) and extending in the first direction (fig 1b:Y), each of the channel structures (fig 1b:124; [para 0047]) including a channel layer (fig 1b:128,125; [para 0064]);
separation regions (fig 1b:130; [para 0056]) extending in the first direction (fig 1b:Y) and a second direction (fig 1b:X) that is perpendicular to the first direction (fig 1b:Y), the separation regions (fig 1b:130; [para 0056]) penetrating through the gate electrodes (fig 1b:116; [para 0047]) ;
source contacts (fig 1b:132; [para 0053]) in the plate layer (fig 1b:120,122,134; [para 0053]) and disposed on the separation regions (fig 1b:130; [para 0056]), the source contacts (fig 1b:132; [para 0053]) extending in the second direction (fig 1b:X);
and second bonding metal layers (fig 1b:113; [para 0044]) below the channel structures (fig 1b:124; [para 0047]) and the gate electrodes (fig 1b:116; [para 0047]) and directly connected to the first bonding metal layers (fig 1b:111; [para 0043]), the plate layer (fig 1b:120,122,134; [para 0053]) is in direct contact with side surfaces of the source contacts (fig 1b:132; [para 0053]) and an upper end of the channel layer (fig 1b:128,125; [para 0064]) of each of the channel structures (fig 1b:124; [para 0047]), and is electrically connected to the source contacts (fig 1b:132; [para 0053]) and the channel layer (fig 1b:128,125; [para 0064]), and upper surfaces of the source contacts (fig 1b:132; [para 0053]) are coplanar with an upper surface of the plate layer (fig 1b:120,122,134; [para 0053]).
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Zhang does not teach a third direction perpendicular to a second and first direction.
Mizutani teaches:
separation regions (fig 4a,4b:72; [para 0074,0075]) extending in the first direction (fig 4a:72; [para 0074,0075]) and a second direction (fig 4b:72; [para 0074,0075]) that is perpendicular to the first direction, the separation regions (fig 4b,9:72; [para 0074,0102]) penetrating through the gate electrodes (fig 9:46; [para 0105]) and being spaced apart from each other in a third direction that is perpendicular to the first and second directions (fig 4a,4b,9)
t would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the memory structure including the separation regions to extend in first, second and third dimensions because it is a three dimensional object, further the separation regions serve to separate memory structures in all directions.
Regarding claim 3.
Zhang in view of Mizutani teaches the semiconductor device of claim 1, further
Zhang teaches:
the second substrate structure (fig 1b:104; [para 0049]) further includes a source interconnection layer (fig 1b:136; [para 0059]) on the source contacts (fig 1b:132; [para 0058]) and covering the upper surface of the plate layer (fig 1b:120,122,134; [para 0059]).
Regarding claim 6.
Zhang in view of Mizutani teaches the semiconductor device of claim 1, further
Zhang teaches:
the second substrate structure (fig 1b:104; [para 0039]) further includes at least one source interconnection layer (fig 1b:136; [para 0059]) having a line shape connected to end portions of the source contacts (fig 1b:132; [para 0058]) in the second direction, the at least one source interconnection layer (fig 1b:136; [para 0059]) extending .
Mizutani teaches:
a third direction (fig 4b) that is perpendicular to the first and second directions (fig 4b; [para 0075])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the interconnection layer would extend in the third direction because of the inherent property of thickness would require that the physical structure extends in all length and depth directions.
Regarding claim 7.
Zhang in view of Mizutani teaches the semiconductor device of claim 6, further
Zhang teaches:
the at least one source interconnection layer (fig 1b:136; [para 0059]) is positioned on a substantially same level as a level of the source contacts (fig 1b:132; [para 0058]).
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Regarding claim 8.
Zhang in view of Mizutani teaches the semiconductor device of claim 1, further
Zhang teaches:
the plate layer (fig 1b:120,122,123; [para 0054]) is a semiconductor layer including N-type impurities;
and the source contacts (fig 1b:132; [para 0054]) include a metallic material.
Regarding claim 9.
Zhang in view of Mizutani teaches the semiconductor device of claim 1, further
Zhang teaches:
the upper end of the channel layer (fig 1b:128,125; [para 0064]) includes an upper surface and an upper region of a side surface of the channel layer (fig 1b:128,125; [para 0064]) connected to the upper surface of the channel layer (fig 1b:128,125; [para 0064]), the upper end of the channel layer is surrounded by the plate layer (fig 1b:120,122,123; [para 0054]).
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Regarding claim 10.
Zhang in view of Mizutani teaches the semiconductor device of claim 1, further
Zhang teaches:
each of the channel structures (fig 1b:124; [para 0047]) includes a channel dielectric layer (fig 1b:126; [para 0050]), the channel layer (fig 1b:128,125; [para 0064]), and a channel filling layer ([para 0080]) sequentially stacked in a channel hole;
and the upper end of the channel layer (fig 1b:128,125; [para 0064]) is exposed by the channel dielectric layer (fig 1b:126; [para 0050]).
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Regarding claim 11.
Zhang in view of Mizutani teaches the semiconductor device of claim 1, further
Zhang teaches:
the plate layer (fig 1b:120,122,123; [para 0054]) has a thickness in a range of about 10 nm to about 150 nm (fig 1b; [para 0050]).
Given the teaching of the references, it would have been obvious to determine the optimum thickness of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) It is not inventive to discover optimum or workable ranges by routine experimentation. Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575,1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 13.
Zhang in view of Mizutani teaches the semiconductor device of claim 1, further
Zhang teaches:
lower surfaces of the source contacts (fig 1b:132; [para 0053]) are in the plate layer (fig 1b:120,122,123; [para 0054]).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 2021/0391315) in view of Mizutani (US 2021/0035965) as applied to claim 3 and further of Lee (US 2005/0127510).
Regarding claim 4.
Zhang in view of Mizutani teaches he semiconductor device of claim 3, above.
Zhang teaches:
the second substrate structure (fig 1b:104; [para 0039])
Zhang in view of Mizutani does not teach an anti-reflection layer
Lee teaches:
an anti-reflection layer (fig 1c:15’; [para 0005]) on the source interconnection layer (fig 1c:13’; [para 0005]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an anti-reflection layer in order to improve the resolution of the patterning process by reducing reflected light during photolithographic patterning.
Allowable Subject Matter
Claims 14 through 20 are allowed.
Claims 5 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 5, the prior art does not teach a semiconductor device comprising: a plate layer comprising a conductive material; gate electrodes stacked below the plate layer; channel structures passing through the gate electrodes; separation regions, source contacts in the plate layer and disposed on the separation regions, the source contacts extending in the second direction; and the plate layer is in direct contact with lateral-side surfaces of the source contacts and an upper end of the channel layer of each of the channel structures, and is electrically connected to the source contacts and the channel layer, and upper surfaces of the source contacts are coplanar with an upper surface of the plate layer,vias connecting the source contacts and the source interconnection layers in regions that the source contacts and the source interconnection layers intersect each other. in combination with other elements of the claim.
Regarding claim 12, the prior art does not teach a semiconductor device comprising: a plate layer comprising a conductive material; gate electrodes stacked below the plate layer; channel structures passing through the gate electrodes; separation regions, source contacts in the plate layer and disposed on the separation regions, the source contacts extending in the second direction; and the plate layer is in direct contact with lateral-side surfaces of the source contacts and an upper end of the channel layer of each of the channel structures, and is electrically connected to the source contacts and the channel layer, and upper surfaces of the source contacts are coplanar with an upper surface of the plate layer,the separation regions comprise an insulating material; and lower surfaces of the source contacts are in direct contact with the separation regions.in combination with other elements of the claim.
Regarding claim 14, the prior art does not teach a semiconductor device comprising: a plate layer; gate electrodes stacked below the plate layer; channel structures passing through the gate electrodes; separation regions extending in the first direction and a second direction that is perpendicular to the first direction, the separation regions penetrating through the gate electrodes and being spaced apart from each other in a third direction that is perpendicular to the first and second directions; source contacts in the plate layer and disposed on the separation regions, the source contacts extending in the second direction; and at least one source interconnection layer on upper surfaces or first side surfaces of the source contacts, the at least one source interconnection layer is electrically connected to the source contacts, and the source contacts have second side surfaces in direct contact with the plate layer, and lower surfaces of the source contacts are in direct contact with the separation regions in combination with other elements of the claim.
Regarding claim 19, the prior art does not teach a data storage system comprising: a plate layer; gate electrodes stacked below the plate layer; separation regions extending in the first direction and a second direction that is perpendicular to the first direction, the separation regions penetrating through the gate electrodes and being spaced apart from each other in a third direction that is perpendicular to the first and second directions; source contacts in the plate layer and disposed on the separation regions, the source contacts extending in the second direction; and at least one source interconnection layer on upper surfaces or first side surfaces of the source contacts, the at least one source interconnection layer being electrically connected to the source contacts, and the source contacts have second side surfaces in direct contact with the plate layer, and lower surfaces of the source contacts are in direct contact with the separation regions.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
The applicant argues that Zhang does not teach “upper surfaces of the source contacts are coplanar with an upper surface if the plate layer”, because the claim has been amended to recite “plate layer formed of a conductive material”.
The examiner disagrees. The claim recites “comprising” in line 1 which is inclusive or open-ended and does not exclude additional, unrecited elements. MPEP 211.03.I. Further, the specific claim element recites “made of”, however “[L]ike the term ‘comprising,’ the terms ‘containing’ and ‘mixture’ are open-ended.”. Invitrogen Corp. v. Biocrest Manufacturing, L.P., 327 F.3d 1364, 1368, 66 USPQ2d 1631, 1634 (Fed. Cir. 2003) “The transition ‘comprising’ in a method claim indicates that the claim is open-ended and allows for additional steps.” in the process of how the structure is “made”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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/D.J.G/Examiner, Art Unit 2817
/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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