DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 8-10, and 16-18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Uzoh (US 2024/0038702 A1).
As to claim 1, Uzoh discloses in Figs. 3A-3H a method for forming a semiconductor device, comprising: forming a stacked chip assembly (“stacked dies” 301/ 303) comprising a plurality of chips (“a plurality of bonded dies” 305) stacked and interconnected in a direction of a thickness thereof (Fig. 3A, para. [0033]-[0034]); providing a package wafer (“carrier” 307) (Fig. 3A, para. [0033]); bonding at least one of the stacked chip assembly (“stacked dies” 301/ 303) to a surface of the package wafer (“carrier” 307) by performing a chip-to-wafer bonding process (Fig. 3A, para. [0033]); obtaining a first reconstructed wafer (comprising “stacked dies” 301/303 and “first protective layer” 309, Fig. 3B) by performing a wafer reconstruction process through forming a first filling cap layer (“first protective layer” 309) over the surface of the package wafer (“carrier” 307) and a surface of each stacked chip assembly (“stacked dies” 301/ 303) on the package wafer (“carrier” 307) (Fig. 3B, para. [0034]), wherein the first reconstructed wafer (comprising “stacked dies” 301/303 and “first protective layer” 309) comprises one layer (one unit) of stacked chip assembly (“stacked dies” 301/ 303) stacked on the package wafer (“carrier” 307) (see Fig. 3B, para. [0034]); forming a bond structure (“bridging layer” 312, Fig. 3G) on a side (top side) of the first reconstructed wafer (comprising “stacked dies” 301/303 and “first protective layer” 309) away from the package wafer (“carrier” 307) (Fig. 3G, para. [0039]); and bonding at least one further layer (another unit) of stacked chip assembly (321/323) to a surface of the first reconstructed wafer (comprising “stacked dies” 301/303 and “first protective layer” 309) through the bond structure (“bridging layer” 312) (Fig. 3H, para. [0042]).
As to claim 2, as applied to claim 1 above, Uzoh discloses in Figs 3A-3H all claimed limitations including the method further comprising: repeating the chip-to-wafer bonding and the wafer reconstruction process over the first reconstructed wafer (comprising “stacked dies” 301/303 and “first protective layer” 309) to stack at least two layers (comprising two units/stacks of 301/303 & 321/323, Fig. 3H) of stacked chip assembly on the package wafer (“carrier” 307) (see Fig. 3H, para. [0042]).
As to claim 3, as applied to claim 1 above, Uzoh discloses in Figs 3A-3H all claimed limitations including the limitation: wherein the formation of the stacked chip assembly (“stacked dies” 301/ 303) comprises: forming a wafer stack (101/105, Figs. 1A-1B) by stacking and interconnecting a plurality of device wafers (each individual die in the stack, Figs. 1A-1B); and obtaining the stacked chip assembly (i.e., “stacked dies” 301/ 303, Fig. 3A) by dicing the wafer stack (101/105, Figs. 1A-1B) in a direction of a thickness thereof (Figs. 1A-2D and 3A, para. [0050], [0055]).
As to claim 4, as applied to claims 1 and 3 above, Uzoh discloses in Figs 3A-3H all claimed limitations including the limitation: wherein each device wafer (each individual die such as 207/219/227, Figs. 2A-2C) in the wafer stack (101/105, Figs. 1A-1B) has a front side, on which an electronic component (“die” 219, Fig. 2B) is formed (Figs. 2A-2D, para. [0027]), and a back side opposite to the front side, and wherein the front side of each device wafer (each individual die such as 207/219/227, Fig. 2A-2C) is oriented in a same direction (Figs. 1A-2C).
As to claim 5, as applied to claims 1, 3 and 4 above, Uzoh discloses in Figs 3A-3H all claimed limitations including the limitation: wherein the wafer stack (101/105, Figs. 1A-1B)/(209/211, Fig. 2D) comprises a first device wafer (“first die”, Fig. 2D), a second device wafer, …, and an n-th device wafer (“20th die”, Fig. 2D), which are stacked sequentially in a direction of a thickness thereof, where n is an integer equal to or greater than 2 (Fig. 2D), wherein each of the first, second, … , and n-th device wafers (“20th die”, Fig. 2D) comprises interconnect structures (“conductive contacts” 205, Fig. 2A) on the front side thereof and the bond structure (comprising “backside bonding layer” 225 and “conductive contacts” 205, Fig. 2B) connected to the interconnect structures on the front side (Figs. 2A-2D, para. [0027]-[0028]), wherein each of the second, and n-th device wafers (each individual from “second die” to “20th die”, Fig. 2D) further comprises interconnect structures (“conductive contacts” 205,Figs. 2A-2B) on the back side thereof and the bond structure (comprising “backside bonding layer” 225 and “conductive contacts” 205, Fig. 2B) connected to the interconnect structures (“conductive contacts” 205,Fig. 2A) on the back side (Figs. 2A-2D, para. [0027]), and wherein between adjacent device wafers (between each individual die, from first die to 20th die, Fig. 2D), the bond structure (“backside bonding layer” 225 and “conductive contacts” 205, Fig. 2B) on the front side of one of the adjacent device wafers (each individual die, from first die to 20th die, Fig. 2D) is bonded and electrically connected to the bond structure (“backside bonding layer” 225 and “conductive contacts” 205, Fig. 2B) on the back side of the other one of the adjacent device wafers (each individual die, from first die to 20th die, Fig. 2D) (see Fig. 2D, para. [0026]-[0027]).
As to claim 8, as applied to claims 1, 3, 4, and 5 above, Uzoh discloses in Figs 3A-3H all claimed limitations including the limitation: wherein bonding each stacked chip assembly (209/211, Fig. 2D)/(“stacked dies” 301/ 303, Fig. 3A) to the package wafer (201, Fig. 2D)/(“carrier” 307, Fig. 3A) is accomplished by bonding the bond structure (comprising “backside bonding layer” 225 and “conductive contacts” 205, Fig. 2B) on the front side of the n-th device wafer (each individual die, from first die to 20th die, Fig. 2D) to the package wafer (201, Fig. 2D)/(“carrier” 307, Fig. 3A) (see Figs. 2A-2D & 3A).
As to claim 9, as applied to claims 1, 3, 4, 5 and 8 above, Uzoh discloses in Figs 3A-3H all claimed limitations including the method further comprising: forming, in the back side of a part of the first device wafer (207, Fig. 2B) in the first reconstructed wafer, TSVs {“a plurality of through substrate vias (TSVs)”, para. [0026]-[0027]} connected to the interconnect structures (“conductive contacts” 205,Fig. 2A) on the front side (215) of the part of the first device wafer (207) (Figs. 2A-3H, para. [0026]-[0027]); and forming, on the back side (217) of the part of the first device wafer (207, Fig. 2B), the bond structure (comprising “backside bonding layer” 225 and “conductive contacts” 205, Fig. 2B) with a wafer-level dimension and connected to the TSVs {“a plurality of through substrate vias (TSVs)”, para. [0026]-[0027]}, in order to allow stacking of the other layer (321/323) of stacked chip assembly on the side of the first reconstructed wafer (comprising “stacked dies” 301/303 and “first protective layer” 309, Figs. 3B), 3H) away from the package wafer (307, Fig. 3H) by the chip-to-wafer bonding (Figs. 2A-3H) (Figs. 2A-3H, para. [0026]-[0027]).
As to claim 10, as applied to claim 1 above, Uzoh discloses in Figs 3A-3H all claimed limitations including the method further comprising, subsequent to the stacking of the at least one stacked chip assembly (“stacked dies” 301/303)/(321/323, Fig. 3H) on the package wafer (“carrier” 307, Fig. 3H), forming metal solder pads (117, Fig. 1A)/(205, Figs. 2A-2C) on a side of the package wafer (103, Fig. 1A)/(307, Fig. 3H) away from the stacked chip assembly (“stacked dies” 301/303)/(321/323, Fig. 3H) (Figs. 1A-3H, para. [0023], [0026]-[0027]).
As to claim 16, as applied to claim 1 above, Uzoh discloses in Figs 3A-3H all claimed limitations including the limitation: wherein each layer (each unit/stack 301/303 or 321/323) of stacked chip assembly comprises a plurality of stacked chip assemblies arranged at intervals along a direction (horizontal direction) perpendicular to the direction (vertical direction) of the thickness (see Fig. 3H).
As to claim 17, as applied to claim 1 and 16 above, Uzoh discloses in Figs 3A-3H all claimed limitations including the limitation: wherein the bond structure (comprising “backside bonding layer” 225 and “conductive contacts” 205, Fig. 2B) comprises a dielectric layer (225) and conductive elements (205) formed in the dielectric layer (225) (Fig. 2B, para. [0027]), wherein adjacent layers of stacked chip assembly are coupled by the conductive elements (205) (see Figs. 2B-2C), and wherein the dielectric layer (225) overlaps with each stacked chip assembly of the at least one layer of stacked chip assembly (see Figs. 2B-3H).
As to claim 18, as applied to claim 1 above, Uzoh discloses in Figs 3A-3H all claimed limitations including the limitation: wherein the filling cap layers (309) of adjacent layers of stacked chip assembly are disconnected (see Fig. 3C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh (US 2024/0038702 A1) in view of TAKAHASHI et al. (U.S 2010/0159643 A1).
As to claim 7, as applied to claims 1, 3, 4, and 5 above, Uzoh discloses in Figs 3A-3H all claimed limitations except for the limitation: wherein the first device wafer is thinned from the back side before the wafer stack is diced.
TAKAHASHI et al. disclose in Figs. 3B-3C a semiconductor device and a corresponding method comprising: the first device wafer (“thinned TSV wafer” 205/205’) is thinned from the back side (bottom side) before the wafer stack (comprising 202’ & 205/205’, Figs. 3B-3C) is diced (Figs. 3B-3C & 5C, para. [0022], [0026], [0031]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify Uzoh’s reference by having the first device wafer is thinned from the back side before the wafer stack is diced, as taught by TAKAHASHI et al., in order to reduce micro-cracks, chipping, and delamination (peeling apart) at the device wafer edges when the mechanical blade or laser cuts through the stack to separate the individual dies/chips.
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5, 7-10, and 16-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 September 16, 2026
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