DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election without traverse of Group I (claims 1-10) in the reply filed on 12/23/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, and 7-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. (U.S 2021/0305226 A1).
As to claim 1, Tsai et al. disclose in Fig. 2G a method for forming a semiconductor device, comprising: forming a stacked chip assembly (“die stack structure” 150’) comprising a plurality of chips (150a1-150d2) stacked and interconnected in a direction of a thickness thereof (Fig. 2G, para. [0039]-[0041], [0043]-[0051], [0055]-[0056], [0059], [0065]-[0082]), providing a package wafer (comprising 122, 115, 15, and 132’) (Fig. 2G, para. [0049]-[0053], [0055]-[0056], [0080], [0088], [0090]-[0091]); bonding at least one of the stacked chip assembly (“die stack structure” 150’) to a surface (top surface) of the package wafer (comprising 122, 115, 15, and 132’) by performing a chip-to-wafer bonding process (Fig. 2G, para. [0035]-[0036], [0039]-[0041], [0045], [0049]-[0051], [0076]); and obtaining a first reconstructed wafer (comprising 150’, 158, and 150a1-150d2) by performing a wafer reconstruction process through forming a first filling cap layer (“encapsulant” 158) over the surface (top surface) of the package wafer (comprising 122, 115, 15, and 132’) and a surface (i.e., side surface) of each stacked chip assembly (“die stack structure” 150’) on the package wafer (comprising 122, 115, 15, and 132’) (Fig. 2G, para. [0045], [0051], [0055]-[0056], [0059], [0078], [0080]-[0081]), wherein the first reconstructed wafer (comprising 150’, 158, and 150a1-150d2) comprises one layer (at least any one layer of the stack 150’) of stacked chip assembly (“die stack structure” 150’) stacked on the package wafer (comprising 122, 115, 15, and 132’) (Fig. 2G).
As to claim 2, as applied to claim 1 above, Tsai et al. disclose in Fig. 2G all claimed limitations including the method further comprising: repeating the chip-to-wafer bonding and the wafer reconstruction process over the first reconstructed wafer (comprising 150’, 158, and 150a1-150d2) to stack at least two layers (at least any two layers of stack 150’) of stacked chip assembly (150’) on the package wafer (comprising 122, 115, 15, and 132’) (Fig. 2G, para. [0045], [0051], [0055]-[0056], [0059], [0078], [0080]-[0081]).
As to claim 3, as applied to claim 1 above, Tsai et al. disclose in Fig. 2G all claimed limitations including the limitation: wherein the formation of the stacked chip assembly (150’) comprises: forming a wafer stack (comprising a stack of 150a1-150d2) by stacking and interconnecting a plurality of device wafers (150a1-150d2) (Fig. 2G, para. [0055], [0066]-[0068]); and obtaining the stacked chip assembly (150’) by dicing the wafer stack (a stack of 150a1-150d2) in a direction of a thickness thereof (Figs. 2G-2H, para. [0054], [0079]).
As to claim 4, as applied to claims 1 and 3 above, Tsai et al. disclose in Fig. 2G all claimed limitations including the limitation: wherein each device wafer (each of 150a1-150d2) in the wafer stack (a stack of 150a1-150d2) has a front side (bottom side/surface), on which an electronic component (150a1, 150a2)/(150b1, 150b2)/(150c1, 150c2)/(150d1, 150d2) is formed, and a back side (top side/surface) opposite to the front side (bottom side/surface), and wherein the front side (bottom side/surface) of each device wafer (each of 150a1-150d2) is oriented in a same direction (Fig. 2G, para. [0055], [0066]-[0068]).
As to claim 5, as applied to claims 1, 3 and 4 above, Tsai et al. disclose in Fig. 2G all claimed limitations including the limitation: wherein the wafer stack (comprising a stack of 150a1-150d2) comprises a first device wafer (150a1, 150a2), a second device wafer (150b1, 150b2), ..., and an n-th device wafer (150d1, 150d2), which are stacked sequentially in a direction of a thickness thereof (see Fig. 2G), where n is an integer equal to or greater than 2 (n is at least 2 because there are more than 2 device wafers 150a1, 150b1, 150c1…), wherein each of the first, second, ..., and n-th device wafers (150a1-150d2) comprises interconnect structures (see interconnect structures on 150a1-150d2) on the front side (bottom side/surface) thereof and a bond structure connected to the interconnect structures (see interconnect structures on 150a1-150d2) on the front side (bottom side/surface) (Fig. 2G), wherein each of the second, ..., and n-th device wafers (150a1-150d2) further comprises interconnect structures (see interconnect structures on 150a1-150d2) on the back side (top side/surface) thereof and a bond structure connected to the interconnect structures (see interconnect structures on 150a1-150d2) on the back side (top side/surface) (Fig. 2G), and wherein between adjacent device wafers (150a1-150d2), the bond structure on the front side (bottom side/surface) of one of the adjacent device wafers (150a1-150d2) is bonded and electrically connected to the bond structure on the back side (top side/surface) of the other one of the adjacent device wafers (150a1-150d2) (Fig. 2G, para. [0045]).
As to claim 7, as applied to claims 1, 3, 4 and 5 above, Tsai et al. disclose in Fig. 2G all claimed limitations including the limitation: wherein the first device wafer (150a1, 150a2) is thinned from the back side (top side/surface) before the wafer stack (stack of 150a1-150d2) is diced (Fig. 2G, para. [0078]).
As to claim 8, as applied to claims 1, 3, 4 and 5 above, Tsai et al. disclose in Fig. 2G all claimed limitations including the limitation: wherein bonding each stacked chip assembly (150’) to the package wafer (comprising 122, 115, 15, and 132’) is accomplished by bonding the bond structure on the front side (bottom side/surface) of the n-th device wafer (150d1, 150d2) to the package wafer (comprising 122, 115, 15, and 132’) (Fig. 2G, para. [0049], [0050]).
As to claim 9, as applied to claims 1, 3, 4, 5 and 8 above, Tsai et al. disclose in Fig. 2G all claimed limitations including the method further comprising: forming, in the back side (top side/surface) of a part of the first device wafer (150a1, 150a1) in the first reconstructed wafer (comprising 150’, 158, and 150a1-150d2), TSVs (as indicated at 153, para. [0066]) connected to the interconnect structures on the front side (bottom side/surface) of the part of the first device wafer (150a, 150a2, Fig. 2G); and forming, on the back side (top side/surface) of the part of the first device wafer (150a1, 150a2), a bond structure with a wafer-level dimension and connected to the TSVs (as indicated at 153), in order to allow stacking of the other layer of stacked chip assembly (150’) on a side of the first reconstructed wafer (comprising 150’, 158, and 150a1-150d2) away from the package wafer (comprising 122, 115, 15, and 132’) by the chip-to-wafer bonding (Fig. 2G).
As to claim 10, as applied to claim 1 above, Tsai et al. disclose in Fig. 2G all claimed limitations including the method further comprising, subsequent to the stacking of the at least one stacked chip assembly (150’) on the package wafer (comprising 122, 115, 15, and 132’) (Fig. 2G), forming metal solder pads (see bottom metal pads corresponding to “connectors” 160, Fig. 2G) on a side (bottom side) of the package wafer (comprising 122, 115, 15, and 132’) away from the stacked chip assembly (150’) (Fig. 2G, para. [0053], [0091]).
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Yu et al. (U.S 2021/0225809 A1), Chung et al. (U.S 2020/0411472 A1), JANG et al. (U.S 2023/0071812 A1), BAE et al. (U.S 2022/0415835 A1).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 April 4, 2026
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