DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/5/2026 has been entered.
Status of the Application
2. Acknowledgement is made of the amendment received on 2/11/2026. Claims 1-15, 18 & 20-27 are pending in this application. Claims 16-17 & 19 are canceled. Claims 14-15, 18 & 20 are withdrawn. Claims 26-27 are new.
Claims 1-13 & 21-27 are examined in this Office Action.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claims 1, 3, 4, 6, 26 and 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hieh et al. (US 2004/0124517).
Re claims 1 & 27, Hieh teaches, under BRI, Figs. 5-6, [0021-0022], a first semiconductor package, comprising:
-a first package substrate (system substrate 20);
-a semiconductor chip (die 27) disposed on the first package substrate (20); and
-a stiffener (stiffening member 11) disposed on the first package substrate (20), the stiffener (11) comprising
a structural inner portion (frame of 11) configured to surround the semiconductor chip (27), the structural inner portion (of 11) defining a space (aperture 17) on the first package substrate (20) external to the structural inner portion (of 11) and located between the structural inner portion (of 11) and outer peripheral edges (at pins 14, indicated) of the first package substrate (20), and
a plurality of leg portions (protrusions of 11) extending outwardly from the structural inner portion (of 11) to the outer peripheral edges of the first package substrate (35) and contacting the outer peripheral edges of the first package substrate (20);
- a component (carrier substrate 25) disposed in the space (17) between two of the plurality of leg portions (between pins 14, Fig. 6).
PNG
media_image1.png
235
540
media_image1.png
Greyscale
Re claim 3, Hsieh teaches the stiffener (11) is comprised of metal [0006].
Re claim 4, Hsieh teaches, Fig. 5, the plurality of leg portions (of 11) include diagonal leg portions extending from corners of the structural inner portion (of 11) to corners of the first package substrate (20).
Re claim 6, Hsieh taches, Fig. 5, the structural inner portion (of 11) is a rectangular.
Re claim 26, Hsieh teaches, Figs. 5-6, two of the plurality of leg portions (of 11) extend to at least one of the outer peripheral edges of the first package substrate (20) and from at least one of i) a same side of the structural inner portion, and ii) corners of the structural inner portion (frame of 11) adjacent a same side of the structure inner portion (Fig 5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-6, 10, 11, 22 and 25-27 are rejected under 35 U.S.C. 103 as being unpatentable over Heng et al. (US 2010/0276799) in view of Liao (US 2008/0038938).
Re claims 1 & 27, Heng teaches, under BRI, Figs. 5-7, [0034], a first semiconductor package, comprising:
-a first package substrate (35);
-a semiconductor chip (40) disposed on the first package substrate (35); and
-a stiffener (stiffener frame 90) disposed on the first package substrate (35), the stiffener (90) comprising
a structural inner portion (frame of 90) configured to surround the semiconductor chip (40), the structural inner portion (of 90) defining a space (outside 90) on the first package substrate (35) external to the structural inner portion (of 90) and located between the structural inner portion (of 90) and outer peripheral edges (sides of 35) of the first package substrate (35), and
a plurality of leg portions (left & right extensions 210) extending outwardly from the structural inner portion (of 90) to the outer peripheral edges of the first package substrate (35).
PNG
media_image2.png
444
515
media_image2.png
Greyscale
Heng does not explicitly teach the plurality of leg portions contacting the outer peripheral edges of the first package substrate; and a component disposed in the space between two of the plurality of leg portions.
Liao teaches, Figs. 1-3, [0015-0016], the plurality of leg portions (extending portions 21 of stiffener 2) contacting the outer peripheral edges of the first package substrate (50); and a component (502, 5021) disposed in the space between two of the plurality of leg portions (21).
As taught by Liao, one of ordinary skill in the art would utilize & modify the above teaching into Heng’s structure to obtain the plurality of leg portions contacting the outer peripheral edges of the first package substrate & a component as claimed, because it aids in avoiding damaging the contacts in the housing [0010]. Further, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) & it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Liao in combination with Heng due to above reason.
Re claims 2 & 3, Heng teaches, [0025, 0030], the first package substrate (35) is laminate substrate (e.g., multiple layers of metallization and dielectric materials) and the stiffener (90) is comprised of a material having a rigidity greater than the laminate structure, wherein the stiffener (35) is comprised of metal (e.g., copper).
Re claim 4, in combination cited above, Liao teaches, Fig. 1, the plurality of leg portions (21) include diagonal leg portions extending from corners of the structural inner portion to corners of the first package substrate (5).
Re claim 5, Heng teaches, Fig. 5, the plurality of leg portions include lateral leg portions (210) extending from sides of the structural inner portion (of 90) to the outer peripheral edges of the first package substrate (35).
Re claim 6, Heng teaches, Fig. 5, the structural inner portion (of 90) is rectangular.
Re claim 10, Heng teaches, Fig. 2, [0024], an electronic data communications device comprising a printed circuit board (PCB 10) and the semiconductor package of claim 1 (see claim 1 discussed above) mounted on the printed circuit board (10).
Re claim 11, Heng teaches, Fig. 2, [0031, 0034], the first semiconductor package includes an array of electrical contact terminals (120) and is surface mounted to the printed circuit board (10) to establish a plurality of electrical contacts via the array of electrical contact terminals (120).
Re claim 22, in combination cited above, Liao teaches, Fig. 3, a component (502, 5021), wherein: the plurality of leg portions (21) include (i) a first leg portion extending diagonally from a first corner of the structural inner portion (of 2), and (ii) a second leg portion (21) extending diagonally from a second corner of the structural inner portion (of 2), the first leg portion and the second leg portion (21) define the space on the first package substrate (50); and the component (502, 5021) is disposed in the space between the first leg portion and the second leg portion (21).
Re claim 25, Heng teaches, under BRI, Fig. 2, the structural inner portion (of 90) is a ring disposed inwardly of the outer peripheral edges of the first package substrate (35); and the plurality of leg portions (210) are connected (via 90) to each other at first ends of the plurality of leg portions by the structural inner portion (of 90) and are not connected to each other at second ends of the plurality of leg portions (210).
Re claim 26, in combination cited above, Liao teaches, Fig. 1, two of the plurality of leg portions (21) extend to at least one of the outer peripheral edges of the first package substrate (50) and from at least one of i) a same side of the structural inner portion, and ii) corners of the structural inner portion (frame of 2) adjacent a same side of the structure inner portion (Fig. 1).
5. Claims 9 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Heng as modified by Liao in view of Wu et al. (US 2023/0104301).
The teachings of Heng/Liao have been discussed above.
Re claim 9, Heng/Liao does not the first semiconductor package is a SerDes device.
Wu teaches the semiconductor package is a SerDes device [0002].
As taught by Wu, one of ordinary skill in the art would utilize & modify the above teaching to obtain the semiconductor package is a SerDes device as claimed, because it aids in achieving desired package that provides high speed communication.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Wu in combination with Heng/Liao due to above reason.
Re claim 24, in combination cited above, Wu teaches, Figs. 1 & 2B-C, [0023], the plurality of leg portions include (i) a first leg portion (225) extending laterally from a first side of the structural inner portion (of 130) (in horizontal), and (ii) a second leg portion (225) (in vertical) extending laterally from a second side of the structural inner portion perpendicular to the first leg portion (225).
6. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Heng as modified by Liao as applied to claim 1 above, in view of Loo et al. (US 2011/0018125).
The teachings of Heng/Liao have been discussed above.
Re claim 7, Heng/Liao does not teach a circuit component arranged on the first package substrate in the space defined between the structural inner portion and the outer peripheral edges of the first package substrate.
Loo teaches, Fig. 6, [0023, 0024], a circuit component (40) arranged on the first package substrate (10) in the space defined between the structural inner portion (of 60) and the outer peripheral edges of the first package substrate (10).
As taught by Loo, one of ordinary skill in the art would utilize & modify the above teaching to obtain a circuit component arranged on the first package substrate in the space defined between the structural inner portion and the outer peripheral edges of the first package substrate as claimed, because it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Loo in combination with Heng/Liao due to above reason.
7. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Heng as modified by Liao/Loo as applied to claims 1 & 7 above, and further in view of Shastri et al. (US 2019/0086618).
The teachings of Heng/Liao/Loo have been discussed above.
Re claim 8, Heng/Liao/Loo does not teach the circuit component is one of a cable connector and a silicon photonics package.
Shastri teaches, Fig. 2, [0065], the circuit component is one of a cable connector (54) and a silicon photonics package (silicon PIC 28).
As taught by Shastri, one of ordinary skill in the art would utilize & modify the above teaching to obtain the circuit component is one of a cable connector and a silicon photonics package as claimed, because it aids in achieving a desired package having high density and high bandwidth interconnection.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Shastri in combination with Heng/Liao/Loo due to above reason.
Allowable Subject Matter
8. Claims 12-13 are allowed. The allowable subject matter includes: “a second semiconductor package mounted on the printed circuit board and in communication with the first semiconductor package via the printed circuit board, the second semiconductor package comprising
a second package substrate,
a second semiconductor chip arranged on the second package substrate, and
a second stiffener disposed on the second package substrate, the second stiffener comprising
a second inner portion configured to surround the second semiconductor chip, the second inner portion defining a second space on the second package substrate external to the second inner portion and located between the second inner portion and outer edges of the second package substrate, and
a second plurality of leg portions extending outwardly from the second inner portion toward one or more of (i) the outer edges of the second package substrate and (ii) corners of the second package substrate” (claim 12)
Claims 21 & 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
9. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 6/1/26
Prosecution Insights