CTNF 18/086,232 CTNF 88433 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Election was made without traverse in the reply filed on 4/17/2026. Applicant has elected Group II, corresponding to claims 1-9 and 18-20. Invention Group I, corresponding to claims 10-17, is withdrawn from further consideration. Information Disclosure Statement The information disclosure statement (IDS) submitted on 4/17/2026 has been considered by the examiner. Specification 07-29 AIA The disclosure is objected to because of the following informalities: [0018] “active component die 106” should be “active component die 108 ” (line 6) [0021] “solder pumps” should be “solder bumps” (line 6) Appropriate correction is required. Drawings The drawings submitted on 12/21/2022 have been accepted by the examiner. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1 and 6 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Kim (US # 20220157676) . Regarding Claim 1 , Kim (US # 20220157676) teaches an electronic system, comprising a substrate (12) comprising: a glass core layer (14; [0030]) comprising a cavity (22) through the glass core layer (see Fig. 3B); at least one active component die (20, 21, 23; [0036]) in the cavity; a first buildup layer (16) contacting a first surface (top of 14) of the glass core layer and a first surface (top of 20) of the at least one active component die, wherein the first buildup layer comprises an electrically conductive interconnect (28, 46, 47, 60) contacting the at least one active component die (see 60) and extending to a first surface of the substrate (see 46 on a top surface of 12); a second buildup layer (18) contacting a second surface (bottom of 14) of the glass core layer and a second surface (bottom of 20) of the at least one active component die (the contact is indirect); and one or more solder bumps (36, 36a) on a second surface of the substrate (indirectly on 12) and contacting the second surface of the at least one active component die (indirectly contacting 20). Regarding Claim 6 , Kim (US # 20220157676) teaches the electronic system of claim 1, comprising another active component die (30a, 30b) attached to the first surface of the substrate (see Fig. 1), wherein the electrically conductive interconnect of the first buildup layer connects the at least one active component die in the cavity to the other active component die (see [0028, 47]) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim s 18 and 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US # 20220157676) in view of Kim # 2 (US # 20180090467) . Regarding Claim 18 , Kim (US # 20220157676) teaches an electronic system, the electronic system (see Fig. 1 and corresponding text) comprising: a substrate (12), the substrate comprising: a glass core layer (14) comprising a cavity (22) through the glass core layer; at least one active component die (20) disposed in the cavity; a first buildup layer (16) contacting a first surface of the glass core layer and a first surface of the at least one active component die (similar mapping to the claim 1 mapping), wherein the first buildup layer comprises an electrically conductive interconnect contacting the at least one active component die and extending to a first surface of the substrate (similar mapping to the claim 1 mapping); and a second buildup layer (18) contacting a second surface of the glass core layer and a second surface of the at least one active component die (similar mapping to the claim 1 mapping); and one or more solder bumps (36) on a second surface of the substrate. Although Kim discloses much of the claimed invention, it does not explicitly teach the the electronic system comprising: a motherboard comprising one or more metal cooling structures; the substrate attached to the motherboard; and the one or more solder bumps contacting the metal cooling structures of the motherboard. Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below. For example, Kim # 2 (US # 20180090467) is in the same or analogous field, and it teaches an electronic system (see especially Fig. 8 and corresponding text) comprising: a circuit board (126) comprising one or more metal cooling structures (124); a substrate (102) attached to the motherboard (shown); and the one or more solder bumps (116) contacting the metal cooling structures of the motherboard (shown). A person having ordinary skill in the art would have recognized that modifying the system of Kim with the cooling path suggested by Kim # 2 would be obvious. Specifically, the modification suggested by Kim # 2 would be to employ an electronic system comprising: a motherboard comprising one or more metal cooling structures; the substrate attached to the motherboard; and the one or more solder bumps contacting the metal cooling structures of the motherboard. The rationale for this obvious modification is that a thermal pathway into a motherboard provides cooling for the hot components mounted to it and also provides structure for communication pathways between those components. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of various packaging pathways, such as heat dissipation pathways, are well known in the art (see MPEP 2144.01). Regarding Claim 3 , Kim teaches the electronic system of claim 1, wherein the one or more solder bumps on the second surface of the substrate include comprise one or more solder bumps connected to the inner circuitry of the active component ([0028, 45, 48]). Although Kim discloses much of the claimed invention, it does not explicitly teach the one or more solder bumps connected to one or more power inputs of the at least one active component die. Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below. For example, Kim # 2 is in the same or analogous field, and it teaches many integrated components (see [0011, 48] and Fig. 15), including a system-in-package (SIP) assembly including ASIC, processor, and/or memory stacks (NAND/DRAM), and a dedicated co-packaged input power system (battery 1536). A person having ordinary skill in the art would have recognized that modifying the balls of Kim so as to connect with the power system suggested by Kim # 2 would be obvious. Specifically, the modification suggested by Kim # 2 would be to employ an electronic system of claim 1, wherein one or more solder bumps connected to one or more power inputs of the at least one active component die. The rationale for this obvious modification is that input power is a functional necessity for any embedded active component die, and power inputs are known to necessitate greater thermal dissipation due to greater heat generation. Regarding Claim 4 , although Kim discloses much of the claimed invention, it does not explicitly teach the electronic system of claim 1, wherein the at least one active component die comprises a high bandwidth memory component. Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below. For example, Kim # 2 is in the same or analogous field, and it teaches architectures that provide the structure for high bandwidth memory (“HBM”) to the processor (see Figs. 8 and 12 showing vertical stacking of memory directly over the processor, which would minimize latency). A person having ordinary skill in the art would have recognized that modifying the active component die of Kim with the SIP suggested by Kim # 2 would be obvious. Specifically, the modification suggested by Kim # 2 would be to employ an electronic system of claim 1, wherein the at least one active component die comprises a high bandwidth memory component. The rationale for this obvious modification is that shortening the thermal pathways and also creating high-bandwidth memory pathways are related and would benefit from the same spatial design choices. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of HBM are well known in the art (see MPEP 2144.01). Regarding Claim 5 , although Kim discloses much of the claimed invention, it does not explicitly teach the electronic system of claim 1, wherein the at least one active component die includes comprises multiple memory die disposed in the cavity as a stack of the multiple memory die. Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below. For example, Kim # 2 is in the same or analogous field, and it teaches architectures that provide the structure for stacked memory (132, 136) to the processor (see Figs. 8 and 12 showing vertical stacking of memory directly over the processor, which would minimize latency). A person having ordinary skill in the art would have recognized that modifying the active component die of Kim with the SIP suggested by Kim # 2 would be obvious. Specifically, the modification suggested by Kim # 2 would be to employ an electronic system of claim 1, wherein the at least one active component die includes comprises multiple memory die disposed in the cavity as a stack of the multiple memory die. The rationale for this obvious modification is that shortening the thermal pathways and also creating signal/memory pathways are related and would benefit from the same stacked design. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of stack die are well known in the art (see MPEP 2144.01) . 07-21-aia AIA Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US # 20220157676) in view of Kim # 3 (US # 20180197831) . Regarding Claim 2 , although Kim discloses much of the claimed invention, it does not explicitly teach the electronic system of claim 1, wherein the one or more solder bumps on the second surface of the substrate comprise a signal-carrying solder bump and a thermal-carrying solder bump sized larger than the signal-carrying solder bump. Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below. For example, Kim # 3 is in the same or analogous field, and it teaches a package configuration (100) comprising a substrate (10, 20, 30) comprising a core layer (10); and an embedded active component die (1); build up layers (20) and one or more solder bumps (50a, 50) on a second surface (bottom) of the substrate comprising a signal-carrying solder bump (50) and a thermal-carrying solder bump sized (50a) larger than the signal-carrying solder bump ([0122]). A person having ordinary skill in the art would have recognized that modifying the solder bumps of Kim with the more sophisticated bumps suggested by Kim # 3 would be obvious. Specifically, the modification suggested by REFB would be to employ an electronic system of claim 1, wherein the one or more solder bumps on the second surface of the substrate comprise a signal-carrying solder bump and a thermal-carrying solder bump sized larger than the signal-carrying solder bump. The rationale for this obvious modification is that integrating both signal bumps and thermal bumps provides optimal thermal management while also providing interconnections for computational functions ([0085-97]) . 07-21-aia AIA Claim s 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US # 20220157676) in view of Ecton (US # 20220352076) . Regarding Claim 7 , although Kim discloses much of the claimed invention, it does not explicitly teach the electronic system of claim 6, wherein the electrically conductive interconnect of the first buildup layer comprises a multi-die interconnect bridge providing electrical continuity between at least one input/output (I/O) pad of the at least one active component die in the cavity and at least one I/O pad of the other active component die. Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below. For example, Ecton is in the same or analogous field, and it teaches a similar package system (100) including an first buildup layer (210, 170, 150) comprising electrically conductive interconnect (the conductive parts of the first buildup) comprising a multi-die interconnect bridge (150) providing electrical continuity between at least one input/output (I/O) pad of the at least one active component die in the cavity and at least one I/O pad of the other active component die (see 160). A person having ordinary skill in the art would have recognized that modifying the first buildup layer of Kim with the buildup layer suggested by Ecton would be obvious. Specifically, the modification suggested by Ecton would be to employ an electronic system of claim 6, wherein the electrically conductive interconnect of the first buildup layer comprises a multi-die interconnect bridge providing electrical continuity between at least one input/output (I/O) pad of the at least one active component die in the cavity and at least one I/O pad of the other active component die. The rationale for this obvious modification is that these interconnect bridges provide predictable die-to-die interconnection in a compact package. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of MDIB are well known in the art (see MPEP 2144.01). Regarding Claim 8 , although Kim discloses much of the claimed invention, it does not explicitly teach the electronic system of claim 7, wherein a first side of the multi-die interconnect bridge is electrically connected to the at least one active component die disposed in the cavity and a second side of the multi-die interconnect bridge is electrically connected to at least one input/out (I/O) pad of the other active component die. Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below. For example, Ecton is in the same or analogous field, and it teaches a bridge (see Figs. 1 and 6) wherein a first side (152) of the multi-die interconnect bridge is electrically connected to the at least one active component die (270 1 ; [0037, 41]) and a second side (154) of the multi-die interconnect bridge is electrically connected to at least one input/out (I/O) pad (272 2 ) of an other active component die (270 2 ). A person having ordinary skill in the art would have recognized that modifying the interconnections of Kim with the bridge suggested by Ecton would be obvious. Specifically, the modification suggested by Ecton would be to employ a electronic system of claim 7, wherein a first side of the multi-die interconnect bridge is electrically connected to the at least one active component die disposed in the cavity and a second side of the multi-die interconnect bridge is electrically connected to at least one input/out (I/O) pad of the other active component die. The rationale for this obvious modification is that these interconnect bridges provide predictable die-to-die interconnection in a compact package. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of MDIB are well known in the art (see MPEP 2144.01) . 07-21-aia AIA Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US # 20220157676) in view of Ecton (US # 20220352076) and further in view of Hossain (US # 20200211969) . Regarding Claim 9 , although Kim in view of Ecton discloses much of the claimed invention, it does not explicitly teach the electronic system of claim 6, wherein the least one active component die in the cavity comprises a high bandwidth memory component and the other active component die comprises a compute component. Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below. For example, Hossain is in the same or analogous field, and it teaches an electronic package (100; see Fig. 1A) comprising a substrate (120) wherein an embedded multi-die interconnect bridge (125) connects a peripheral die (140) on top of the package substrate and also includes a high bandwidth memory component (HBM 140, 240; see [0002, 22, 31]) and the other active component die comprises a compute component (154; see [0027]). A person having ordinary skill in the art would have recognized that modifying the dies of Kim in view of Ecton with the dies suggested by Hossain would be obvious. Specifically, the modification suggested by Hossain would be to employ an electronic system of claim 6, wherein the least one active component die in the cavity comprises a high bandwidth memory component and the other active component die comprises a compute component. The rationale for this obvious modification is that these dies provide high performance for advanced nodes and can be reused across package generations. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of this die-pairing are well known in the art (see MPEP 2144.01) . 07-21-aia AIA Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US # 20220157676) in view of Kim # 2 (US # 20180090467) Ecton (US # 20220352076) and further in view of Hossain (US # 20200211969) . Regarding Claim 19 , Kim teaches the electronic system of claim 18, comprising: a compute component die (30a, 30b) attached to the first surface (32) of the substrate (12) wherein the at least one active component die comprises multiple dies (20) arranged in the cavity. Although Kim discloses much of the claimed invention, it does not explicitly teach the electronic system wherein the multiple dies are memory dies arranged as a stack of memory dies and wherein the electrically conductive interconnect provides electrical continuity between the compute component die and the multiple memory dies. Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below. Firstly, Ecton teaches an electronic package containing a compute die (first device (270 1 ) and a second device (270 2 )) mounted on a first surface (top) of a substrate (210); ([0043] describes the variety of possible devices); multiple dies are memory dies arranged as a stack of memory dies (150); electrically conductive interconnect (170, 150, 210) provides electrical continuity between multiple memory dies. Secondly, Hossain teaches an electronic package containing stacked memory dies (150; see also a variation of 150 in Fig. 1B: stacked memory dies 156 1-n ) interconnected by vias (158) and bumps (159), all these stacked on top of a base compute die (154), these are interconnected through the multi-die bridge (EMIB 125) to a peripheral die (high bandwidth memory “HBM” 140). A person having ordinary skill in the art would have recognized that modifying the cavity structure of Kim with the stacked dies suggested by Ecton and Hossain would be obvious. Specifically, the modification suggested by Ecton and Hossain would be to employ an electronic system wherein the multiple dies are memory dies arranged as a stack of memory dies and wherein the electrically conductive interconnect provides electrical continuity between the compute component die and the multiple memory dies. The rationale for this obvious modification is that stacked memory dies with a compute die connected via bridge to HMB is known and simplified design with a predictable expectation of success . 07-21-aia AIA Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US # 20220157676) in view of Kim # 2 (US # 20180090467) Ecton (US # 20220352076) . Regarding Claim 20 , the applicant recites here limitations that are nearly the same scope as Claims 7 and 8, the reasons can be reviewed in that part of the office action. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899 Application/Control Number: 18/086,232 Page 2 Art Unit: 2899 Application/Control Number: 18/086,232 Page 3 Art Unit: 2899 Application/Control Number: 18/086,232 Page 4 Art Unit: 2899 Application/Control Number: 18/086,232 Page 5 Art Unit: 2899 Application/Control Number: 18/086,232 Page 6 Art Unit: 2899 Application/Control Number: 18/086,232 Page 7 Art Unit: 2899 Application/Control Number: 18/086,232 Page 8 Art Unit: 2899 Application/Control Number: 18/086,232 Page 9 Art Unit: 2899 Application/Control Number: 18/086,232 Page 10 Art Unit: 2899 Application/Control Number: 18/086,232 Page 11 Art Unit: 2899 Application/Control Number: 18/086,232 Page 12 Art Unit: 2899 Application/Control Number: 18/086,232 Page 13 Art Unit: 2899 Application/Control Number: 18/086,232 Page 14 Art Unit: 2899 Application/Control Number: 18/086,232 Page 15 Art Unit: 2899
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