Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
The applicant’s most recent amendment, filed on 9/08/2026, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered; the pending claims are 1-6, 9, and 21-33.
Election/Restrictions
Newly submitted claims 21-33 are directed to an invention that is independent or distinct from the invention originally claimed, for the following reasons.
Claims 21 to 27 require a metallization layer on a second surface of the at least one active component die, require the second buildup layer to contact the second surface of the glass core layer only, and require a second solder bump in contact with the metallization layer within an opening of the second buildup layer. Claims 28 to 33 require, in addition, an adhesive on the metallization layer, the second buildup layer contacting the second surface of the glass core layer and the adhesive, and a second solder bump in contact with the metallization layer and the adhesive within an opening of the second buildup layer.
The claims originally presented and acted upon on the merits recite the opposite arrangement at that interface. Each of claims 1 to 9 and 18 to 20, as presented in the reply filed April 17, 2026 and examined in the action mailed June 8, 2026, recites “a second buildup layer contacting a second surface of the glass core layer and a second surface of the at least one active component die,” and claim 1 recites “one or more solder bumps on a second surface of the substrate and contacting the second surface of the at least one active component die.” None of claims 1 to 9 and 18 to 20 recites a metallization layer, an adhesive, or any other layer interposed between the second surface of the die and either the second buildup layer or a solder bump. The sole claim ever to recite such a layer is claim 17, “forming a solderable metallization layer on the second surface of the at least one active component die,” a method claim of Invention Group I, which was not elected, was never examined on the merits, and has now been cancelled.
The two arrangements are mutually exclusive. The specification presents them as alternatives: the larger opening in the bottom buildup layer “extends to the solderable metallization layer 120 or the bottom surface of an active component die 108” (application [0027]). It also describes layer 120 as a layer of the package rather than part of the die, in that it “can be added to the cavity before the active component die 108 or dies are placed” (application [0025]). A structure in which the second buildup layer and the second solder bump meet the second surface of the die itself cannot also be one in which a separately fo1med metallization layer, and in claims 28 to 33 an adhesive, is interposed between that surface and each of them. The claims therefore do not overlap in scope. See MPEP 806.04(f).
A serious search burden would be imposed. The application is classified in H10W 90/00, “Package configurations,” and the connection recited in the claims originally presented falls in H10W 72/20, “Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps,” and H10W 90/701, “Package configurations characterized by the relative positions of pads or connectors relative to package parts.” The search made for those claims was directed to a solder bump carried through an opening in a dielectric layer onto the back surface of a die held in a cavity. Claims 21 to 33 direct the search elsewhere. The separately fanned metallization laid into the cavity before the die is placed is searched as a pad or under-bump metallurgy for a bump connector, in H10W 72/29, “Bond pads specially adapted therefor,” and H10W 72/90, “Bond pads, in general,” with H10W 72/951 and H10W 72/952 for the materials of such pads. The die-attach adhesive through which the bump opening passes is searched as a die-attach connector in H10W 72/30, the definition of which gives as its example “an insulating adhesive to connect the inactive surface of a chip to a package substrate,” and in H10W 20/425, “Barrier, adhesion or liner layers.” Neither search has been made, because no claim originally presented recited either feature, and neither is likely to result in finding art pertinent to the invention originally claimed. See MPEP 808.02.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 21-33 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the requirement. Applicant is advised that if a claim under examination is later indicated as allowable, any withdrawn claim that requires all the limitations of that allowable claim will be considered for rejoinder. See MPEP 821.04(a).
Response to Arguments
Applicant’s arguments with respect to all pending claims have been considered but are moot because the arguments do not apply to the current grounds of rejection.
Specification
The objections to paragraphs [0018] and [0021] are withdrawn in view of the replacement paragraphs filed September 8, 2026.
The disclosure is objected to under 37 CFR 1.71 because of the following infom1alitics. In [0022], “the active comment die 108” should read “the active component die 108.” In [0027), in “signal-carrying solder bumps 116 are formed in the smaller openings 230 a larger thermal-carrying solder bump 118 is fanned,” the word “and” is missing after “230.” In [0031], “FIG. 4 is a is a side view” should read “FIG. 4 is a side view.”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1, 4, 5, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim-676 (US # 20220157676) in view of Kim-467 (US # 20180090467).
Regarding Claim 1, Kim-676 teaches:
An apparatus (integrated circuit package 10; Kim-676 Fig. 1), comprising:
a glass core layer (core layer 14, which can include glass; Kim-676 [0030]) comprising a cavity (cavity 22; Kim-676 Fig. 1) through the glass core layer (cavities 22 can extend completely through core layer 14; Kim-676 Fig. 3B, [0031]);
at least one active component die (die 20; Kim-676 [0037]) in the cavity (Kim-676 Figs. 1 and 3D);
a first buildup layer (first dielectric layer 16 formed of laminated sub layers 48, 50; Kim-676 [0034]) contacting a first surface of the glass core layer (top surface of 14; Kim-676 Fig. l) and a first surface of the at least one active component die (top of die 20, over which first sublayer 48 is disposed; Kim-676 Fig. 3E, [0065]), wherein the first buildup layer comprises an electrically conductive interconnect (first patterned conductive layer 28, third patterned conductive layer 46 and via 60; Kim-676 Fig. 1, [0040], [0043], [0047]) contacting the at least one active component die (via 60 connected to top contact 21 of die 20; Kim-676 [0040]);
a second buildup layer (second dielectric layer 18 formed of sub layers 52, 54; Kim-676 [0034]) contacting a second surface of the glass core layer (bottom surface 104 of 14, on which first sublayer 52 is disposed; Kim-676 Figs. 3C and 3F, [0063], [0066]) and a second surface of the at least one active component die (bottom of die 20, which, where cavity 22 extends completely through core layer 14, is placed directly on carrier layer 102 or on a release layer disposed on it, on which bottom surface 104 of the core layer also lies, so that sublayer 52, applied after the carrier is removed, lies against both; Kim-676 Figs. 3C to 3F, [0063], [0064], [0066); first sublayer 52 lying across the bottom of die 20, through which via 66 reaches bottom contact 23, Fig. 1, [0040]); and
a plurality of solder bumps (conductive pads 36, which can include solder balls, solder or bumps, Kim-676 [0048]; and second conductive pads 36a, which Fig. 1 draws in the same form as pads 36, Kim-676 Fig. 1, [0053]), wherein a first of the plurality of solder bumps is in contact with the second buildup layer (a pad 36 or 36a disposed on outer surface 38 of second dielectric layer 18; Kim-676 Fig. 1, [0028], [0053]) and a second of the plurality of solder bumps (the pad 36 beneath die 20 that is electrically connected to die 20; Kim-676 Fig. 1, [0048])
Although Kim-676 discloses much of the claimed invention, it does not explicitly teach the plurality of solder bumps, wherein the second of the plurality of solder bumps is in contact with the second surface of the at least one active component die within an opening of the second buildup layer.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Kim-467 is in the same or analogous field, and it teaches solder balls (116; Kim-467 Fig. 3, [0023]) in contact with a metal body on the second side of a die (heat spreader 112, e.g., a copper slug, coupled with processor 106 through thermal interface material 114; Kim-467 Fig. 3, [0022], [0023]; processor 106, Figs. 6 and 8), each solder ball lying within a through-via of the dielectric that covers that side of the die (molding compound 120, a portion 122 of which is ground away to expose solder balls 116, which form through mold via structures; Kim-467 Fig. 6, [0025], [0026]) and being joined to a metal pad of a circuit board (metal pad 124 of PCB 126; Kim-467 Fig. 8, [0028]; bonding to a PCB, [0027]).
A person having ordinary skill in the art would have recognized that modifying the connection between pad and bottom contact of Kim-676 with the solder-filled dielectric via suggested by Kim-467 would be obvious. Specifically, the modification suggested by Kim-467 would be to employ a plurality of solder bumps, wherein the second of the plurality of solder bumps is in contact with the second surface of the at least one active component die within an opening of the second buildup layer. The rationale for this obvious modification is that solder carried through the dielectric onto the back of the die allows ready thermal conductivity from the die toward the circuit board (Kim-467 [0026]: solder balls 116 within molding compound 120 “may allow ready thermal conductivity”; [0027]). Kim-676 teaches that packages whose die contacts are distributed over source and drain pads can also allow heat to be drawn from the die through two or more sides of the package (Kim-676 [0026]). It is the examiner's reasoning that a solder body landing directly on bottom contact 23 shortens the path between die 20 and pad 36, which in Kim-676 otherwise runs through via 66 and second patterned conductive layer 34 (Kim-676 Fig. 1, [0040], [0045], [0048]), and so improves that heat path. Kim-676 states that pads 36 can be electrically connected to dies 20 using any suitable technique, and places pads 36 on or in second dielectric layer 18 (Kim-676 [0028], [0040], [0048], [0071]).
Regarding Claim 4, Kim-676 as modified by Kim-467, as applied to claim 1, teaches the apparatus of claim 1, wherein the first of the plurality of solder bumps is a signal-carrying solder bump (a pad 36, which can be electrically connected to first patterned conductive layer 28 and to devices 30, the listed devices including a logic circuit or analog circuit; Kim-676 [0046], [0048]) and the second of the plurality of solder bumps is a power solder bump (the solder of pad 36 joined to bottom contact 23 in the combination applied to claim 1, bottom contact 23 being connected to pad 36 in Kim-676 through via 66 and second patterned conductive layer 34 (Kim-676 Fig. 1, (0040], [0045], [0048]), and die 20 being a die that can be a high-voltage die and can include a MOSFET or IGBT (Kim-676 [0037]); Kim-676 teaches that multiple contacts of a die can be distributed over the source and drain pads of the package, which can increase maximum current capability (Kim-676 [0026])).
Regarding Claim 5, Kim-676 as modified by Kim-467, as applied to claim 1, teaches the apparatus of claim 1, wherein the at least one active component die comprises (die 20; Kim-676 [0037])
Kim-676 as modified by Kim-467 does not teach “a high bandwidth memory component or a stack of multiple memory dies”.
The prior art before the effective filing date of the claimed invention renders that difference obvious, as explained below.
For example, Kim-467 is in the same or analogous field, and it teaches a stack of multiple memory dies (NAND stack 136, coupled to DRAM 132; Kim-467 Fig. 8, [0029]) co-packaged with the heat-generating die, the packaged components being die stacks (Kim-467 [0011]). Kim-467 teaches the second alternative of the claim; it does not use the term high bandwidth memory. A person having ordinary skill in the art would have recognized that modifying the stacked dies 20 of Kim-676 as modified by Kim-467 with the memory die stack suggested by Kim-467 would be obvious. Specifically, the modification suggested by Kim-467 would be to employ, as the at least one active component die, “a stack of multiple memory dies”, which meets the second alternative of the claim (NAND stack 136; Kim-467 Fig. 8, [0029]). The rationale for this obvious modification is the examiner's: Kim-676 accepts “any suitable type of die or dies 20,” including low-voltage dies, and contemplates dies 20 arranged in a stacked relationship (Kim-676 [003 7]); Kim-467 identifies memory die stacks as dies packaged in a system in package (Kim-467 [0011]: the co-packaged components, including DRAM and NAND, “may be die stacks”; [0029]); and substituting one known packaged die for another would have yielded the predictable result of a package containing a memory die stack (MPEP 2143(1)(8)).
Regarding Claim 9, Kim-676 as modified by Kim-467 does not teach “comprising a motherboard comprising a metal cooling structure, wherein the second of the plurality of solder bumps is in contact with the metal cooling structure”.
The prior art before the effective filing date of the claimed invention renders that difference obvious, as explained below.
For example, Kim-467 is in the same or analogous field, and it teaches a metal pad that may be coupled to a circuit board and that completes a thermal path from the die (metal pad 124 coupled to PCB 126; Kim-467 Fig. 8, [0028]); it is the examiner's finding that pad 124, so coupled, is a metal cooling structure of the board with which the solder balls on the back of the die are in contact (solder balls 116 thermally coupled to metal pad 124; Kim-467 Fig. 8, [0028]), and it teaches that a computing device houses a board such as motherboard 1502 (Kim-467 Fig. 15, [0047]) and that the processor of that device may include a die in a package assembly such as package assembly 700 or 800 (Kim-467 [0051 ]), package assembly 800 being the assembly shown with PCB 126 (Kim-467 Fig. 8, [0028]). It is the examiner's finding that one of ordinary skill would have understood PCB 126 to be such a board.
A person having ordinary skill in the art would have recognized that modifying the mounting of package 10 of Kim-676 as modified by Kim-467 with the board-side metal pad suggested by Kim-467 would be obvious. Specifically, the modification suggested by Kim-467 would be to employ an apparatus “comprising a motherboard comprising a metal cooling structure, wherein the second of the plurality of solder bumps is in contact with the metal cooling structure” (metal pad 124; Kim-467 Fig. 8, [0028]). The rationale for this obvious modification is that the pad completes a thermal path from the die through the solder to the board (Kim-467 [0028]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim-676 (US # 20220157676) in view of Kim-467 (US # 20180090467) and Kim-831 (US # 20180197831).
Regarding Claim 2, Kim-676 as modified by Kim-467, as applied to claim l , teaches the apparatus of claim 1, wherein the first of the plurality of solder bumps is a signal-carrying solder bump (a pad 36, which can be electrically connected to first patterned conductive layer 28 and to devices 30, the listed devices including a logic circuit or analog circuit; Kim-676 (0046], (0048]; it is the examiner's finding that a pad connected to a logic or analog circuit carries signals) and the second of the plurality of solder bumps is a thermal-carrying solder bump (the solder of pad 36 against bottom contact 23 in the combination applied to claim 1, which forms a thermal path from the die to the board as in Kim-467 (Kim-467 [0027], [0028]); Kim-676 also teaches that heat can be drawn from the die through two or more sides of the package (Kim-676 [0026]))
A person having ordinary skill in the art would have recognized that modifying the mounting of package 10 of Kim-676 as modified by Kim-467 with the board-side metal pad suggested by Kim-467 would be obvious. Specifically, the modification suggested by Kim-467 would be to employ an apparatus “comprising a motherboard comprising a metal cooling structure, wherein the second of the plurality of solder bumps is in contact with the metal cooling structure” (metal pad 124; Kim-467 Fig. 8, [0028]). The rationale for this obvious modification is that the pad completes a thermal path from the die through the solder to the board (Kim-467 [0028]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kim-676 (US # 20220157676) in view of Kim-467 (US # 20180090467) and Ecton-076 (US # 20220352076).
Regarding Claim 6, Kim-676 as modified by Kim-467, as applied to claim 1, teaches the apparatus of claim 1, comprising a second active component die (device 30a or 30b, the listed devices 30 including a logic circuit or analog circuit; Kim-676 Fig. 1, [0046], [0047]; it is the examiner's finding that a logic or analog circuit device is an active component die) coupled to the electrically conductive interconnect of the first buildup layer (devices 30a, 306 are connected to die 20 by third patterned conductive layer 46 and via 60; Kim-676 [0047]), wherein the electrically conductive interconnect of the first buildup layer comprises (the interconnect of first dielectric layer identified above for the base claim)
Kim-676 as modified by Kim-467 does not teach a multi-die interconnect bridge providing electrical continuity between at least one input/output (I/O) pad of the at least one active component die in the cavity and at least one I/O pad of the second active component die.
The prior art before the effective filing date of the claimed invention renders that difference obvious, as explained below.
For example, Ecton-076 is in the same or analogous field (glass-layer package substrates with embedded silicon components), and it teaches a bridge embedded in the substrate (bridge 150; Ecton-076 Fig. 1, [0037]) having a device-to-device interconnection route between bond pads (route 160 between bond pads 162; Ecton-076 Fig. l, [0037]) through which a first and a second integrated circuit device are electrically connected (devices 270 1 and 2702; Ecton-076 Fig. 1, [0043]). Ecton-076 connects two devices mounted on the substrate; it does not show the bridge connected to a die in a cavity, and it places bridge 150 in an opening of a glass layer rather than within a buildup layer. It is the examiner's reasoning that the modification would place the bridge in first dielectric layer 16, where the interconnect between die 20 and device 30 already lies (Kim-676 [0043], [0047], [0069]).
A person having ordinary skill in the art would have recognized that the bridge of Ecton-076 would have improved Kim-676 as modified by Kim-467. Specifically, the modification suggested by Ecton-076 would be to employ, in first dielectric layer 16 between top contact 21 of die 20 and device contact 62 of device 30, a multi-die interconnect bridge providing electrical continuity between at least one input/output (I/O) pad of the at least one active component die in the cavity and at least one I/O pad of the second active component die” (bridge 150; Ecton-076 Fig. 1, [0037]). The rationale for this obvious modification is that, as Ecton-076 teaches for one embodiment, a silicon bridge may be preferred because the interconnect pitches and line widths achievable with silicon process technology may be significantly smaller, and thus more dense, than copper signal lines in polymer layers (Ecton-076 [0038]).
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 3, although the prior art shows substantial features of the claimed invention, the prior art reviewed by the examiner neither teaches nor reasonably suggests all the claimed limitations, including a thermal-carrying solder bump sized larger than the
signal-carrying solder bump that covers substantially an entirety of the second surface of the die in the cavity.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER A JOHNSON/Primary Examiner, Art Unit 2899
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