DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Application
In response to Office action dated 04/03/2026 (“04-03-26 OA”), Applicant amended title and filed remarks in reply dated 07/06/2026 (“07-06-26 Reply”).
Response to Arguments
Applicant’s amendments to title have overcome the objection to specification as set forth under line item number 1 of the 04-03-26 OA.
The prior art rejections as set forth under line item number 2 of the 04-03-26 OA under 35 U.S.C. §102(a)(2) is withdrawn/overcome in view of Applicant’s statement under 35 U.S.C. §102(b)(2)(C) establishing common ownership as made clear in the remarks of the 07-06-26 Reply.
The prior art rejections as set forth under line item number 2 of the 04-03-26 OA under 35 U.S.C. §102(a)(1) as being anticipated by US 2022/0310602 A1 to Greene et al. (“Greene”) is maintained.
Applicant’s traversal of the §102(a)(2) rejection via the common ownership exception under 35 U.S.C. §102(b)(2)(C) is acknowledged and accepted. However, this exception applies only to prior art under §102(a)(2) and does not disqualify a reference as prior art under §102(a)(1). See MPEP 2152.02(c) and MPEP 2154.02(c).
Greene was published on September 29, 2022, which is before the effective filing date of the claimed invention (December 21, 2022). The inventive entity of the instant application is also different from that of Greene. Therefore, Greene remains available as prior art under §102(a)(1), and the anticipation rejection is maintained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 9-10, 12, 14-16 and 18 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by US 2022/0310602 A1 to Greene et al. (“Greene”).
Applicant has provided statement in the remarks of the 07-06-26 Reply showing that the claimed invention and the subject matter disclosed in the prior art reference were owned by, or subject to an obligation of assignment to, the same entity as International Business Machines Corporation not later than the effective filing date of the claimed invention, or the subject matter disclosed in the prior art reference was developed and the claimed invention was made by, or on behalf of one or more parties to a joint research agreement in effect not later than the effective filing date of the claimed invention. However, although the Greene reference has been excepted as prior art under 35 U.S.C. 102(a)(2), it is still applicable as prior art under 35 U.S.C. 102(a)(1) that cannot be excepted under 35 U.S.C. 102(b)(2)(C).
Applicant may rely on the exception under 35 U.S.C. 102(b)(1)(A) to overcome this rejection under 35 U.S.C. 102(a)(1) by a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application, and is therefore not prior art under 35 U.S.C. 102(a)(1). Alternatively, applicant may rely on the exception under 35 U.S.C. 102(b)(1)(B) by providing evidence of a prior public disclosure via an affidavit or declaration under 37 CFR 1.130(b).
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Regarding independent claim 1, Greene teaches in Figure 15 of a semiconductor device (see title and abstract), comprising:
a first stacked structure nFET disposed on a substrate 102 (“substrate”; paragraph 0036), wherein the first stacked structure nFET comprises a first plurality of gate structures 134 (“metal gate”; paragraph 0057) alternately stacked with a first plurality of channel layers 108 (“active semiconductor layer”; paragraph 0040; this layer appears to operate as a channel);
a first plurality of epitaxial source/drain regions 126 (“nFET layer”; paragraph 0052; this layer is epitaxially grown and appears to operate as source/drain regions. See paragraph 0037: “Accordingly, the BDI layer 104 isolates the source/drain regions from the substrate 102 and/or isolates the nanosheet region from the substrate 102”) disposed on sides of the first stacked structure nFET;
a first dielectric layer 104 (“bottom dielectric isolation BDI layer”; paragraph 0037) disposed between (see Figure 15) the first stacked structure nFET and the substrate 102, and between (see Figure 15) the first plurality of epitaxial source/drain regions 126 and the substrate 102;
a second stacked structure pFET disposed on the substrate 102, wherein the second stacked structure pFET comprises a second plurality of gate structures 134 alternately stacked with a second plurality of channel layers 108;
a second plurality of epitaxial source/drain regions 122 (“pFET layer”; paragraph 0050; this layer is epitaxially grown and appears to operate as source/drain regions) disposed on sides of the second stacked structure pFET; and
a second dielectric layer 104 disposed between (see Figure 15) the second stacked structure pFET and the substrate 102, wherein at least a portion of the second plurality of epitaxial source/drain regions 122 contact (i.e., directly contacting in Figure 15) the substrate 102.
Regarding claim 2, Greene teaches wherein the first dielectric layer 104-nFET isolates (see Figure 15) the first plurality of epitaxial source/drain regions 126 from the substrate 102.
Regarding claim 3, Greene teaches wherein portions of respective ones of the second plurality of epitaxial source/drain regions 122 are formed on respective lateral sides (see Figure 15) of the second dielectric layer 104-pFET.
Regarding claim 4, Greene teaches wherein bottom surfaces of respective ones the first plurality of epitaxial source/drain regions 126 contact a top surface (see Figure 15) of the first dielectric layer 104-nFET region.
Regarding claim 5, Greene teaches wherein bottom surfaces (see Figure 15) of respective ones the second plurality of epitaxial source/drain regions 122 contact a top surface (see Figure 15) of the substrate 102.
Regarding claim 9, Greene teaches wherein the first plurality of epitaxial source/drain regions 126 contact sides (see Figure 15; directly contact) of the first plurality of channel layers 108; and the second plurality of epitaxial source/drain regions 122 contact sides (see Figure 15; directly contact) of the second plurality of channel layers 108.
Regarding claim 10, Greene teaches of a first plurality of spacers 118 (“inner spacers”; paragraph 0049) disposed on lateral sides (see Figure 15) of the first plurality of gate structures 134; and a second plurality of spacers 118 disposed on lateral sides (see Figure 15) of the second plurality of gate structures 134.
Regarding claim 12, Greene teaches wherein the first stacked structure nFET and the first plurality of epitaxial source/drain regions correspond to an n-type transistor (see claim 1 rejection supra and Figure 15 labels), and the second stacked structure pFET and the second plurality of epitaxial source/drain regions correspond to a p-type transistor (see claim 1 rejection supra and Figure 15 labels).
Regarding independent claim 14, Greene teaches in Figure 15 of a semiconductor device (see title and abstract), comprising:
a first nanosheet structure nFET (i.e., nanosheet is used throughout Greene) disposed on a substrate 102, wherein the first nanosheet structure nFET comprises a first plurality of stacked channel layers 108;
a first plurality of source/drain regions 126 disposed on lateral sides (see Figure 15) of the first nanosheet structure nFET;
a first dielectric layer 104-nFET disposed between the first nanosheet structure nFET and the substrate 102, and between (see Figure 15) the first plurality of source/drain regions 126 and the substrate 102;
a second nanosheet structure pFET disposed on the substrate 102, wherein the second nanosheet structure pFET comprises a second plurality of stacked channel layers 108;
a second plurality of source/drain regions 122 disposed on lateral sides (see Figure 15) of the second nanosheet structure pFET; and
a second dielectric layer 104-pFET disposed between the second nanosheet structure pFET and the substrate 102, wherein at least a portion (see Figure 15) of the second plurality of source/drain regions 122 contact (i.e., directly contact) the substrate 102.
Regarding claim 15, Greene teaches wherein bottom surfaces of respective ones of the first plurality of source/drain regions 126 contact a top surface (see Figure 15) of the first dielectric layer 104-nFET.
Regarding claim 16, Greene teaches wherein bottom surfaces of respective ones the second plurality of source/drain regions 122 contact a top surface (see Figure 15; directly contacting) of the substrate 102.
Regarding independent claim 18, Greene teaches in Figure 15 of a semiconductor device (see title and abstract), comprising:
at least two stacked nanosheet transistor nFET/pFET (i.e., nanosheet is described throughout Greene) structures on a substrate 102;
a first dielectric layer 104-nFET disposed between a first stacked nanosheet transistor structure nFET of the at least two stacked nanosheet transistor structures nFET/pFET and the substrate 102;
a second dielectric layer 104-pFET disposed between a second stacked nanosheet transistor structure pFET of the at least two stacked nanosheet transistor structures nFET/pFET and the substrate 102;
a first plurality of source/drain regions 126 corresponding to the first stacked nanosheet transistor structure nFET, wherein the first plurality of source/drain regions 126 is disposed on and separated from the substrate 102 by the first dielectric layer 104-nFET; and
a second plurality of source/drain regions 122 corresponding to the second stacked nanosheet transistor structure pFET, wherein the second plurality of source/drain regions 122 is disposed on and contacts (see Figure 15; directly contacts) the substrate 102.
Allowable Subject Matter
Claims 6-8, 11, 13, 17 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 6 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 6, wherein the first plurality of channel layers and the second plurality of channel layers each comprise strained carbon doped silicon.
Dependent claims 7-8 contain allowable subject matter, because they depend on the allowable subject matter of claim 6.
Claim 11 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 11, wherein the first plurality of channel layers comprise carbon doped silicon, and the second plurality of channel layers comprise silicon.
Claim 13 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 13, first bottom surfaces of respective ones the second plurality of epitaxial source/drain regions contact a top surface of the second dielectric layer; and second bottom surfaces of respective ones the second plurality of epitaxial source/drain regions contact a top surface of the substrate.
Claim 17 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 17, wherein the first plurality of stacked channel layers and the second plurality of stacked channel layers each comprise carbon doped silicon.
Claim 19 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 19, wherein the first stacked nanosheet transistor structure comprises a first plurality of channel layers; the second stacked nanosheet transistor structure comprises a second plurality of channel layers; and the first plurality of channel layers and the second plurality of channel layers each comprise carbon doped silicon.
Claim 20 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 20, wherein the at least two stacked nanosheet transistor structures, the first plurality of source/drain regions and the second plurality of source/drain regions correspond to n-type transistors.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P DULKA whose telephone number is (571)270-7398. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ELISEO RAMOS-FELICIANO can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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16 July 2026
/John P. Dulka/Primary Examiner, Art Unit 2817
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