DETAILED ACTION
This Office Action, based on application 18/086,315 filed 21 December 2022, is entered responsive to applicant’s initial filing. Claims 1-20 are currently pending and have been fully considered below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 21 December 2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by PARK et al (US PGPub 2020/0126621).
PARK discloses:
Claim 15: A method, comprising:
controlling access to three-dimensional (3D) NAND media (Fig 1, Memory Device 10; ¶[0005] – “A non-volatile memory device may have a 3D memory cell array”; ¶[0038] – “embodiments are described for the case in which the plurality of memory cells include NAND flash memory cells”) with a plurality of decks (Abstract – “A nonvolatile memory device includes a first memory stack including first memory cells vertically stacked on each other, a second memory stack including memory cells vertically stacked on each other” – {a stack layer or portion is commonly referred to as a ‘deck’}); and
configuring a targeted block of the 3D NAND media in a hybrid deck single-level cell (SLC) mode in response to a command from a host (¶[0136] – “at least one of the flash memory devices … may program the memory cells on the lower portion of the plurality of memory stacks using an SLC program {analogous to ‘a first program mode’}, for example, the memory cells on the middle portion of the plurality of memory stacks using a TLC program {a stack layer or portion is commonly referred to as a ‘deck’; since the deck may use a TLC program, the deck is ‘hybrid’}, for example …”; ¶[0037] – “the stack manager may program the memory cells in a lower portion of the plurality of memory stacks in 1 bit, the memory cells in a middle portion in 2 bits …”; ¶[0031] – “the memory controller may control the non-volatile memory device in response to a write request or a read request received from the host HOST”).
Claim 16: The method of claim 15, further comprising: configuring a first deck of the targeted block in a SLC mode in response to the command from the host; and configuring a second deck of the targeted block in a native mode in response to the command from the host (¶[0136] – “at least one of the flash memory devices … may program the memory cells on the lower portion of the plurality of memory stacks using an SLC program {analogous to ‘a first program mode’}, for example, the memory cells on the middle portion of the plurality of memory stacks using a TLC program {analogous to ‘a second program mode’ and/or ‘a native mode’}, for example …”; ¶[0037] – “the stack manager may program the memory cells in a lower portion of the plurality of memory stacks in 1 bit, the memory cells in a middle portion in 2 bits …”; ¶[0031] – “the memory controller may control the non-volatile memory device in response to a write request or a read request received from the host HOST”).
Claim 17: The method of claim 16, further comprising: configuring a third deck of the targeted block in the native mode in response to the command from the host (¶[0136] – “at least one of the flash memory devices … may program … the memory cells on the upper portion of the plurality of memory stacks using an SLC program or an MLC program, for example.”).
Claim 18: The method of claim 16, further comprising: setting one or more of a pass voltage and a program verify voltage (¶[0048] – “The voltage generator 130 may generate various kinds of voltages for performing the program operation, the read operation, and an erase operation for the memory cell array 140 based on the voltage control signal Ctrl vol. The voltage generator 130 may generate word line voltages VWL, for example, a program voltage (or a write voltage), a read voltage, a pass voltage (or a word line non-selection voltage), a verify voltage, a recovery voltage, etc”) for one or more of the first deck and the second deck in accordance with an offset profile indicated by the command from the host (¶[0088] – “when the memory cells of the second memory stack ST2 have cell characteristics such as a threshold voltage distribution that is shifted by the offset α from cell characteristics of the memory cells of the first memory stack ST1, the offset α may be added to the determined voltage (e.g., V1_4) of an operation performed on the first memory stack ST1. The sum of the offset α and the determined voltage may be applied to the second memory stack ST2”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over PARK in further view of NAMALA et al (US PGPub 2022/0066894).
With respect to Claim 1, PARK discloses a memory device, comprising:
NAND media (¶[0036] – “example embodiments include managed memory devices implementing NAND flash memory cells”) with a plurality of decks (Abstract – “A nonvolatile memory device includes a first memory stack including first memory cells vertically stacked on each other, a second memory stack including memory cells vertically stacked on each other” – {a stack layer or portion is commonly referred to as a ‘deck’}); and
circuitry coupled to the NAND media (Fig 2, Control Logic 110) to:
configure the NAND media in a first program mode for the first block of the superblock; and
configure the NAND media in a second program mode for the second block of the superblock (¶[0136] – “at least one of the flash memory devices … may program the memory cells on the lower portion of the plurality of memory stacks using an SLC program {analogous to ‘a first program mode’}, for example, the memory cells on the middle portion of the plurality of memory stacks using a TLC program {analogous to ‘a second program mode’}, for example …”; ¶[0037] – “the stack manager may program the memory cells in a lower portion of the plurality of memory stacks in 1 bit, the memory cells in a middle portion in 2 bits …”).
PARK may not explicitly disclose control access to a superblock, wherein the superblock includes at least a first block that corresponds to memory cells aligned along the pillar in a first deck of the plurality of decks and a second block that corresponds to memory cells aligned along the pillar in a second deck of the plurality of decks of memory cells aligned along a pillar of the NAND media.
However, NAMALA discloses control access to a superblock (Fig 4, Block 402A, 402B), wherein the superblock includes at least a first block (Fig 4, Sub-Block 402A0…402An, 402B0…402Bn; ¶[0068] – “a sub-block may be termed a deck”) that corresponds to memory cells aligned along the pillar in a first deck of the plurality of decks and a second block (Fig 4, Sub-Block 402A0…402An, 402B0…402Bn; ¶[0068] – “a sub-block may be termed a deck”) that corresponds to memory cells aligned along the pillar in a second deck of the plurality of decks of memory cells aligned along a pillar of the NAND media (¶[0077] – Memory block 500 may include two distinct portions or ‘decks’ 505 and 510. Each deck has one or more data word lines, one or more dummy word lines (DWL), and one or more select gates that formed about a plurality of pillars”).
PARK and NAMALA are analogous art because they are from the same field of endeavor of configuring flash memory. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of PARK and NAMALA before him or her, to organize the storage units of PARK to be coupled to pillars taught by NAMALA. A motivation for doing so would have been to enable program voltages to be applied to targeted memory cells that share a common channel (¶[0054]). Therefore, it would have been obvious to combine PARK and NAMALA to obtain the invention as specified in the instant claims.
With respect to Claim 2, the combination of PARK and NAMALA disclose the memory device of claim 1.
PARK further discloses wherein the circuitry is further to: configure the NAND media in the second program mode for a third block of the superblock (¶[0136] – “at least one of the flash memory devices … may program … the memory cells on the upper portion of the plurality of memory stacks using an SLC program or an MLC program, for example.”).
NAMALA further discloses wherein the third block corresponds to memory cells aligned along the pillar in a third deck of the plurality of decks (¶[0077] – Memory block 500 may include two distinct portions or ‘decks’ 505 and 510. Each deck has one or more data word lines, one or more dummy word lines (DWL), and one or more select gates that formed about a plurality of pillars … the memory block 500 includes three word lines per deck, 4 pillars per deck, and two decks, but in other examples … more than two decks may be utilized”).
With respect to Claim 3, the combination of PARK and NAMALA disclose the memory device of claim 1.
PARK further discloses wherein the first program mode is a single-level cell mode and wherein the second program mode is a native mode of the NAND media (¶[0136] – “at least one of the flash memory devices … may program the memory cells on the lower portion of the plurality of memory stacks using an SLC program {analogous to ‘a first program mode’}, for example, the memory cells on the middle portion of the plurality of memory stacks using a TLC program {analogous to ‘a second program mode’ and/or ‘a native mode’}, for example …”; ¶[0037] – “the stack manager may program the memory cells in a lower portion of the plurality of memory stacks in 1 bit, the memory cells in a middle portion in 2 bits …”).
With respect to Claim 4, the combination of PARK and NAMALA disclose the memory device of claim 1.
NAMALA further discloses wherein the first block is to be reserved to store system-specific information (¶[0025] – “These virtual blocks may be constructed from any number of different salvaged block portions and may store user data, system data, system table information, and the like”).
With respect to Claim 5, the combination of PARK and NAMALA disclose the memory device of claim 4.
NAMALA further discloses wherein the second block is to be available to store general user data (¶[0025] – “These virtual blocks may be constructed from any number of different salvaged block portions and may store user data, system data, system table information, and the like”).
With respect to Claim 6, the combination of PARK and NAMALA disclose the memory device of claim 1.
PARK further discloses wherein the circuitry is further to configure the NAND media in accordance with respective offsets for respective voltage settings for the first and second blocks (¶[0088] – “the stack manager 120 may determine the offset α by applying a plurality of voltages to each of the first memory stack ST1 and the second memory stack ST2”).
With respect to Claim 7, the combination of PARK and NAMALA disclose the memory device of claim 1.
PARK further discloses wherein the NAND media comprises three-dimensional NAND memory cells (¶[0005] – “A non-volatile memory device may have a 3D memory cell array”).
Claim(s) 8-10 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over PARK.
With respect to Claim 8, PARK discloses a system, comprising:
a processor (Fig 1, Memory Controller 20); and
a three-dimensional (3D) memory device (Fig 1, Memory Device 10; ¶[0005] – “A non-volatile memory device may have a 3D memory cell array”) coupled with the processor, wherein the 3D memory device includes 3D NAND media (¶[0038] – “embodiments are described for the case in which the plurality of memory cells include NAND flash memory cells”) with a plurality of decks (Abstract – “A nonvolatile memory device includes a first memory stack including first memory cells vertically stacked on each other, a second memory stack including memory cells vertically stacked on each other” – {a stack layer or portion is commonly referred to as a ‘deck’}), and a controller (Fig 2, Control Logic 110) coupled to the 3D NAND media to:
configure a first deck of the plurality of decks for a targeted block in a first program mode in response to a command, and
configure a second deck of the plurality of decks for the targeted block in a second program mode in response to the command (¶[0136] – “at least one of the flash memory devices … may program the memory cells on the lower portion of the plurality of memory stacks using an SLC program {analogous to ‘a first program mode’}, for example, the memory cells on the middle portion of the plurality of memory stacks using a TLC program {analogous to ‘a second program mode’}, for example …”; ¶[0037] – “the stack manager may program the memory cells in a lower portion of the plurality of memory stacks in 1 bit, the memory cells in a middle portion in 2 bits …”; ¶[0031] – “the memory controller may control the non-volatile memory device in response to a write request or a read request received from the host HOST”).
PARK may not explicitly disclose wherein the command indicates the targeted block and the first deck.
However, PARK states “the memory controller may control the non-volatile memory device in response to a write request or a read request received from the host HOST” (¶[0031]) and “the non-volatile device may include a stack manager … the stack manager may control a program operation and a read operation for a plurality of memory stacks … the program operation may denote a series of operations that cause a memory cell included in a memory cell array to have a certain threshold voltage to write data to the memory cell array, and the read operation may denote an operation of determining data stored in the memory cell array” (¶[0032]) which at least suggests program and read operations may be directed to a particular memory cell.
As such, with the suggestions asserted by PARK, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have taken into consideration PARK’s explicit teachings and suggestions to have been able to modify PARK’s explicit teachings such that host commands specify the location of a particular memory cell in conjunction with a write or read request with a reasonable expectation of success. A motivation for doing so would be to provide a way to identify the particular memory cell onto which an access request is to be performed.
With respect to Claim 9, PARK discloses the system of claim 8.
PARK further discloses wherein the controller is further to: configure a third deck of the plurality of decks for the targeted block in the second program mode in response to the command (¶[0136] – “at least one of the flash memory devices … may program … the memory cells on the upper portion of the plurality of memory stacks using an SLC program or an MLC program, for example.”).
With respect to Claim 10, PARK discloses the system of claim 8.
PARK further discloses wherein the first program mode is a single-level cell mode and wherein the second program mode is a native mode of the 3D NAND media (¶[0136] – “at least one of the flash memory devices … may program the memory cells on the lower portion of the plurality of memory stacks using an SLC program {analogous to ‘a first program mode’}, for example, the memory cells on the middle portion of the plurality of memory stacks using a TLC program {analogous to ‘a second program mode’ and/or ‘a native mode’}, for example …”; ¶[0037] – “the stack manager may program the memory cells in a lower portion of the plurality of memory stacks in 1 bit, the memory cells in a middle portion in 2 bits …”).
With respect to Claim 13, PARK discloses the system of claim 8.
PARK further discloses wherein the controller is further to: configure the first deck of the targeted block and the second deck of the targeted block in accordance with respective voltage setting offsets indicated by the command (¶[0088] – “the stack manager 120 may determine the offset α by applying a plurality of voltages to each of the first memory stack ST1 and the second memory stack ST2”).
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over PARK as applied to Claim 8 above, and further in view of NAMALA.
With respect to Claim 11, PARK discloses the system of claim 8.
PARK may not explicitly disclose wherein the first deck of the targeted block and the second deck of the targeted block are aligned along a pillar of the 3D NAND media.
NAMALA further discloses wherein the first deck of the targeted block and the second deck of the targeted block are aligned along a pillar of the 3D NAND media (¶[0077] – Memory block 500 may include two distinct portions or ‘decks’ 505 and 510. Each deck has one or more data word lines, one or more dummy word lines (DWL), and one or more select gates that formed about a plurality of pillars”).
PARK and NAMALA are analogous art because they are from the same field of endeavor of configuring flash memory. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of PARK and NAMALA before him or her, to organize the storage units of PARK to be coupled to pillars taught by NAMALA. A motivation for doing so would have been to enable program voltages to be applied to targeted memory cells that share a common channel (¶[0054]). Therefore, it would have been obvious to combine PARK and NAMALA to obtain the invention as specified in the instant claims.
With respect to Claim 12, PARK discloses the system of claim 8.
PARK may not explicitly disclose wherein the first deck of the targeted block is to be reserved to store system-specific information.
NAMALA further discloses wherein the first deck of the targeted block is to be reserved to store system-specific information (¶[0025] – “These virtual blocks may be constructed from any number of different salvaged block portions and may store user data, system data, system table information, and the like”).
PARK and NAMALA are analogous art because they are from the same field of endeavor of configuring flash memory. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of PARK and NAMALA before him or her, to organize the storage units of PARK to be allocated to particular types of data as taught by NAMALA. A motivation for doing so would have been to store the types of data in locations less susceptible to certain defect types decreasing the likelihood of data loss (¶[0082]). Therefore, it would have been obvious to combine PARK and NAMALA to obtain the invention as specified in the instant claims.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over PARK as applied to Claim 13 above, and further in view of Applicant Admitted Prior Art (AAPA).
With respect to Claim 14, PARK discloses the system of claim 13.
PARK may not explicitly disclose wherein the command corresponds to a set feature command with a first parameter that indicates an offset profile and a second parameter that indicates an unselected deck status.
However, AAPA discloses wherein the command corresponds to a set feature command with a first parameter that indicates an offset profile and a second parameter that indicates an unselected deck status (Page 12, Lines 7-15 – “a command interface may be implemented by a NAND controller that allows a host to send commands that cause the controller to configure various operational parameters/settings of the NAND memory device … various specifications published at onfi.org describe set features commands”).
PARK and AAPA are analogous art because they are from the same field of endeavor of configuring flash memory. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of PARK and AAPA before him or her, to modify the host requests of PARK to include set features as taught by AAPA. A motivation for doing so would have been to conform to an industry standard command interface enabling compatibility with other systems. Therefore, it would have been obvious to combine PARK and AAPA to obtain the invention as specified in the instant claims.
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over PARK as applied to Claim 18 above, and further in view of Applicant Admitted Prior Art (AAPA).
With respect to Claim 19, PARK discloses the method of claim 18.
PARK may not explicitly disclose determining the offset profile based on a value of a first parameter of the command from the host.
However, AAPA discloses determining the offset profile based on a value of a first parameter of the command from the host (Page 12, Lines 7-15 – “a command interface may be implemented by a NAND controller that allows a host to send commands that cause the controller to configure various operational parameters/settings of the NAND memory device … various specifications published at onfi.org describe set features commands”).
PARK and AAPA are analogous art because they are from the same field of endeavor of configuring flash memory. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of PARK and AAPA before him or her, to modify the host requests of PARK to include set features as taught by AAPA. A motivation for doing so would have been to conform to an industry standard command interface enabling compatibility with other systems. Therefore, it would have been obvious to combine PARK and AAPA to obtain the invention as specified in the instant claims.
With respect to Claim 20, the combination of PARK and AAPA disclose the method of claim 19.
PARK may not explicitly disclose determining a status of an unselected deck based on a value of a second parameter of the command from the host.
However, AAPA discloses determining a status of an unselected deck based on a value of a second parameter of the command from the host (Page 12, Lines 7-15 – “a command interface may be implemented by a NAND controller that allows a host to send commands that cause the controller to configure various operational parameters/settings of the NAND memory device … various specifications published at onfi.org describe set features commands”).
PARK and AAPA are analogous art because they are from the same field of endeavor of configuring flash memory. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of PARK and AAPA before him or her, to modify the host requests of PARK to include set features as taught by AAPA. A motivation for doing so would have been to conform to an industry standard command interface enabling compatibility with other systems. Therefore, it would have been obvious to combine PARK and AAPA to obtain the invention as specified in the instant claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure teach related systems and methods for configuring 3-D flash memory.
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/ERIC T LOONAN/Examiner, Art Unit 2137