DETAILED ACTION
This Office Action, based on application 18/086,315 filed 21 December 2022, is filed responsive to applicant’s amendment and remarks filed 19 May 2026. Claims 1, 2, 6-9, 11, 13-15, and 17-22 are currently pending and have been fully considered below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s remarks, submitted 19 May 2026 in response to the Office Action filed 24 February 2026, have been fully considered below.
Claim Rejections under 35 U.S.C. 102/103
The applicant traverses the rejection to Claims 15-18 (Section I) alleging cited prior art fails to teach or suggest all claim features as amended. While the Office agrees PARK no longer anticipates each feature of the claims, the Office has issued an obviousness rejection in response to applicant’s amendment for reasons now presented below.
Similar to the traversal of Section I, the applicant further traverses the rejections to Claim 1-7 (Section II), Claims 8-10 and 13 (Section III), Claims 11 and 12 (Section IV), Claim 14 (Section V), and Claims 19 and 20 (Section VI) alleging cited prior art fails to teach or suggest all claim features as amended. Applicant’s traversal merely states cited prior art fails to disclose the features without further presenting why cited prior art fails to disclose the features. The Office maintains an obviousness rejection and addresses the amended limitations in the grounds of rejection below.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 2, 6-9, 11, 13, 15, 17, 18, 21, and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over PARK et al (US PGPub 2020/0126621) in further view of NAMALA et al (US PGPub 2022/0066894).
With respect to Claim 1, PARK discloses a memory device, comprising:
NAND media (¶[0036] – “example embodiments include managed memory devices implementing NAND flash memory cells”) with a plurality of decks (Abstract – “A nonvolatile memory device includes a first memory stack including first memory cells vertically stacked on each other, a second memory stack including memory cells vertically stacked on each other” – {a stack layer or portion is commonly referred to as a ‘deck’}); and
circuitry coupled to the NAND media (Fig 2, Control Logic 110) to:
configure the NAND media in a single-level cell (SLC) mode for the first block of the superblock corresponding to the first deck, wherein each memory cell of the first block is configured to store a single bit of first data (¶[0136] – “at least one of the flash memory devices … may program the memory cells on the lower portion of the plurality of memory stacks using an SLC program {analogous to ‘a SLC mode’}, for example, the memory cells on the middle portion of the plurality of memory stacks using a TLC program {analogous to ‘a native mode’}, for example …”; ¶[0037] – “the stack manager may program the memory cells in a lower portion of the plurality of memory stacks in 1 bit, the memory cells in a middle portion in 2 bits …”; ¶[0031] – “the memory controller may control the non-volatile memory device in response to a write request or a read request received from the host HOST”); and
configure the NAND media in a native mode for the second block of the superblock corresponding to the second deck, wherein each memory cell of the second block is configured to store a plurality of bits of second data (¶[0136] – “at least one of the flash memory devices … may program the memory cells on the lower portion of the plurality of memory stacks using an SLC program {analogous to ‘a SLC mode’}, for example, the memory cells on the middle portion of the plurality of memory stacks using a TLC program {analogous to ‘a second program mode’ and/or ‘a native mode’}, for example …”; ¶[0037] – “the stack manager may program the memory cells in a lower portion of the plurality of memory stacks in 1 bit, the memory cells in a middle portion in 2 bits …”; ¶[0031] – “the memory controller may control the non-volatile memory device in response to a write request or a read request received from the host HOST”).
PARK may not explicitly disclose (1) control access to a superblock, wherein the superblock includes at least a first block that corresponds to memory cells aligned along the pillar in a first deck of the plurality of decks and a second block that corresponds to memory cells aligned along the pillar in a second deck of the plurality of decks of memory cells aligned along a pillar of the NAND media, (2) in response to a first command, select the first deck from the plurality of decks to store first data, wherein the first data is system specific information (3) in response to a second command, assign the second deck of the plurality of decks to store second data, wherein the second data is general user data.
However, NAMALA discloses (1) control access to a superblock (Fig 4, Block 402A, 402B), wherein the superblock includes at least a first block (Fig 4, Sub-Block 402A0…402An, 402B0…402Bn; ¶[0068] – “a sub-block may be termed a deck”) that corresponds to memory cells aligned along the pillar in a first deck of the plurality of decks and a second block (Fig 4, Sub-Block 402A0…402An, 402B0…402Bn; ¶[0068] – “a sub-block may be termed a deck”) that corresponds to memory cells aligned along the pillar in a second deck of the plurality of decks of memory cells aligned along a pillar of the NAND media (¶[0077] – Memory block 500 may include two distinct portions or ‘decks’ 505 and 510. Each deck has one or more data word lines, one or more dummy word lines (DWL), and one or more select gates that formed about a plurality of pillars”), (2) in response to a first command, select the first deck from the plurality of decks to store first data, wherein the first data is system specific information (¶[0025] – “These virtual blocks may be constructed from any number of different salvaged block portions and may store user data, system data, system table information, and the like”) (3) in response to a second command, assign the second deck of the plurality of decks to store second data, wherein second data is general user data (¶[0025] – “These virtual blocks may be constructed from any number of different salvaged block portions and may store user data, system data, system table information, and the like”)
PARK and NAMALA are analogous art because they are from the same field of endeavor of configuring flash memory. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of PARK and NAMALA before him or her, to organize the storage units of PARK to be coupled to pillars as taught by NAMALA and to store particular types of data to particular locations in the memory as further taught by NAMALA. A motivation for coupling storage units to pillars would have been to enable program voltages to be applied to targeted memory cells that share a common channel (¶[0054]). A motivation for storing particular data at particular locations in memory would have been to recognize that different decks may operate differently (¶[0082-0083]) such that storing data on one deck versus another deck may experience an access performance tradeoff (e.g. decks where cells are programmed using SLC vs MLC may experience different access times, block/page sizes, endurance, etc – see DELKIN DEVICES white paper); as such, placing data in a particular deck would experience the access performance tradeoff which may be beneficial to that data type (e.g. a user may wish to have certain data stored in locations such that the data may be accessed the fastest). Therefore, it would have been obvious to combine PARK and NAMALA to obtain the invention as specified in the instant claims.
With respect to Claim 8, PARK discloses a system, comprising:
a processor (Fig 1, Memory Controller 20); and
a three-dimensional (3D) memory device (Fig 1, Memory Device 10; ¶[0005] – “A non-volatile memory device may have a 3D memory cell array”) coupled with the processor, wherein the 3D memory device includes 3D NAND media (¶[0038] – “embodiments are described for the case in which the plurality of memory cells include NAND flash memory cells”) with a plurality of decks (Abstract – “A nonvolatile memory device includes a first memory stack including first memory cells vertically stacked on each other, a second memory stack including memory cells vertically stacked on each other” – {a stack layer or portion is commonly referred to as a ‘deck’}), and a controller (Fig 2, Control Logic 110) coupled to the 3D NAND media to:
configure the first deck of the plurality of decks for the targeted block in a single-level cell (SLC) mode, wherein each memory cell of the first deck is configured to store a single bit of the first data (¶[0136] – “at least one of the flash memory devices … may program the memory cells on the lower portion of the plurality of memory stacks using an SLC program {analogous to ‘a SLC mode’}, for example, the memory cells on the middle portion of the plurality of memory stacks using a TLC program {analogous to ‘a native mode’}, for example …”; ¶[0037] – “the stack manager may program the memory cells in a lower portion of the plurality of memory stacks in 1 bit, the memory cells in a middle portion in 2 bits …”; ¶[0031] – “the memory controller may control the non-volatile memory device in response to a write request or a read request received from the host HOST”); and
configure a second deck of the plurality of decks for the targeted block in a native mode, wherein each memory cell of the second deck is configured to store a plurality of bits of the second data (¶[0136] – “at least one of the flash memory devices … may program the memory cells on the lower portion of the plurality of memory stacks using an SLC program {analogous to ‘a SLC mode’}, for example, the memory cells on the middle portion of the plurality of memory stacks using a TLC program {analogous to ‘a native mode’}, for example …”; ¶[0037] – “the stack manager may program the memory cells in a lower portion of the plurality of memory stacks in 1 bit, the memory cells in a middle portion in 2 bits …”; ¶[0031] – “the memory controller may control the non-volatile memory device in response to a write request or a read request received from the host HOST”).
PARK may not explicitly disclose wherein the command indicates the targeted block and the first deck, (1) select the first deck from the plurality of decks to store first data, wherein the first data is system specific information (2) assign a second deck of the plurality of decks to store second data, wherein the second data is general user data.
However, NAMALA discloses (1) selecting a first deck from the plurality of decks to store first data, wherein the first data is system specific information (¶[0025] – “These virtual blocks may be constructed from any number of different salvaged block portions and may store user data, system data, system table information, and the like”), and (2) assign the second deck of the plurality of decks to store second data, wherein the second data is general user data (¶[0025] – “These virtual blocks may be constructed from any number of different salvaged block portions and may store user data, system data, system table information, and the like”)
PARK and NAMALA are analogous art because they are from the same field of endeavor of configuring flash memory. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of PARK and NAMALA before him or her, to organize the storage units of PARK to store particular types of data to particular locations in the memory as further taught by NAMALA. A motivation for storing particular data at particular locations in memory would have been to recognize that different decks may operate differently (¶[0082-0083]) such that storing data on one deck versus another deck may experience an access performance tradeoff (e.g. decks where cells are programmed using SLC vs MLC may experience different access times, block/page sizes, endurance, etc – see DELKIN DEVICES white paper); as such, placing data in a particular deck would experience the access performance tradeoff which may be beneficial to that data type (e.g. a user may wish to have certain data stored in locations such that the data may be accessed the fastest). Therefore, it would have been obvious to combine PARK and NAMALA to obtain the invention as specified in the instant claims.
PARK and NAMALA may not explicitly disclose wherein the command indicates the targeted block and the first deck.
However, PARK states “the memory controller may control the non-volatile memory device in response to a write request or a read request received from the host HOST” (¶[0031]) and “the non-volatile device may include a stack manager … the stack manager may control a program operation and a read operation for a plurality of memory stacks … the program operation may denote a series of operations that cause a memory cell included in a memory cell array to have a certain threshold voltage to write data to the memory cell array, and the read operation may denote an operation of determining data stored in the memory cell array” (¶[0032]) which at least suggests program and read operations may be directed to a particular memory cell.
As such, with the suggestions asserted by PARK, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have taken into consideration PARK’s explicit teachings and suggestions to have been able to modify PARK’s explicit teachings such that host commands specify the location of a particular memory cell in conjunction with a write or read request with a reasonable expectation of success. A motivation for doing so would be to provide a way to identify the particular memory cell onto which an access request is to be performed.
With respect to Claim 15, PARK discloses a method, comprising:
controlling access to three-dimensional (3D) NAND media (Fig 1, Memory Device 10; ¶[0005] – “A non-volatile memory device may have a 3D memory cell array”; ¶[0038] – “embodiments are described for the case in which the plurality of memory cells include NAND flash memory cells”) with a plurality of decks (Abstract – “A nonvolatile memory device includes a first memory stack including first memory cells vertically stacked on each other, a second memory stack including memory cells vertically stacked on each other” – {a stack layer or portion is commonly referred to as a ‘deck’}); and
configuring a targeted block of the 3D NAND media in a hybrid deck single-level cell (SLC) mode in response to a command from a host (¶[0136] – “at least one of the flash memory devices … may program the memory cells on the lower portion of the plurality of memory stacks using an SLC program {analogous to ‘a SLC mode’}, for example, the memory cells on the middle portion of the plurality of memory stacks using a TLC program {a stack layer or portion is commonly referred to as a ‘deck’; since the deck may use a TLC program, the deck is ‘hybrid’}, for example …”; ¶[0037] – “the stack manager may program the memory cells in a lower portion of the plurality of memory stacks in 1 bit, the memory cells in a middle portion in 2 bits …”; ¶[0031] – “the memory controller may control the non-volatile memory device in response to a write request or a read request received from the host HOST”), including:
configuring the first deck of the plurality of decks for the targeted block in an SLC mode, wherein each memory cell of the first deck is configured to store a single bit of the first data (¶[0136] – “at least one of the flash memory devices … may program the memory cells on the lower portion of the plurality of memory stacks using an SLC program {analogous to ‘a SLC mode’}, for example, the memory cells on the middle portion of the plurality of memory stacks using a TLC program {analogous to ‘a native mode’}, for example …”; ¶[0037] – “the stack manager may program the memory cells in a lower portion of the plurality of memory stacks in 1 bit, the memory cells in a middle portion in 2 bits …”; ¶[0031] – “the memory controller may control the non-volatile memory device in response to a write request or a read request received from the host HOST”); and
configuring the second deck of the plurality of decks for the targeted block in a native mode, wherein each memory cell of the second deck is configured to store a plurality of bits of the second data (¶[0136] – “at least one of the flash memory devices … may program the memory cells on the lower portion of the plurality of memory stacks using an SLC program {analogous to ‘a SLC mode’}, for example, the memory cells on the middle portion of the plurality of memory stacks using a TLC program {analogous to ‘a native mode’}, for example …”; ¶[0037] – “the stack manager may program the memory cells in a lower portion of the plurality of memory stacks in 1 bit, the memory cells in a middle portion in 2 bits …”; ¶[0031] – “the memory controller may control the non-volatile memory device in response to a write request or a read request received from the host HOST”).
PARK may not explicitly disclose (1) selecting a first deck from the plurality of decks to store first data, wherein the first data is system specific information (2) assigning a second deck of the plurality of decks to store second data, wherein the second data is general user data.
However, NAMALA discloses (1) selecting a first deck from the plurality of decks to store first data, wherein the first data is system specific information (¶[0025] – “These virtual blocks may be constructed from any number of different salvaged block portions and may store user data, system data, system table information, and the like”), and (2) assign the second deck of the plurality of decks to store second data, wherein the second data is general user data (¶[0025] – “These virtual blocks may be constructed from any number of different salvaged block portions and may store user data, system data, system table information, and the like”)
PARK and NAMALA are analogous art because they are from the same field of endeavor of configuring flash memory. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of PARK and NAMALA before him or her, to organize the storage units of PARK to store particular types of data to particular locations in the memory as further taught by NAMALA. A motivation for storing particular data at particular locations in memory would have been to recognize that different decks may operate differently (¶[0082-0083]) such that storing data on one deck versus another deck may experience an access performance tradeoff (e.g. decks where cells are programmed using SLC vs MLC may experience different access times, block/page sizes, endurance, etc – see DELKIN DEVICES white paper); as such, placing data in a particular deck would experience the access performance tradeoff which may be beneficial to that data type (e.g. a user may wish to have certain data stored in locations such that the data may be accessed the fastest). Therefore, it would have been obvious to combine PARK and NAMALA to obtain the invention as specified in the instant claims.
With respect to Claim 2, the combination of PARK and NAMALA disclose the memory device of claim 1.
PARK further discloses wherein the circuitry is further to: configure the NAND media in the native mode for a third block of the superblock (¶[0136] – “at least one of the flash memory devices … may program … the memory cells on the upper portion of the plurality of memory stacks using an SLC program or an MLC program, for example.”).
NAMALA further discloses wherein the third block corresponds to memory cells aligned along the pillar in a third deck of the plurality of decks (¶[0077] – Memory block 500 may include two distinct portions or ‘decks’ 505 and 510. Each deck has one or more data word lines, one or more dummy word lines (DWL), and one or more select gates that formed about a plurality of pillars … the memory block 500 includes three word lines per deck, 4 pillars per deck, and two decks, but in other examples … more than two decks may be utilized”).
With respect to Claim 6, the combination of PARK and NAMALA disclose the memory device of claim 1.
PARK further discloses wherein the circuitry is further to configure the NAND media in accordance with respective offsets for respective voltage settings for the first and second blocks (¶[0088] – “the stack manager 120 may determine the offset α by applying a plurality of voltages to each of the first memory stack ST1 and the second memory stack ST2”).
With respect to Claim 7, the combination of PARK and NAMALA disclose the memory device of claim 1.
PARK further discloses wherein the NAND media comprises three-dimensional NAND memory cells (¶[0005] – “A non-volatile memory device may have a 3D memory cell array”).
With respect to Claim 9, the combination of PARK and NAMALA disclose the system of claim 8.
PARK further discloses wherein the controller is further to: configure a third deck of the plurality of decks for the targeted block in the native mode in response to the command (¶[0136] – “at least one of the flash memory devices … may program … the memory cells on the upper portion of the plurality of memory stacks using an SLC program or an MLC program, for example.”).
With respect to Claim 11, the combination of PARK and NAMALA disclose the system of claim 8.
NAMALA further discloses wherein the first deck of the targeted block and the second deck of the targeted block are aligned along a pillar of the 3D NAND media (¶[0077] – Memory block 500 may include two distinct portions or ‘decks’ 505 and 510. Each deck has one or more data word lines, one or more dummy word lines (DWL), and one or more select gates that formed about a plurality of pillars”).
With respect to Claim 13, the combination of PARK and NAMALA disclose the system of claim 8.
PARK further discloses wherein the controller is further to: configure the first deck of the targeted block and the second deck of the targeted block in accordance with respective voltage setting offsets indicated by the command (¶[0088] – “the stack manager 120 may determine the offset α by applying a plurality of voltages to each of the first memory stack ST1 and the second memory stack ST2”).
With respect to Claim 17, the combination of PARK and NAMALA disclose the method of claim 15, further comprising: configuring a third deck of the targeted block in the native mode in response to the command from the host (¶[0136] – “at least one of the flash memory devices … may program … the memory cells on the upper portion of the plurality of memory stacks using an SLC program or an MLC program, for example.”).
With respect to Claim 18, the combination of PARK and NAMALA disclose the method of claim 15, further comprising: setting one or more of a pass voltage and a program verify voltage (¶[0048] – “The voltage generator 130 may generate various kinds of voltages for performing the program operation, the read operation, and an erase operation for the memory cell array 140 based on the voltage control signal Ctrl vol. The voltage generator 130 may generate word line voltages VWL, for example, a program voltage (or a write voltage), a read voltage, a pass voltage (or a word line non-selection voltage), a verify voltage, a recovery voltage, etc”) for one or more of the first deck and the second deck in accordance with an offset profile indicated by the command from the host (¶[0088] – “when the memory cells of the second memory stack ST2 have cell characteristics such as a threshold voltage distribution that is shifted by the offset α from cell characteristics of the memory cells of the first memory stack ST1, the offset α may be added to the determined voltage (e.g., V1_4) of an operation performed on the first memory stack ST1. The sum of the offset α and the determined voltage may be applied to the second memory stack ST2”).
With respect to Claim 21, the combination of PARK and NAMALA disclose the memory device of claim 1.
PARK further discloses wherein for each of the plurality of decks, the NAND media is configured in a single respective program mode selected between the SLC mode and the native mode (¶[0136] – “Accordingly, at least one of the flash memory devices (3230, 3240, and 3250) may determine applied voltages for other stacks by using the applied voltage for any one of the plurality of memory stacks. In addition, at least one of the flash memory devices (3230, 3240, 3250) may, in the program operation, perform a program for a memory cell included in a plurality of memory stacks alternately between the plurality of memory stacks, or may program the memory cells on the lower portion of the plurality of memory stacks using an SLC program, for example, the memory cells on the middle portion of the plurality of memory stacks using a TLC program, for example, and the memory cells on the upper portion of the plurality of memory stacks using an SLC program or an MLC program, for example.”).
With respect to Claim 22, the combination of PARK and NAMALA disclose the memory device of claim 1.
PARK further discloses wherein for each of the plurality of decks, all memory cells of the respective deck are configured to store the same number of bits (¶[0136] – “Accordingly, at least one of the flash memory devices (3230, 3240, and 3250) may determine applied voltages for other stacks by using the applied voltage for any one of the plurality of memory stacks. In addition, at least one of the flash memory devices (3230, 3240, 3250) may, in the program operation, perform a program for a memory cell included in a plurality of memory stacks alternately between the plurality of memory stacks, or may program the memory cells on the lower portion of the plurality of memory stacks using an SLC program, for example, the memory cells on the middle portion of the plurality of memory stacks using a TLC program, for example, and the memory cells on the upper portion of the plurality of memory stacks using an SLC program or an MLC program, for example.”).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over PARK and NAMALA as applied to Claim 13 above, and further in view of Applicant Admitted Prior Art (AAPA).
With respect to Claim 14, the combination of PARK and NAMALA disclose the system of claim 13.
PARK and NAMALA may not explicitly disclose wherein the command corresponds to a set feature command with a first parameter that indicates an offset profile and a second parameter that indicates an unselected deck status.
However, AAPA discloses wherein the command corresponds to a set feature command with a first parameter that indicates an offset profile and a second parameter that indicates an unselected deck status (Page 12, Lines 7-15 – “a command interface may be implemented by a NAND controller that allows a host to send commands that cause the controller to configure various operational parameters/settings of the NAND memory device … various specifications published at onfi.org describe set features commands”).
PARK, NAMALA, and AAPA are analogous art because they are from the same field of endeavor of configuring flash memory. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of PARK, NAMALA, and AAPA before him or her, to modify the host requests of the combination of PARK and NAMALA to include set features as taught by AAPA. A motivation for doing so would have been to conform to an industry standard command interface enabling compatibility with other systems. Therefore, it would have been obvious to combine PARK, NAMALA, and AAPA to obtain the invention as specified in the instant claims.
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over PARK and NAMALA as applied to Claim 18 above, and further in view of Applicant Admitted Prior Art (AAPA).
With respect to Claim 19, the combination of PARK and NAMALA disclose the method of claim 18.
PARK and NAMALA may not explicitly disclose determining the offset profile based on a value of a first parameter of the command from the host.
However, AAPA discloses determining the offset profile based on a value of a first parameter of the command from the host (Page 12, Lines 7-15 – “a command interface may be implemented by a NAND controller that allows a host to send commands that cause the controller to configure various operational parameters/settings of the NAND memory device … various specifications published at onfi.org describe set features commands”).
PARK, NAMALA, and AAPA are analogous art because they are from the same field of endeavor of configuring flash memory. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of PARK, NAMALA, and AAPA before him or her, to modify the host requests of the combination of PARK and NAMALA to include set features as taught by AAPA. A motivation for doing so would have been to conform to an industry standard command interface enabling compatibility with other systems. Therefore, it would have been obvious to combine PARK, NAMALA, and AAPA to obtain the invention as specified in the instant claims.
With respect to Claim 20, the combination of PARK, NAMALA, and AAPA disclose the method of claim 19.
AAPA further discloses determining a status of an unselected deck based on a value of a second parameter of the command from the host (Page 12, Lines 7-15 – “a command interface may be implemented by a NAND controller that allows a host to send commands that cause the controller to configure various operational parameters/settings of the NAND memory device … various specifications published at onfi.org describe set features commands”).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T LOONAN whose telephone number is (571)272-6994. The examiner can normally be reached M-F 8am-5pm.
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/ERIC T LOONAN/Examiner, Art Unit 2137
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