Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references cited in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Specification
The use of the term Amazon Web Services, Google Cloud and Microsoft Azure, Fortran, Python, Java, and Bluetooth, which are trade names or marks used in commerce, has been noted in this application. The term should be accompanied by the generic terminology; furthermore the term should be capitalized wherever it appears or, where appropriate, include a proper symbol indicating use in commerce such as ™, SM , or ® following the term.
Although the use of trade names and marks used in commerce (i.e., trademarks, service marks, certification marks, and collective marks) are permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as commercial marks.
Claim Objections
Claims 2, 9, 15-16, and 18 are objected to because of the following informalities:
In claim 2, line 2, “based, at least in part, replacing” should recite “based, at least in part on replacing”.
In claim 9, line 2, “based, at least in part, replacing” should recite “based, at least in part on replacing”.
Claim 15, line 1 recites “the storage location”; however, claim 14 recites “one or more storage locations”. Thus, it is unclear which storage location is being referred to in “the storage location” when there are more than one (e.g., at least one, only one, each, all of the storage locations, etc.).
Claim 16, line 2 recites “the storage location”; however, claim 14 recites “one or more storage locations”. Thus, it is unclear which storage location is being referred to in “the storage location” when there are more than one (e.g., at least one, only one, all of the storage locations, etc.). Additionally, it is unclear if “another storage location” is a different storage location from the “one or more storage locations” of claim 14 or if it is included in the “one or more storage locations”.
Claim 18, line 2 recites “one or more storage locations”. It is unclear if this is referring to the same “one or more storage locations” of claim 14. If they are the same, claim 18 should be amended to recite “the one or more storage locations”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “one or more circuits to perform” in line 1. This limitation identifies an intended use for the “one or more circuits”. Thus, it is unclear if these circuits actually perform the recited functions or if they are merely capable of performing the functions. Accordingly, this renders the metes and bounds of the claims indefinite.
Claim 8 recites “one or more processors to perform” in line 1. This limitation identifies an intended use for the “one or more processors”. Thus, it is unclear if these processors actually perform the recited functions or if they are merely capable of performing the functions. Accordingly, this renders the metes and bounds of the claims indefinite.
Furthermore, claims 1, 8 and 14 recite “perform[/performing] an application programming interface (API) to indicate” in lines 1 and 2. However, an API is an interface (e.g. a library of computing functions of a program that can be invoked by other programs to communicate with the program), and it is not clear what is meant by “perform” an interface; such as to call the interface to invoke a function provided by the interface (e.g. an indication function), or to initialize for execution, or to download the interface, or to generate the interface as part of a development process, etc.
For the following analysis, the Examiner will consider the limitations “perform/performing an application programming interface (API) to indicate” are referring to --perform/performing an application programming interface (API) function to indicate--.
Claims 2-7 depend from claim 1 and therefore inherit the same deficiencies of claim 1. Claims 9-13 depend from claim 8 and therefore inherit the same deficiencies of claim 8. Claims 15-20 depend from claim 14 and therefore inherit the same deficiencies of claim 14.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-7 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1:
The claims are reciting a processor comprising one or more circuits which is a concrete thing consisting of parts, or of certain devices and combination of devices, and therefore are directed to a machine, which is one of the four statutory categories.
Step 2A, Prong One:
Claim 1 recites the limitation indicate one or more storage locations of information to be mapped from a first tensor to a second tensor which can be performed in the human mind through observation, judgement, evaluation and opinion, with the aid of pen and paper, and is therefore reciting an abstract idea (i.e., a mental process).
Step 2A, Prong Two:
The judicial exception is not integrated into a practical application because the additional claim limitations only recite mere instructions to apply the exception.
The additional element of A processor comprising: one or more circuits to perform an application programming interface (API) to is reciting generic computing components, e.g. hardware and software, to implement the judicial exception. As such, the additional element amounts to no more than mere instructions to apply the judicial exception on a computer.
Mere instructions to apply the exception are not indicative of integration into a practical application (see MPEP 2106.04(d)); accordingly, the claim is directed to the judicial exception.
Step 2B:
As explained with respect to Step 2A, Prong Two, the additional element amounts to no more than mere instructions to apply the exception, as it is merely reciting generic computing components to perform the exception. Accordingly, the additional element does not amount to significantly more than the recited judicial exception (see MPEP 2106.05(f)), and does not provide an inventive concept. Thus, claim 1 in ineligible.
Claim 2 is dependent on claim 1, and therefore inherits the same judicial exception recited in claim 1. Claim 2 further recites indicate the one or more storage locations based, at least in part, replacing an indication of a first memory location with an indication of a second memory location which can be performed in the human mind through observation, judgement, evaluation and opinion, with the aid of pen and paper, and is therefore reciting an abstract idea (i.e., a mental process).
Claim 2 recites the additional element wherein the one or more circuits are to perform the API to which amounts to mere instructions to apply the exception for the same reasons presented with respect to claim 1. This additional element of mere instructions to apply the exception, when considered alone and in combination with the additional element recited in claim 1, is not indicative of integration into a practical application.
Further, this additional element of mere instructions to apply the exception does not amount to significantly more than the recited judicial exception. Even when considered in combination with the additional element recited in claim 1, these additional elements represent mere instructions to apply the exceptions, and therefore do not provide an inventive concept. Accordingly, claim 2 is not eligible.
Claim 3 is dependent on claim 1, and therefore inherits the same judicial exception recited in claim 1. Claim 3 further recites modify a data structure that indicates a mapping of the first tensor to the second tensor which can be performed in the human mind through observation, judgement, evaluation and opinion, with the aid of pen and paper, and is therefore reciting an abstract idea (i.e., a mental process).
Claim 3 recites the additional element wherein the API is to which amounts to mere instructions to apply the exception for the same reasons presented with respect to claim 1. This additional element of mere instructions to apply the exception, when considered alone and in combination with the additional element recited in claim 1, is not indicative of integration into a practical application.
Further, this additional element of mere instructions to apply the exception does not amount to significantly more than the recited judicial exception. Even when considered in combination with the additional element recited in claim 1, these additional elements represent mere instructions to apply the exceptions, and therefore do not provide an inventive concept. Accordingly, claim 3 is not eligible.
Claim 4 is dependent on claim 1, and therefore inherits the same judicial exception recited in claim 1. Claim 4 further recites update a mapping of a third tensor to the second tensor to a mapping of the first tensor to the second tensor which can be performed in the human mind through observation, judgement, evaluation and opinion, with the aid of pen and paper, and is therefore reciting an abstract idea (i.e., a mental process).
Claim 4 recites the additional element wherein the API is to which amounts to mere instructions to apply the exception for the same reasons presented with respect to claim 1. This additional element of mere instructions to apply the exception, when considered alone and in combination with the additional element recited in claim 1, is not indicative of integration into a practical application.
Further, this additional element of mere instructions to apply the exception does not amount to significantly more than the recited judicial exception. Even when considered in combination with the additional element recited in claim 1, these additional elements represent mere instructions to apply the exceptions, and therefore do not provide an inventive concept. Accordingly, claim 4 is not eligible.
Claim 5 is dependent on claim 1, and therefore inherits the same judicial exception recited in claim 1. Claim 5 further recites reuse a mapping with a different set of tensors which can be performed in the human mind through observation, judgement, evaluation and opinion, with the aid of pen and paper, and is therefore reciting an abstract idea (i.e., a mental process).
Claim 5 recites the additional element wherein the API is to which amounts to mere instructions to apply the exception for the same reasons presented with respect to claim 1. This additional element of mere instructions to apply the exception, when considered alone and in combination with the additional element recited in claim 1, is not indicative of integration into a practical application.
Further, this additional element of mere instructions to apply the exception does not amount to significantly more than the recited judicial exception. Even when considered in combination with the additional element recited in claim 1, these additional elements represent mere instructions to apply the exceptions, and therefore do not provide an inventive concept. Accordingly, claim 5 is not eligible.
Claim 6 is dependent on claim 1, and therefore inherits the same judicial exception recited in claim 1. The judicial exception recited in claim 1 is not integrated into a practical application because the additional elements recited only represent mere instructions to apply the exception.
Claim 6 recites the additional element wherein the API is to receive as input an indication of a
storage location in which a mapping between tensors is stored which is insignificant extra-solution activity of mere data gathering. This additional element of insignificant extra-solution activity, when considered alone and in combination with the additional element recited in claim 1, is not indicative of integration into a practical application.
This additional element of insignificant extra-solution activity does not amount to significantly more than the recited judicial exception. Even when considered in combination with the additional element recited in claim 1, these additional elements represent mere instructions to apply the exception and insignificant extra-solution activity, and therefore do not provide an inventive concept. Accordingly, claim 6 is not eligible.
Claim 7 is dependent on claim 1, and therefore inherits the same judicial exception recited in claim 1. Claim 7 further recites replace a first memory address with a second memory address in a data structure which can be performed in the human mind through observation, judgement, evaluation and opinion, with the aid of pen and paper, and is therefore reciting an abstract idea (i.e., a mental process).
Claim 7 recites the additional element wherein the API is to which amounts to mere instructions to apply the exception for the same reasons presented with respect to claim 1. This additional element of mere instructions to apply the exception, when considered alone and in combination with the additional element recited in claim 1, is not indicative of integration into a practical application.
Further, this additional element of mere instructions to apply the exception does not amount to significantly more than the recited judicial exception. Even when considered in combination with the additional element recited in claim 1, these additional elements represent mere instructions to apply the exceptions, and therefore do not provide an inventive concept. Accordingly, claim 7 is not eligible.
Claims 8-13 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claims 8-9 and 11 are directed to A system, comprising: one or more processors to perform an application programming interface (API) to perform the functions performed by the processor of claim 1-2 and 4. As such, in view of the abovementioned reasons presented with respect to claim 1-2 and 4, claims 8-9 and 11 are also directed to a judicial exception without significantly more and is ineligible.
For clarity, the additional element of claim 8 recited above is considered to be mere instructions to apply the exception, which is not indicative of integration into a practical application nor does it amount to significantly more than the judicial exception.
Claim 10 is dependent on claim 8, and therefore inherits the same judicial exception recited in claim 8. Claim 10 further recites update a data structure to replace a first memory address of a third tensor with a memory address of the first tensor which can be performed in the human mind through observation, judgement, evaluation and opinion, with the aid of pen and paper, and is therefore reciting an abstract idea (i.e., a mental process).
Claim 10 recites the additional element wherein the API is to which amounts to mere instructions to apply the exception for the same reasons presented with respect to claim 8. This additional element of mere instructions to apply the exception, when considered alone and in combination with the additional element recited in claim 8, is not indicative of integration into a practical application.
Further, this additional element of mere instructions to apply the exception does not amount to significantly more than the recited judicial exception. Even when considered in combination with the additional element recited in claim 8, these additional elements represent mere instructions to apply the exceptions, and therefore do not provide an inventive concept. Accordingly, claim 10 is not eligible.
Claim 12 is dependent on claim 8, and therefore inherits the same judicial exception recited in claim 8. Claim 12 further recites reuse a tensor map with at least one different tensor which can be performed in the human mind through observation, judgement, evaluation and opinion, with the aid of pen and paper, and is therefore reciting an abstract idea (i.e., a mental process).
Claim 12 recites the additional element wherein the API is to which amounts to mere instructions to apply the exception for the same reasons presented with respect to claim 8. This additional element of mere instructions to apply the exception, when considered alone and in combination with the additional element recited in claim 8, is not indicative of integration into a practical application.
Further, this additional element of mere instructions to apply the exception does not amount to significantly more than the recited judicial exception. Even when considered in combination with the additional element recited in claim 8, these additional elements represent mere instructions to apply the exceptions, and therefore do not provide an inventive concept. Accordingly, claim 12 is not eligible.
Claim 13 is dependent on claim 8, and therefore inherits the same judicial exception recited in claim 8. Claim 13 further recites indicate a memory location of a mapping to be updated which can be performed in the human mind through observation, judgement, evaluation and opinion, with the aid of pen and paper, and is therefore reciting an abstract idea (i.e., a mental process).
Claim 13 recites the additional element wherein the API is to which amounts to mere instructions to apply the exception for the same reasons presented with respect to claim 8. This additional element of mere instructions to apply the exception, when considered alone and in combination with the additional element recited in claim 8, is not indicative of integration into a practical application.
Further, this additional element of mere instructions to apply the exception does not amount to significantly more than the recited judicial exception. Even when considered in combination with the additional element recited in claim 8, these additional elements represent mere instructions to apply the exceptions, and therefore do not provide an inventive concept. Accordingly, claim 13 is not eligible.
Claims 14-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 14 is directed to A method, comprising: performing an application programming interface (API) to perform the functions performed by the processor of claim 1. As such, in view of the abovementioned reasons presented with respect to claim 1, claim 14 is also directed to a judicial exception without significantly more and is ineligible.
For clarity, the additional element of claim 14 recited above is considered to be mere instructions to apply the exception, which is not indicative of integration into a practical application nor does it amount to significantly more than the judicial exception.
Claim 15 is dependent on claim 14, and therefore inherits the same judicial exception recited in claim 14. The judicial exception recited in claim 14 is not integrated into a practical application because the additional elements recited only represent mere instructions to apply the exception.
Claim 15 recites the additional element wherein the storage location corresponds to a tensor which amounts to generally linking the use of the exception to a particular technological environment. This additional element of generally linking the use of the exception to a particular technological environment, when considered alone and in combination with the additional element recited in claim 14, is not indicative of integration into a practical application.
Further, this additional element of generally linking the use of the exception to a particular technological environment does not amount to significantly more than the recited judicial exception. Even when considered in combination with the additional element recited in claim 14, these additional elements represent mere instructions to apply the exception and generally linking the use of the exception to a particular technological environment, and therefore do not provide an inventive concept. Accordingly, claim 15 is not eligible.
Claim 16 is dependent on claim 14, and therefore inherits the same judicial exception recited in claim 14. Claim 16 further recites replace an indication of another storage location with an indication of the storage location which can be performed in the human mind through observation, judgement, evaluation and opinion, with the aid of pen and paper, and is therefore reciting an abstract idea (i.e., a mental process).
Claim 16 recites the additional element wherein the API is to which amounts to mere instructions to apply the exception for the same reasons presented with respect to claim 14. This additional element of mere instructions to apply the exception, when considered alone and in combination with the additional element recited in claim 14, is not indicative of integration into a practical application.
Further, this additional element of mere instructions to apply the exception does not amount to significantly more than the recited judicial exception. Even when considered in combination with the additional element recited in claim 14, these additional elements represent mere instructions to apply the exceptions, and therefore do not provide an inventive concept. Accordingly, claim 16 is not eligible.
Claim 17 is dependent on claim 14, and therefore inherits the same judicial exception recited in claim 14. Claim 17 further recites updating a tensor map which can be performed in the human mind through observation, judgement, evaluation and opinion, with the aid of pen and paper, and is therefore reciting an abstract idea (i.e., a mental process).
Claim 17 recites the additional element wherein performing the API comprises which amounts to mere instructions to apply the exception for the same reasons presented with respect to claim 14. This additional element of mere instructions to apply the exception, when considered alone and in combination with the additional element recited in claim 14, is not indicative of integration into a practical application.
Further, this additional element of mere instructions to apply the exception does not amount to significantly more than the recited judicial exception. Even when considered in combination with the additional element recited in claim 14, these additional elements represent mere instructions to apply the exceptions, and therefore do not provide an inventive concept. Accordingly, claim 17 is not eligible.
Claim 18 is dependent on claim 14, and therefore inherits the same judicial exception recited in claim 14. Claim 18 further recites replacing one or more indications of one or more storage locations which can be performed in the human mind through observation, judgement, evaluation and opinion, with the aid of pen and paper, and is therefore reciting an abstract idea (i.e., a mental process).
Claim 18 recites the additional element wherein performing the API comprises which amounts to mere instructions to apply the exception for the same reasons presented with respect to claim 14. This additional element of mere instructions to apply the exception, when considered alone and in combination with the additional element recited in claim 14, is not indicative of integration into a practical application.
Further, this additional element of mere instructions to apply the exception does not amount to significantly more than the recited judicial exception. Even when considered in combination with the additional element recited in claim 14, these additional elements represent mere instructions to apply the exceptions, and therefore do not provide an inventive concept. Accordingly, claim 18 is not eligible.
Claim 19 is dependent on claim 14, and therefore inherits the same judicial exception recited in claim 14. Claim 19 further recites updating a data structure that stores information indicating how to transform the first tensor to obtain the second tensor which can be performed in the human mind through observation, judgement, evaluation and opinion, with the aid of pen and paper, and is therefore reciting an abstract idea (i.e., a mental process).
Claim 19 recites the additional element wherein performing the API comprises which amounts to mere instructions to apply the exception for the same reasons presented with respect to claim 14. This additional element of mere instructions to apply the exception, when considered alone and in combination with the additional element recited in claim 14, is not indicative of integration into a practical application.
Further, this additional element of mere instructions to apply the exception does not amount to significantly more than the recited judicial exception. Even when considered in combination with the additional element recited in claim 14, these additional elements represent mere instructions to apply the exceptions, and therefore do not provide an inventive concept. Accordingly, claim 19 is not eligible.
Claim 20 is dependent on claim 14, and therefore inherits the same judicial exception recited in claim 14. The judicial exception recited in claim 14 is not integrated into a practical application because the additional elements recited only represent mere instructions to apply the exception.
Claim 20 recites the additional element A non-transitory computer-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to at least perform the method of claim 14 which amounts to mere instructions to apply the exception. This additional element of mere instructions to apply the exception, when considered alone and in combination with the additional element recited in claim 14, is not indicative of integration into a practical application.
Further, this additional element of mere instructions to apply the exception does not amount to significantly more than the recited judicial exception. Even when considered in combination with the additional element recited in claim 14, these additional elements represent mere instructions to apply the exceptions, and therefore do not provide an inventive concept. Accordingly, claim 20 is not eligible.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (U.S. Pub. No. 2021/0117806), hereinafter Liu, in view of Yu et al. (U.S. Patent No. 11,494,321), hereinafter Yu.
Regarding claim 1, Liu teaches A processor, comprising: one or more circuits to (FIG 4C; [0100] – “a processor 432 that includes a program 434. The program includes tensor manipulation instructions. When executed, the program 434 requests tensor manipulation instruction circuits 436 to perform the requested tensor manipulation instructions. The tensor manipulation instructions include one or more of instructions for manipulating generic tensor raw data 306 and/or instructions for manipulating generic tensor descriptors 308.”; [0124] – “Suitable processors include, by way of example […] Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) circuits, any other type of integrated circuit (IC)”) perform an application programming interface (API) ([0026] – “The individual operations are, in various implementations, performed by any of the following entities: […] hardware that performs the operations in response to an invocation such as an API call”; [0093] – “the operations are API functions that can be called by software. In some implementations, the operations are operations performed by a compiler at compile-time. In some implementations, the operations that act on the generic tensor descriptor are compile-time operations and the operations that act on the data itself are runtime operations. In various implementations, any of the operations are implemented as hardware instructions as part of an instruction set architecture or that is invoked in any technically feasible manner.”) […] one or more storage locations of information ([0027] – “Some operations are operations that act not on the generic tensor raw data, itself, but instead on the generic tensor descriptor.”; [0030] – “A generic tensor is described both by a generic tensor descriptor and generic tensor raw data. A generic tensor descriptor indicates the number of dimensions of the generic tensor, the lengths for each dimension, and a base address for the generic tensor raw data that the generic tensor descriptor is associated with. In addition, a generic tensor descriptor also provides a means to calculate the memory "offset" of a tensor raw data that is associated with a multi-index. Thus, a generic tensor descriptor indicates the manner in which a multi-index maps to generic tensor raw data as stored in memory. The generic tensor descriptor facilitates proper mapping of elements of a multi-index to elements of generic tensor raw data. […] With a generic tensor stored in memory, the point of origin corresponds to the base address of the generic tensor.”; [0033] – “The function g: X[Symbol font/0xAE]Y is referred to as the “address function” of the generic tensor T. The “generic tensor descriptor” of T is the implementation of the address function g: X[Symbol font/0xAE]Y. The address function maps the set of all tensor coordinates of a generic tensor T to the set of all memory addresses associated with the generic tensor T.” Operations performed in response to an API call may act on a generic tensor descriptor which includes a base address of the tensor raw data of a tensor (one storage location of information) and implements an address function which maps the tensor to the memory addresses (more storage locations) of the tensor raw data. [0094] – “The in-program tensor manipulator 404 or the tensor manipulator 406 external to the program 403 manipulate the generic tensor raw data 306 and generic tensor descriptor 308 according to the operations for manipulating the generic tensor raw data and the generic tensor descriptor described elsewhere herein.”; [0120] – “a tensor manipulator requestor 302 transmits a request to manipulate a generic tensor descriptor to a tensor manipulator 304. […] the tensor manipulator 304 performs the requested operation to manipulate the generic tensor descriptor.” The generic tensor descriptor, including the base address of the tensor raw data, on which to perform the manipulation/operation would necessarily be “indicated” to the tensor manipulator 404 or 406 to perform the operation.) to be mapped from a first tensor to a second tensor ([0027] – “Some operations are operations that act not on the generic tensor raw data, itself, but instead on the generic tensor descriptor. Such operations include the following: slice, strided slice, reorder, unfold, merge, embed, pad, and move slicing window. As an example of these operations, the slice operator "slices out" a given portion of a tensor to make a new generic tensor descriptor. Specifically, a slice modifies a generic tensor descriptor by limiting the possible index values in one or more dimensions, but the slice does not operate on the tensor raw data. The range of possible indices index to which indexing is limited in the sliced tensor is called a "slicing window." The number of possible index values in the given dimension is called the "length of a slicing window" in that dimension. In the above example, one example slice limits the possible index values in the z dimension to 0 through 3 ( out of 0 through 7). A different example slice limits the possible index values in the x dimension to 0 and in the y dimension to 0 and 1.”; [0038]-[0039] – “B is a generic tensor descriptor that maps tensor coordinate space W to memory space Y. More specifically, generic tensor descriptor B can be thought of as being constructed using generic tensor descriptor A, which maps coordinate space X to memory address space Y as g: X[Symbol font/0xAE]Y, and the function ƒ: W[Symbol font/0xAE]X that maps coordinate space W to X. The function g: X[Symbol font/0xAE]Y is the address function associated with the generic tensor descriptor A. The function (gοƒ): W[Symbol font/0xAE]Y is the address function associated with generic tensor descriptor B. The function ƒ: W[Symbol font/0xAE] X is referred to as a “transformation function” here, which transforms generic tensor descriptor A into B.”; [0080] – “A reorder (also called "permute") transformation operation changes the order of the dimensions of a generic tensor descriptor. […] A reorder operation creates a new generic tensor "TensorB" with a new order of dimensions, where, for example, z, y, and x are its first, second and third dimension. TensorB has lengths of Lz, Ly, and Lx, and strides of Sz, Sy, Sx on its first, second, and third dimension. "TensorA" and "TensorB" share the same tensor raw data in memory. An element of TensorA with multi-index of (Ix, Iy, Iz) has the same memory address as the element of TensorB with multi-index of (Iz, Iy, Ix).” Performing an operation on the generic tensor descriptor, e.g. slice or reorder, results in the tensor raw data (“information”) of a first tensor represented by the original generic tensor descriptor, being mapped to a second tensor according to the transformed/manipulated generic tensor descriptor.).
Liu fails to explicitly teach the API is to indicate the one or more storage locations.
However, Yu teaches an API to indicate one or more storage locations of information to be mapped from a first tensor to a second tensor (Col. 18, lines 1-32 – “Driver 422 can provide an interface between applications executing on host system 400 (or on another host system) and acceleration engine 412. For example, driver 422 can provide an Application Program Interface (API) that defines functions for feeding input data to acceleration engine 412 and defining the operation to perform on the input data. In this and other examples, driver 422 can configure acceleration engine 412 to perform the operation. For example, driver 422 can identify a neural network that acceleration engine 412 is to execute, as well as the location in processor memory 404 or on storage device 406 where compiled code 444 for the neural network is located. Driver 422 can further load into acceleration engine 412 or cause acceleration engine 412 to load compiled code 444, can load or cause acceleration engine 412 to load the input data on which the neural network is to operate, and/or can cause acceleration engine 412 to being executing on the input data. Once acceleration engine 412 has finished, acceleration engine 412 can notify driver 422, and driver 422 can deliver a result back to the application that requested the result. Data transfers between the local memory of a neural network processor and the system memory, including loading input tensors from the system memory to the local memory and saving intermediate output tensors from the local memory to the system memory to make room for other input tensors for other operations may be performed using a direct memory access (DMA) engine, in order to limit the involvement of the host processor. A DMA engine may use memory descriptors to perform the data transfers.”; Col. 17, lines 15-18 – “the processor 402, through the execution of a driver 422, may need to perform steps such as configuring DMA descriptors for moving data into or out of the acceleration engine 412”; Col. 19, lines 29-38 – “a set of memory descriptors used by DMA engine 550 to exchange data between system memory 520 and other components of computing system 500. For example, when an accelerator 502-m has data to store in system memory 520 or is requesting data from system memory 520, a memory descriptor providing a source address and a destination address can be placed in descriptor queue 560 to initiate the transfer. A memory descriptor may also include other information, such as the number of elements to transfer, data size, transfer unit, transfer type”. Via the API provided by a driver, applications, such as those executing on processor 402, are able to indicate input data to load and operations to perform on the input data to the driver/acceleration engine which performs the operations. E.g., through the driver API, a processor configures DMA descriptors, which indicate a source address (of a first tensor stored in system memory to be to be mapped to a destination address in local memory where it may be stored as a second tensor) such that input data may be loaded.).
Liu and Yu are considered to be analogous art to the claimed invention because they are in the same field of processing resources that perform an API to cause operations on tensors. Yu teaches an API provided by a driver controlling an acceleration engine allows applications to indicate input data to be loaded and operations to be executed on the input data (Yu: Col. 18, lines 1-32). Liu similarly teaches an API may be provided by a driver controlling an accelerated processing device to applications executing on a processor to access functionality of the accelerated processing device (Liu: [0018]). Therefore, it would have been obvious to one of ordinary skill in the art that the API calls of Liu, which cause operations that transform a first tensor to a second tensor to be performed on a generic tensor descriptor, would necessarily “indicate” the generic tensor descriptor to be operated on (and in indicating the descriptor, would also indicate the base address of the tensor raw data included in the descriptor) as evidenced by Yu. Further, the teachings of YU improve the overall performance of a computing system for implementing a neural network model (Yu: Col. 2, lines 13-14).
Regarding claim 2, the combination of Liu in view of Yu teaches the processor of claim 1. Liu teaches wherein the one or more circuits (FIG. 4C, [0100], and [0124]) are to perform the API to indicate the one or more storage locations (see portions of [0026]-[0027], [0030], [0033], [0093]-[0094], and [0120] cited in claim 1) based on operations performed by a compiler (see [0018] and [0093]).
Yu further teaches based, at least in part, replacing an indication of a first memory location with an indication of a second memory location (Col. 22, lines 30-37 – “The compiler may also replace a DMA load instruction for reloading the tensor with a tensor copy instruction that may be executed to read the (reshaped) tensor in the candidate region, change the dimensions of the (reshaped) tensor according to the dimensions of the destination of the DMA load instruction, and save the tensor (e.g., in its original dimensions) to the destination of the DMA load instruction.”; Col. 31, lines 47-50 – “first DMA load instruction may be used to load the tensor from the location of the system memory to a second region of the local memory (i.e., the destination of the second DMA load instruction)”. The first DMA instruction maps the location of system memory (“a first memory location”) where tensor data (a third tensor) is stored to the second region of the local memory where the tensor data (a second tensor) is to be stored. Col. 2, lines 47-48 – “the local memory (also referred to as a state buffer”; Col. 32, lines 46-55 – “At block 1050, the host system may replace the first DMA load instruction in the instruction code with a second tensor copy instruction for saving data in the selected local memory block to a destination of the first DMA load instruction. For example, the second tensor copy instruction may be executed to read the reshaped tensor from the selected local memory block, change the reshaped tensor to the tensor in its original dimensions or in different dimensions matching the second region of the state buffer, and save the tensor to the second region of state buffer.” The second tensor copy instruction maps a selected local memory block (“a second memory location”) storing reshaped tensor data (a first tensor) to the second region of the state buffer, i.e., local memory, where the tensor data (the second tensor) is to be stored. The second tensor copy instruction replaces the first DMA instruction, i.e., the mapping of the first tensor to the second tensor is replaces the mapping of the third tensor to the second tensor, and thus the indication of the second memory location replaces the indication of the first memory location.).
It would have been obvious to one of ordinary skill in the art to have modified the teachings of Liu to incorporate the teachings of Yu. Replacing some DMA load instructions that indicate a source location of a tensor in system memory with tensor copy instructions indicating a source location of a reshaped tensor in a state buffer reduces the overhead and results in a faster processing speed, lower latency, and high throughput (Yu: Col. 4, lines 25-37, and Col. 20, lines 24-32).
Regarding claim 3, the combination of Liu in view of Yu teaches the processor of claim 1. Liu teaches wherein the API is to modify a data structure ([0027] – “Some operations are operations that act not on the generic tensor raw data, itself, but instead on the generic tensor descriptor. Such operations include the following: slice, […] Specifically, a slice modifies a generic tensor descriptor”; [0101] – “the generic tensor descriptors are stored at any appropriate location such as a memory”; [0120] – “The generic tensor descriptor is a construct that indicates how to obtain data elements of generic tensor raw data given an input multi-index.”) that indicates a mapping of the first tensor to the second tensor ([0038]-[0039] – “B is a generic tensor descriptor that maps tensor coordinate space W to memory space Y. More specifically, generic tensor descriptor B can be thought of as being constructed using generic tensor descriptor A, which maps coordinate space X to memory address space Y as g: X[Symbol font/0xAE]Y, and the function ƒ: W[Symbol font/0xAE]X that maps coordinate space W to X. The function g: X[Symbol font/0xAE]Y is the address function associated with the generic tensor descriptor A. The function (gοƒ): W[Symbol font/0xAE]Y is the address function associated with generic tensor descriptor B. The function ƒ: W[Symbol font/0xAE] X is referred to as a “transformation function” here, which transforms generic tensor descriptor A into B.”; [0047] – “any number of transformation functions can be chained an applied to an existing generic tensor descriptor to construct a series of new generic tensor descriptors. […] Since a generic tensor can be defined using tensor raw data and an address function, a series of generic tensors T1, …, Tk can be defined by combining these transformation functions with the address function
g
:
→
x
0
→
y
for T0.” The original tensor descriptor A (a data structure which includes an address function mapping from the coordinate space original tensor A to the memory addresses of tensor raw data) is modified to indicate an address function for the generic tensor B, which is the original address function combined with a transformation function f (a mapping of a first tensor A to a second tensor B).).
Regarding claim 4, the combination of Liu in view of Yu teaches the processor of claim 1. Liu teaches wherein the API is to cause operations performed by a compiler (see [0018] and [0093]).
Yu teaches operations performed by a compiler to update a mapping of a third tensor to the second tensor to a mapping of the first tensor to the second tensor (Col. 22, lines 30-37 – “The compiler may also replace a DMA load instruction for reloading the tensor with a tensor copy instruction that may be executed to read the (reshaped) tensor in the candidate region, change the dimensions of the (reshaped) tensor according to the dimensions of the destination of the DMA load instruction, and save the tensor (e.g., in its original dimensions) to the destination of the DMA load instruction.”; Col. 31, lines 47-50 – “first DMA load instruction may be used to load the tensor from the location of the system memory to a second region of the local memory (i.e., the destination of the second DMA load instruction)”. The first DMA instruction maps the location of system memory where tensor data (a third tensor) is stored to the second region of the local memory where the tensor data (a second tensor) is to be stored. Col. 2, lines 47-48 – “the local memory (also referred to as a state buffer”; Col. 32, lines 46-55 – “At block 1050, the host system may replace the first DMA load instruction in the instruction code with a second tensor copy instruction for saving data in the selected local memory block to a destination of the first DMA load instruction. For example, the second tensor copy instruction may be executed to read the reshaped tensor from the selected local memory block, change the reshaped tensor to the tensor in its original dimensions or in different dimensions matching the second region of the state buffer, and save the tensor to the second region of state buffer.” The second tensor copy instruction maps a selected local memory block storing reshaped tensor data (a first tensor) to the second region of the state buffer, i.e., local memory, where the tensor data (the second tensor) is to be stored. The second tensor copy instruction replaces the first DMA instruction, i.e., the mapping of the first tensor to the second tensor replaces the mapping of the third tensor to the second tensor is replaced.).
It would have been obvious to one of ordinary skill in the art to have modified the teachings of Liu to incorporate the teachings of Yu. Replacing some DMA load instructions, which map a source location of a third tensor in system memory to a destination location in a state buffer for a second tensor, with tensor copy instructions, which map a source location of a first reshaped tensor in the state buffer to the destination location in the state buffer for the second tensor, reduces the overhead and results in a faster processing speed, lower latency, and high throughput (Yu: Col. 4, lines 25-37, and Col. 20, lines 24-32).
Regarding claim 5, the combination of Liu in view of Yu teaches the processor of claim 1. Liu teaches wherein the API is to reuse a mapping with a different set of tensors ([0033] – “The address function maps the set of all tensor coordinates of a generic tensor T to the set of all memory addresses associated with the generic tensor T.”; [0047] – “any number of transformation functions can be chained an applied to an existing generic tensor descriptor to construct a series of new generic tensor descriptors. […] Since a generic tensor can be defined using tensor raw data and an address function, a series of generic tensors T1, …, Tk can be defined by combining these transformation functions with the address function
g
:
→
x
0
→
y
for T0.” The address function (a mapping) of the original generic tensor descriptor is reused in defining any number of new tensors by combining the address function with any number of transformation functions.).
Regarding claim 6, the combination of Liu in view of Yu teaches the processor of claim 1. Liu teaches a storage location in which a mapping between tensors is stored ([0027] – “Some operations are operations that act not on the generic tensor raw data, itself, but instead on the generic tensor descriptor. […]. Specifically, a slice modifies a generic tensor descriptor”; [0030] – “a generic tensor descriptor indicates the manner in which a multi-index maps to generic tensor raw data as stored in memory. The generic tensor descriptor facilitates proper mapping of elements of a multi-index to elements of generic tensor raw data.”; [0033] – “The “generic tensor descriptor” is the implementation of the address function g: X[Symbol font/0xAE]Y. The address function maps the set of all tensor coordinates of a generic tensor T to the set of all memory addresses associated with the generic tensor T.”; [0039] – “The function ƒ: W[Symbol font/0xAE] X is referred to as a “transformation function” here, which transforms generic tensor descriptor A into B.”; [0047] – “any number of transformation functions can be chained an applied to an existing generic tensor descriptor to construct a series of new generic tensor descriptors. […] Since a generic tensor can be defined using tensor raw data and an address function, a series of generic tensors T1, …, Tk can be defined by combining these transformation functions with the address function
g
:
→
x
0
→
y
for T0.” [0101] – “the generic tensor descriptors are stored at any appropriate location such as a memory”).
Yu teaches wherein the API is to receive as input an indication of a storage location (Col. 18, lines 1-32 – “Driver 422 can provide an interface between applications executing on host system 400 (or on another host system) and acceleration engine 412. For example, driver 422 can provide an Application Program Interface (API) that defines functions for feeding input data to acceleration engine 412 and defining the operation to perform on the input data. In this and other examples, driver 422 can configure acceleration engine 412 to perform the operation. For example, driver 422 can identify a neural network that acceleration engine 412 is to execute, as well as the location in processor memory 404 or on storage device 406 where compiled code 444 for the neural network is located. Driver 422 can further load into acceleration engine 412 or cause acceleration engine 412 to load compiled code 444, can load or cause acceleration engine 412 to load the input data on which the neural network is to operate, and/or can cause acceleration engine 412 to being executing on the input data. […] Data transfers between the local memory of a neural network processor and the system memory, including loading input tensors from the system memory to the local memory and saving intermediate output tensors from the local memory to the system memory to make room for other input tensors for other operations may be performed using a direct memory access (DMA) engine, in order to limit the involvement of the host processor. A DMA engine may use memory descriptors to perform the data transfers.”; Col. 25, lines 8-11 – “the compiled instruction code may include an instruction load[0] ( e.g., a DMA load instruction) for loading the tensor into region SB1 of the state buffer,”; Col. 17, lines 15-18 – “the processor 402, through the execution of a driver 422, may need to perform steps such as configuring DMA descriptors for moving data into or out of the acceleration engine 412”; Col. 19, lines 29-38 – “a set of memory descriptors used by DMA engine 550 to exchange data between system memory 520 and other components of computing system 500. For example, when an accelerator 502-m has data to store in system memory 520 or is requesting data from system memory 520, a memory descriptor providing a source address and a destination address can be placed in descriptor queue 560 to initiate the transfer. A memory descriptor may also include other information, such as the number of elements to transfer, data size, transfer unit, transfer type”. The API of the driver defines functions for feeding input data to acceleration engine, where input data may be fed to acceleration engine via DMA load operations in compiled code which use memory descriptors comprising a mapping of memory addresses (indication of a storage location), where the memory descriptors were configured by the processor 402, using the driver 422. Thus, the driver API receives, e.g., from compiled code 444 generated by compiler 430 or from processor 402, a DMA instruction which indicates at least one indication of a storage location (source address) as input to the acceleration engine.).
Yu teaches an API provided by a driver controlling an acceleration engine allows applications to indicate input data to be loaded and operations to be executed on the input data (Yu: Col. 18, lines 1-32), where the input data may be referenced using memory addresses of the location in memory the data is stored (Yu: Col. 34, lines 52-53). Liu similarly teaches an API may be provided by a driver controlling an accelerated processing device to applications executing on a processor to access functionality of the accelerated processing device (Liu: [0018]), where an API call may cause operations on a generic tensor descriptor stored in memory (Liu: [0027] and [0101]). Therefore, it would have been obvious to one of ordinary skill in the art that the API of Liu, which cause operations on a generic tensor descriptor stored in memory, would receive the storage location of the generic tensor descriptor to be operated on as input as evidenced by Yu. Further, the teachings of YU improve the overall performance of a computing system for implementing a neural network model (Yu: Col. 2, lines 13-14).
Regarding claim 7, the combination of Liu in view of Yu teaches the processor of claim 1. Liu teaches wherein the API is to cause operations performed by a compiler (see [0018] and [0093]).
Yu teaches operations performed by a compiler to replace a first memory address with a second memory address (Col. 19, lines 29-36 – “store a set of memory descriptors used by DMA engine 550 to exchange data between system memory 520 and other components of computing system 500. […] memory descriptor providing a source address and a destination address can be placed in descriptor queue 560 to initiate the transfer.”; Col. 31, lines 47-50 – “first DMA load instruction may be used to load the tensor from the location of the system memory to a second region of the local memory (i.e., the destination of the second DMA load instruction)”. The source of DMA operation may be a system memory; destination may be a local memory. Thus, in combination with the cited portion of Col. 19, both the system memory and local memory (a.k.a. state buffer) are addressable (i.e., locations of the memories are referenced by addresses). The first DMA instruction maps the location of system memory (referenced by a “first memory address”) where tensor data (a third tensor) is stored to the second region of the local memory where the tensor data (a second tensor) is to be stored. Col. 2, lines 47-48 – “the local memory (also referred to as a state buffer”; Col. 32, lines 46-55 – “At block 1050, the host system may replace the first DMA load instruction in the instruction code with a second tensor copy instruction for saving data in the selected local memory block to a destination of the first DMA load instruction. For example, the second tensor copy instruction may be executed to read the reshaped tensor from the selected local memory block, change the reshaped tensor to the tensor in its original dimensions or in different dimensions matching the second region of the state buffer, and save the tensor to the second region of state buffer.” The second tensor copy instruction maps a selected local memory block (referenced by a “second memory address”) storing reshaped tensor data (a first tensor) to the second region of the state buffer, i.e., local memory, where the tensor data (the second tensor) is to be stored. The second tensor copy instruction replaces the first DMA instruction, i.e., the mapping of the first tensor to the second tensor replaces the mapping of the third tensor to the second tensor, effectively replacing the first memory address referencing the location of system memory with the second memory address referencing the selected local memory block of the state buffer.) in a data structure (Col. 15, lines 44-61 – “instructions for the program can be stored in processor memory 404. The instructions can also be stored elsewhere, such as on storage device 406, and can be loaded into processor memory 404 when needed by processor 402. […] program code and other data stored on storage device 406” Instruction code (data) is stored in memory (a structure); therefore replacing instructions indicating memory addresses in instruction code is replacing “in a data structure”.).
It would have been obvious to one of ordinary skill in the art to have modified the teachings of Liu to incorporate the teachings of Yu. Replacing some DMA load instructions that indicate a source location (a first data address) of a tensor in system memory with tensor copy instructions indicating a source location (a second data address) of a reshaped tensor in a state buffer reduces the overhead and results in a faster processing speed, lower latency, and high throughput (Yu: Col. 4, lines 25-37, and Col. 20, lines 24-32).
Regarding claim 8, Liu teaches A system, comprising: one or more processors (FIG. 1, processor 102) to implement the same functions of the circuits of the processor of claim 1. Thus, claim 8 is rejected as being unpatentable over Liu in view of Yu for the same reasons presented with respect to claim 1.
Claim 9 recites substantially the same limitations as claim 2. Thus, claim 9 is rejected as being unpatentable over Liu in view of Yu for the same reasons presented with respect to claim 2.
Claim 10 recites substantially the same limitations as claim 7, and further specifies the first memory address is “of a third tensor” and the second memory address is “of the first tensor”. The rejection made for claim 7 clarifies the first memory address corresponds to a “third tensor” and a second memory address corresponds to a “first tensor” as taught by Yu, even though the claim language did not require it. Thus, claim 10 is rejected for the same reasons presented with respect to claim 7.
Claim 11 recites substantially the same limitations as claim 4. Thus, claim 11 is rejected as being unpatentable over Liu in view of Yu for the same reasons presented with respect to claim 4.
Regarding claim 12, the combination of Liu in view of Yu teaches the system of claim 8. Liu further teaches wherein the API is to reuse a tensor map with at least one different tensor ([0033] – “The address function maps the set of all tensor coordinates of a generic tensor T to the set of all memory addresses associated with the generic tensor T.”; [0047] – “any number of transformation functions can be chained an applied to an existing generic tensor descriptor to construct a series of new generic tensor descriptors. […] Since a generic tensor can be defined using tensor raw data and an address function, a series of generic tensors T1, …, Tk can be defined by combining these transformation functions with the address function
g
:
→
x
0
→
y
for T0.” The address function (a mapping of a tensor to tensor data in memory, or a “tensor map”) of the original generic tensor descriptor is reused in defining any number of new tensors by combining the address function with any number of transformation functions.).
Regarding claim 13, the combination of Liu in view of Yu teaches the system of claim. Liu teaches a memory location of a mapping to be updated ([0027] – “Some operations are operations that act not on the generic tensor raw data, itself, but instead on the generic tensor descriptor. […]. Specifically, a slice modifies a generic tensor descriptor”; [0030] – “a generic tensor descriptor indicates the manner in which a multi-index maps to generic tensor raw data as stored in memory. The generic tensor descriptor facilitates proper mapping of elements of a multi-index to elements of generic tensor raw data.”; [0101] – “the generic tensor descriptors are stored at any appropriate location such as a memory”; [0094] – “The in-program tensor manipulator 404 or the tensor manipulator 406 external to the program 403 manipulate the generic tensor raw data 306 and generic tensor descriptor 308 according to the operations for manipulating the generic tensor raw data and the generic tensor descriptor described elsewhere herein.”; [0120] – “a tensor manipulator requestor 302 transmits a request to manipulate a generic tensor descriptor to a tensor manipulator 304. […] the tensor manipulator 304 performs the requested operation to manipulate the generic tensor descriptor.” The generic tensor descriptor, stored at an address in memory, on which to perform the manipulation/operation would necessarily be “indicated” to the tensor manipulator 404 or 406 to perform the operation. As is known in the art, data stored in memory can be represented by memory addresses.).
Yu teaches wherein the API is to indicate a memory location of data to be operated on (Col. 18, lines 1-32 – “Driver 422 can provide an interface between applications executing on host system 400 (or on another host system) and acceleration engine 412. For example, driver 422 can provide an Application Program Interface (API) that defines functions for feeding input data to acceleration engine 412 and defining the operation to perform on the input data. In this and other examples, driver 422 can configure acceleration engine 412 to perform the operation. For example, driver 422 can identify a neural network that acceleration engine 412 is to execute, as well as the location in processor memory 404 or on storage device 406 where compiled code 444 for the neural network is located. Driver 422 can further load into acceleration engine 412 or cause acceleration engine 412 to load compiled code 444, can load or cause acceleration engine 412 to load the input data on which the neural network is to operate, and/or can cause acceleration engine 412 to being executing on the input data. […] Data transfers between the local memory of a neural network processor and the system memory, including loading input tensors from the system memory to the local memory and saving intermediate output tensors from the local memory to the system memory to make room for other input tensors for other operations may be performed using a direct memory access (DMA) engine, in order to limit the involvement of the host processor. A DMA engine may use memory descriptors to perform the data transfers.”; Col. 34, lines 52-53- “a descriptor identifies an address for a block of data and an operation ( e.g., a read or a write) to perform.” Via the API provided by a driver, applications, such as those executing on processor 402, are able to feed (“indicate”) input data using memory addresses for the input data and define operations to perform on the input data to the driver/acceleration engine which performs the operations.)
Yu teaches an API provided by a driver controlling an acceleration engine allows applications to indicate input data to be loaded and operations to be executed on the input data (Yu: Col. 18, lines 1-32), where the input data may be referenced using memory addresses of the location in memory the data is stored (Yu: Col. 34, lines 52-53). Liu similarly teaches an API may be provided by a driver controlling an accelerated processing device to applications executing on a processor to access functionality of the accelerated processing device (Liu: [0018]), where an API call may cause operations on a generic tensor descriptor stored in memory (Liu: [0027] and [0101]). Therefore, it would have been obvious to one of ordinary skill in the art that the API calls of Liu, which cause operations on a generic tensor descriptor stored in memory, would indicate the storage location of the generic tensor descriptor to be operated on as evidenced by Yu. Further, the teachings of YU improve the overall performance of a computing system for implementing a neural network model (Yu: Col. 2, lines 13-14).
Claim 14 is directed to A method comprising the operations performs by the circuits of the processor of claim 1. Thus, claim 14 is rejected as being unpatentable over Liu in view of Yu for the same reasons presented with respect to claim 1.
Regarding claim 15, the combination of Liu in view of Yu teaches the method of claim 14. Liu teaches wherein the storage location corresponds to a tensor ([0030] – “With a generic tensor stored in memory, the point of origin corresponds to the base address of the generic tensor”).
Claim 16 recites substantially the same limitations as claim 2. Thus, claim 16 is rejected as being unpatentable over Liu in view of Yu for the same reasons presented with respect to claim 2.
Regarding claim 17, the combination of Liu in view of Yu teaches the method of claim 14. Liu teaches wherein performing the API comprises updating a tensor map ([0026] – “The individual operations are, in various implementations, performed by any of the following entities: […] hardware that performs the operations in response to an invocation such as an API call,”; [0027] – “Some operations are operations that act not on the generic tensor raw data, itself, but instead on the generic tensor descriptor. […]. Specifically, a slice modifies a generic tensor descriptor”; [0030] – “A generic tensor is described both by a generic tensor descriptor and generic tensor raw data. A generic tensor descriptor indicates the number of dimensions of the generic tensor, the lengths for each dimension, and a base address for the generic tensor raw data that the generic tensor descriptor is associated with. In addition, a generic tensor descriptor also provides a means to calculate the memory "offset" of a tensor raw data that is associated with a multi-index. Thus, a generic tensor descriptor indicates the manner in which a multi-index maps to generic tensor raw data as stored in memory. The generic tensor descriptor facilitates proper mapping of elements of a multi-index to elements of generic tensor raw data. […] With a generic tensor stored in memory, the point of origin corresponds to the base address of the generic tensor.”).
Claim 18 recites limitations which are substantially the same as the limitations recited in claim 2. Thus, claim 18 is rejected as being unpatentable over Liu in view of Yu for the same reasons presented with respect to claim 2.
Regarding claim 19, the combination of Liu in view of Yu teaches the method of claim 14. Liu teaches wherein performing the API comprises updating a data structure ([0027] – “Some operations are operations that act not on the generic tensor raw data, itself, but instead on the generic tensor descriptor. Such operations include the following: slice, […] Specifically, a slice modifies a generic tensor descriptor”; [0101] – “the generic tensor descriptors are stored at any appropriate location such as a memory”; [0120] – “The generic tensor descriptor is a construct that indicates how to obtain data elements of generic tensor raw data given an input multi-index.”) that stores information indicating how to transform the first tensor to obtain the second tensor ([0038]-[0039] – “B is a generic tensor descriptor that maps tensor coordinate space W to memory space Y. More specifically, generic tensor descriptor B can be thought of as being constructed using generic tensor descriptor A, which maps coordinate space X to memory address space Y as g: X[Symbol font/0xAE]Y, and the function ƒ: W[Symbol font/0xAE]X that maps coordinate space W to X. The function g: X[Symbol font/0xAE]Y is the address function associated with the generic tensor descriptor A. The function (gοƒ): W[Symbol font/0xAE]Y is the address function associated with generic tensor descriptor B. The function ƒ: W[Symbol font/0xAE] X is referred to as a “transformation function” here, which transforms generic tensor descriptor A into B.”; [0047] – “any number of transformation functions can be chained an applied to an existing generic tensor descriptor to construct a series of new generic tensor descriptors. […] Since a generic tensor can be defined using tensor raw data and an address function, a series of generic tensors T1, …, Tk can be defined by combining these transformation functions with the address function
g
:
→
x
0
→
y
for T0.” The original tensor descriptor A (a data structure which includes an address function mapping from the coordinate space original tensor A to the memory addresses of tensor raw data) is modified to indicate an address function for the generic tensor B, which is the original address function combined with a transformation function f (information indication how to transform from a first tensor A to a second tensor B).).
Regarding claim 20, the combination of Liu in view of Yu teaches the method of claim 14. Liu teaches A non-transitory computer-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to at least perform the method ([0124] – “The various functional units illustrated in the figures and/or described herein […] are, in various implementations, implemented as […] a program, software, or firmware, stored in a non-transitory computer readable medium or in another medium, executable by a general purpose computer, a processor, or a processor core.”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liu et al. (U.S. Pub. No. 2021/0334105) teaches a tensor descriptor, indicating a shape of a tensor and at least one address of the tensor data, is re-used by modifying a new address of the tensor data after it has been transferred to a shared storage space in response to a request (see [0047]-[0048], [0057], [0089], and [0091]).
LIU et al. (U.S. Pub. No. 2022/0188614) teaches in response to loading an operand (tensor data) to local memory such that it overwrites tensor data previously stored in the local memory, replacing an address correspondence in a data address information table between an address of the previously stored tensor data in an external storage and an address in the local memory with an address correspondence between an address of the loaded operand in external storage and the address in local memory (see [0058], [0300], and [0307]-[0308]).
Ashwathnarayan et al. (U.S. Pub. No. 2020/0364088) teaches a tensor can be imported as a pointer by an API model, and data can be received via input of an API (see [0060] and [0102]).
Zhao et al. (U.S. Pub. No. 2020/0174840) teaches an API call to perform a memory copy operation receives inputs for a device pointer and a host pointer, and copies tensor data from host to device (see [0069]).
Brady et al. (U.S. Pub. No. 2022/0108135) teaches a method for performing a machine learning instruction using storage element pointer comprising remapping input tensor data based on a first storage element pointer, causing execution of the machine learning operation on the remapped input tensor data to create intermediate tensor data, remapping the intermediate tensor data based on a second storage element pointer, and providing the remapped intermediate tensor data as an output tensor (see Abstract).
Lichtenau et al. (U.S. Pub. No. 2022/0405348) teaches reformatting an original tensor to provide one or more sub-tensors stored in memory, and general purpose-processors provide memory address information of the tensor data to a special-purpose processor for use in neural network computations (see [0067]-[0068]).
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/JENNIFER MARIE GUTMAN/Examiner, Art Unit 2194 /KEVIN L YOUNG/Supervisory Patent Examiner, Art Unit 2194
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