DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed December 21, 2022.
Claims 1-20 are pending. Claims 1, 7 and 11 are independent.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on April 11, 2024 and August 1, 2024. These IDSs have been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Applicant Admitted Prior Art (Figures 1a-1f; hereinafter “AAPA”).
Regarding independent claim 1, AAPA discloses an apparatus (Figs. 1a-1b), comprising:
a data buffer chip (Fig. 1a: 101) comprising write leveling training circuitry (Fig. 1b: 108), the write leveling training circuitry to detect when a sampled value of a WL pulse within a memory chip has changed (see AAPA description paragraph 0023 of Applicant’s Specification).
Regarding claim 2, AAPA discloses wherein the write leveling training circuitry is to, before the change of the value, determine a position of a DB pulse that is to be sent to the memory chip along an MDQS strobe wire that coupled the data buffer and the memory chip (see AAPA description paragraph 0021 of Applicant’s Specification).
Regarding claim 3, AAPA discloses wherein the write leveling training circuitry is to inform a register clock driver (RCD) chip of the value change (see AAPA description paragraph 0019 of Applicant’s Specification).
Regarding claim 4, AAPA discloses wherein the RCD chip is to be informed of the value change through an I3C bus that coupled the data buffer chip to the RCD chip (Fig. 1a: I3C).
Regarding claim 5, AAPA discloses wherein the detection is part of a Phase II internal write leveling training process of the memory chip (see AAPA description paragraph 0033 of Applicant’s Specification).
Regarding claim 6, AAPA discloses wherein the write leveling training circuitry is to determine a fixed DB pulse position of an MDQS strobe signal that is sent to the memory chip for a Phase I internal write leveling training process of the memory chip (see AAPA description paragraph 0031 and 0033 of Applicant’s Specification).
Regarding independent claim 7, AAPA discloses an apparatus (Figs. 1a-1b), comprising:
a registering clock driver (RCD) chip (Figs. 1a-1b: RCD) comprising write leveling training circuitry (Fig. 1b: 108) to determine when to send a write command to a memory chip and a data buffer chip during an external write leveling training process for the memory chip (see AAPA description paragraph 0019 of Applicant’s Specification).
Regarding claim 8, AAPA discloses the limitations with respect to claim 7.
As discussed above, AAPA’s apparatus is substantially identical in structure to the claimed “apparatus,” where the differences reside only in the remaining limitations relating to function of “receive from the data buffer results of samples of a WL pulse within the memory chip that was generated in response to the write command.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). AAPA’s apparatus appears to be identical to applicant’s apparatus, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 9, AAPA discloses wherein the write leveling training circuitry is to determine the external write leveling training process is complete in part because of a value change in the samples (see AAPA description paragraph 0033 of Applicant’s Specification).
Regarding claim 10, AAPA discloses wherein the write leveling training circuitry is to determine when to send a write command to a memory chip and a data buffer chip during an internal write leveling training process for the memory chip (see AAPA description paragraph 0019-0021 of Applicant’s Specification).
Allowable Subject Matter
Claims 11-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to independent claim 11, there is no teaching or suggestion in the prior art of record to provide the recited data buffer chip comprising first write leveling training circuitry, the write leveling training circuitry to detect when a sampled value of a WL pulse within a memory chip has changed as part of a write leveling training process of the memory chip, a registering clock driver (RCD) chip comprising second write leveling training circuitry to determine when to send a write command to the memory chip and the data buffer chip during the write leveling training process for the memory chip, in combination with the other limitations.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825