DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of species I in the reply filed on 11/26/2025 is acknowledged. The traversal is on the ground(s) that the difference between the identified species is the shape of the floating gate electrode. Applicant asserts that a search for one shape will have all the rest of the particulars of the memory cell such that there is no search and/or examination burden. This is not found persuasive because while the only difference is the comb-like or rectangular shape of the floating electrode Applicant has not stated on the record nor provided evidence that these distinct shapes are obvious variants such that a teaching of one shape is shows the obviousness of the other shape. That is a single reference showing only the rectangle shape is sufficient to reject the comb-like shape as well. As no evidence nor statement of obvious variants exists in the record these species remain distinct.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 8 recites “wherein when the non-volatile memory cell operates in the erase mode, the first voltage is a negative voltage, the second voltage is a low voltage, the read bit line voltage and the source line voltage are both a medium voltage, so that the read transistor induces an electron tunneling ejection.” The claim is indefinite because while claim 1, from which claim 8 depends, begins by reciting an apparatus, claim 8 further includes a method of using the structure in performing an erase operation. The claim is not considered a product by process claim because the claim does not state that any feature was made using the process of claim 8. The claim recites that the apparatus is used in performing the method of claim 8.
A single claim that includes both an apparatus and a method of using the apparatus is indefinite (See MPEP 2173.05(p)(II)). It is unclear if infringement would occur when the device is created as an apparatus or when the semiconductor device is used in the erase operation. For the purposes of examination the process limitation will be treated as an intended result limitation (i.e. the apparatus must be capable of being used in an erase operation).
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 9 recites “wherein when the non-volatile memory cell operates in the program mode, the first voltage and the second voltage are both a high voltage, the source line voltage is a medium voltage, the read bit line voltage is a low voltage such that the read transistor induces an electron tunneling injection, or the read bit line voltage is the medium voltage such that the read transistor does not induce the electron tunneling injection.” The claim is indefinite because while claim 1, from which claim 9 depends, begins by reciting an apparatus, claim 9 further includes a method of using the structure in performing a programming operation. The claim is not considered a product by process claim because the claim does not state that any feature was made using the process of claim 9. The claim recites that the apparatus is used in performing the method of claim 9.
A single claim that includes both an apparatus and a method of using the apparatus is indefinite (See MPEP 2173.05(p)(II)). It is unclear if infringement would occur when the device is created as an apparatus or when the semiconductor device is used in the programming operation. For the purposes of examination the process limitation will be treated as an intended result limitation (i.e. the apparatus must be capable of being used in a programming operation).
Claims 10-11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 10 recites “wherein when the non-volatile memory cell operates in the read mode, the select transistor is turned on, the source line voltage is a low voltage, and the read bit line voltage is a read voltage.” The claim is indefinite because while claim 1, from which claim 10 depends, begins by reciting an apparatus, claim 10 further includes a method of using the structure in performing a read operation. The claim is not considered a product by process claim because the claim does not state that any feature was made using the process of claim 10. The claim recites that the apparatus is used in performing the method of claim 10.
A single claim that includes both an apparatus and a method of using the apparatus is indefinite (See MPEP 2173.05(p)(II)). It is unclear if infringement would occur when the device is created as an apparatus or when the semiconductor device is used in the read operation. For the purposes of examination the process limitation will be treated as an intended result limitation (i.e. the apparatus must be capable of being used in a read operation).
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 11 recites “wherein when the non-volatile memory cell operates in the read mode, the first voltage and the second voltage are both a specific bias voltage.” The claim is indefinite because while claim 1, from which claim 11 depends, begins by reciting an apparatus, claim 11 further includes a method of using the structure in performing a read operation. The claim is not considered a product by process claim because the claim does not state that any feature was made using the process of claim 11. The claim recites that the apparatus is used in performing the method of claim 11.
A single claim that includes both an apparatus and a method of using the apparatus is indefinite (See MPEP 2173.05(p)(II)). It is unclear if infringement would occur when the device is created as an apparatus or when the semiconductor device is used in the read operation. For the purposes of examination the process limitation will be treated as an intended result limitation (i.e. the apparatus must be capable of being used in a read operation).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 9,653,173 B1 (Lo).
Re claim 1, Lo teaches a non-volatile memory cell (memory cell 100), comprising:
a tunneling part (portion of floating gate L1 in annotated Fig. 7 below);
a coupling transistor (coupling device CD), comprising a coupling gate part (portion of floating gate L1 in annotated Fig. 7 below), a first conductive region (P+ region in Reg1) and a second conductive region (Reg1), wherein the coupling gate part is coupled to the tunneling part, and disposed in the first conductive region;
a read transistor (read transistor RT), comprising a read gate part (portion of floating gate L1 in annotated Fig. 7 below) coupled to the tunneling part, for forming an electron tunneling ejection path in an erase mode, and forming an electron tunneling injection path in a program mode; and
a select transistor (second read selection transistor RST2), connected in series with the read transistor, for forming a read path with the read transistor in a read mode (Figs. 1-7).
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Re claim 2, Lo teaches wherein the first conductive region includes a first active region (highly doped P+ region), the second conductive region includes an electronic well (Reg1 is an N-well Col. 3 lines 3-4), and the first active region is disposed in the electronic well (Fig. 7).
Re claim 3, Lo teaches wherein the first active region surrounds the coupling gate part (Fig. 7).
Re claim 4, Lo teaches wherein the electron tunneling ejection path is the same as the electron tunneling injection path (electron tunneling and ejection paths are all along the L1 Fig. 7).
Re claim 5, Lo teaches wherein the read path is different from the electron tunneling ejection path and the electron tunneling injection path (read path is the electrical path along the SL to BL Fig. 4).
Re claim 6, Lo teaches wherein a second active region is disposed between the read gate part of the read transistor and a select gate part of the select transistor, and the read transistor is connected in series with the select transistor through the second active region (Figs. 1-7).
Re claim 7, Lo teaches wherein the first conductive region is used for receiving a first voltage, the second conductive region is used for receiving a second voltage, a first end of the read transistor different from the second active region is used for receiving a read bit line voltage (bit line signal BL), a second end of the select transistor different from the second active region is used for receiving a source line voltage (read source line signal SL), and the select gate part is used for receiving a read word line voltage (read select gate signal SG).
Re claim 8, Lo teaches wherein when the non-volatile memory cell operates in the erase mode, the first voltage is a negative voltage, the second voltage is a low voltage, the read bit line voltage and the source line voltage are both a medium voltage, so that the read transistor induces an electron tunneling ejection (this limitation is functional language and as the structure of the prior art is the same as that claimed then it is capable of this operation MPEP 2114 (II)).
Re claim 9, Lo teaches wherein when the non-volatile memory cell operates in the program mode, the first voltage and the second voltage are both a high voltage, the source line voltage is a medium voltage, the read bit line voltage is a low voltage such that the read transistor induces an electron tunneling injection, or the read bit line voltage is the medium voltage such that the read transistor does not induce the electron tunneling injection (this limitation is functional language and as the structure of the prior art is the same as that claimed then it is capable of this operation MPEP 2114 (II)).
Re claim 10, Lo teaches wherein when the non-volatile memory cell operates in the read mode, the select transistor is turned on, the source line voltage is a low voltage, and the read bit line voltage is a read voltage (this limitation is functional language and as the structure of the prior art is the same as that claimed then it is capable of this operation MPEP 2114 (II)).
Re claim 11, Lo teaches wherein when the non-volatile memory cell operates in the read mode, the first voltage and the second voltage are both a specific bias voltage (this limitation is functional language and as the structure of the prior art is the same as that claimed then it is capable of this operation MPEP 2114 (II)).
Re claim 12, Lo teaches wherein the coupling gate part is arranged as a finger shape or a rectangle (Fig. 7)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2019/0164982 A1 (Lu)
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US 8,472,251 B2 (Lee)
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US 2014/0293709 A1 (Kwon)
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896