DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Final office action is in response to application 18/087,025, Applicant’s response filed on 12/02/2025. In the response, claims 1-5, 7-15 and 17-20 are currently amended. No claims are cancelled. Claims 1-20 are currently pending in this application.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Response to Arguments
Applicant’s amendment and remarks filed on 12/02/2025 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by WANG et al. (US PG Pub No. 2013/0305200).
7. With respect to independent claims 1, 11 and 20, WANG teaches:
A method comprising:
receiving a register transfer level (RTL) circuit representation (receiving RTL, see Fig 2 at 202; user supplies RTL codes 202, para 73) comprising a first node (see RTL code for test point/node selection, para 73);
identifying the first node as a candidate for selective scan insertion (see node/test point selection for scan selection and insertion, para 73-75) for functional verification (verifying functionality, par 4, 12-13; accepting functional logic, functional verification, para 70-73); and
performing the selective scan insertion at the first node within the RTL circuit representation to enable simulation and verification of circuit operation prior to circuit synthesis (scan selection, test point insertion, Abstract; scan before logic synthesis, para 12; RTL scan insertion prepared for synthesis and verification, para 12).
8. With respect to claims 2 and 12, WANG teaches:
The method of claim 1, further comprising:
simulating operation of a circuit in the circuit representation prior to synthesis (simulating circuit representation, para 18; scan selection, test point insertion, Abstract; scan before logic synthesis, para 12; RTL scan insertion prepared for synthesis and verification, para 12); and
in response to the simulated circuit generating an output at the first node, generating a characteristic signature for the circuit based on the output (see expected signature once stimuli is applied, para 72).
9. With respect to claims 3 and 13, WANG teaches:
The method of claim 2, further comprising:
synthesizing or fabricating a circuit based on the RTL circuit representation (see synthesizing circuit design, para 12, 82);
simulating or monitoring operation of the synthesized or fabricated circuit (performing simulation on synthesized circuit, para 148-150);
comparing the operation of the synthesized or fabricated circuit with the characteristic signature for the circuit (comparing synthesized circuit output with signature, para 72); and
providing an indication of whether the operation of the synthesized or fabricated circuit aligns with the characteristic signature for the circuit (see aligning/fixing mismatches between signature and expected output between synthesized circuit and output signatures, para 145-149, 155-158).
10. With respect to claims 4 and 14, WANG teaches:
The method of claim 3, further comprising performing selective scan insertion on at least one additional node in response to operation of the synthesized or fabricated circuit not aligning with the characteristic signature for the circuit (see node/test point selection for scan selection and insertion, para 73-75; see not-aligning/fixing mismatches between signature and expected output between synthesized circuit and output signatures, para 145-149, 155-158).
11. With respect to claims 5 and 15, WANG teaches:
The method of claim 1, wherein identifying the first node as a candidate for selective scan insertion comprises simulating operation of a virtualized component within the RTL circuit representation (see virtualized components, virtual removal and/or replacing storage elements, para 23-25).
12. With respect to claims 6 and 16, WANG teaches:
The method of claim 1, wherein identifying the first node as a candidate for selective scan insertion comprises identifying the first node based on a behavioral model or a machine learning model (see behavioral model, scan insertion and observation points based on behavioral/combinational logic models, para 138-143).
13. With respect to claims 7 and 17, WANG teaches:
The method of claim 1, wherein identifying the first node as a candidate for selective scan insertion comprises monitoring the first node for errors or distortions during simulation of the RTL circuit representation (see not-aligning/fixing mismatches between signature and expected output between synthesized circuit and output signatures, para 145-149, 155-158; see errors, para 34, 73, 117).
14. With respect to claims 8 and 18, WANG teaches:
The method of claim 1, wherein identifying the first node as a candidate for selective scan insertion comprises randomly selecting one or more nodes in the RTL circuit representation (see node/test point selection for scan selection and insertion, para 73-75).
15. With respect to claim 9, WANG teaches:
The method of claim 1, further comprising including the selective scan insertion in a request for manufacture of a circuit based on the RTL circuit representation (see reporting files including RTL and scan insertion as output for circuit fabrication, Fig 2, 213, 216).
16. With respect to claims 10 and 19, WANG teaches:
The method of claim 1, wherein performing scan insertion at the first node includes inserting memory built-in self-test logic within the RTL circuit representation (see built-in-self-test, Abstract).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm.
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/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851
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