DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 04 Mar 2026 for application number 18/087,159. The Office hereby acknowledges receipt of the following and placed of record in file: Applicant Arguments/Remarks, and Claims.
Claims 1-20 are presented for examination; elected claims 1-3 and 5-20 are examined below; non-elected claim 4 has been withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 27 Mar 2026 was filed before the mailing of this Office Action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
The objections to claims 1-3 and 5-10 and 11 have been removed in light of amendments.
Regarding claim 1, Applicant contends that the prior art does not teach, “a channel column array…among the transition channel columns”; Examine respectfully disagrees. Kwon teaches:
a channel column [channel structure 122; Fig. 1, para 0032] array in the stacked layers, wherein the channel column array [122] comprises storage channel columns [122] operated to store charges [para 0050 discloses the columns contain a charge storage layer], arranged in the first lateral direction [first direction];
a gate isolating trench [first dummy structure 124; Fig. 2, para 0032] in the stacked layers [102/134], wherein the gate isolating trench [124] extends between the channel column [122] array and the dummy channel column [126] array along the second lateral direction [second direction; Figs. 1 and 12].
Kwon and Jung further teach:
wherein the channel column [122 of Kwon] array comprises storage channel columns [first dummy structures 124; Fig. 3, para 0044 of Jung] and transition channel columns [second dummy structures 126; Fig. 3, para 0044 of Jung], arranged along the first lateral direction [first direction; Fig. 3 of Jung]; wherein:
the transition channel columns [126 of Jung] are arranged between the storage channel columns [124 of Jung] and the gate isolating trench [124 of Kwon]; and
each transition channel column [126 of Jung] in a row of transition channel columns that extends in the second lateral direction [second direction; Fig. 3 of Jung] and is immediately adjacent to the gate isolating trench [124 of Kwon] has a greatest critical dimension among the transition channel columns [furthest right column of 126 of Jung have the largest diameter; Fig. 3 of Jung; the furthest right column of 126 of Jung would be immediately adjacent to 124 of Kwon].
It would have been obvious to one of ordinary skill in the art to replace the channel column array of Kwon with the channel column array of Jung, i.e. the storage channel columns and transition channel columns of Jung. In doing so, the transition columns of Jung would be “immediately adjacent” the gate isolating trench of Kwon. One of ordinary skill in the art would be motivated to obtain a semiconductor device with transition channel columns and channel structures that are different sizes to provide the predictable result of reducing defects in the structure [Jung, para 0052], as well as drastically limiting leakage current. Therefore, the prior art teaches, a channel column array…among the transition channel columns.”
Claim 11 is rejected for these reasons, and for reasons as expressed in the Rejection below.
Dependent claims 2-3, 5-10, and 12-20 are rejected for these reasons, and for reasons as expressed in the Rejection below.
The argument regarding rejoinder of claim 4 is moot, as claim 1 is not currently allowable.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5, 8-14, and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. [hereinafter as Kwon] (US 2019/0035942 A1) in view of Jung et al. [hereinafter as Jung] (US 2020/0105785 A1).
In reference to claim 1, Kwon teaches A semiconductor device, comprising:
stacked layers [insulating layers 102 and conductive layers 134; Fig. 1, para 0035], wherein the stacked layers comprise insulating layers [102] and gate layers [134] that are alternately stacked along a vertical direction [third direction; Fig. 1] and extending in a first lateral direction [first direction; Fig. 1] and a second lateral direction [second direction; Fig. 1], wherein the first lateral direction [first direction] and the second lateral direction [second direction] are perpendicular to each other and are both perpendicular to the vertical direction [first and second direction are perpendicular to each other, and perpendicular to the third direction];
a channel column [channel structure 122; Fig. 1, para 0032] array in the stacked layers, wherein the channel column array [122] comprises storage channel columns [122] operated to store charges [para 0050 discloses the columns contain a charge storage layer], arranged in the first lateral direction [first direction];
a dummy channel column [second dummy structure 126; Fig. 1, para 0032] array in the stacked layers, wherein the dummy channel column [126] array comprises a plurality of dummy channel columns [126] arranged in the first lateral direction [first direction] and the second lateral direction [second direction]; and
a gate isolating trench [first dummy structure 124; Fig. 2, para 0032] in the stacked layers [102/134], wherein the gate isolating trench [124] extends between the channel column [122] array and the dummy channel column [126] array along the second lateral direction [second direction; Figs. 1 and 12].
However, Kwon does not explicitly teach:
wherein the channel column array comprises storage channel columns and transition channel columns, arranged along the first lateral direction; wherein
the transition channel columns are arranged between the storage channel columns and the gate isolating trench; and
each transition channel column in a row of transition channel columns that extends in the second lateral direction and is immediately adjacent to the gate isolating trench has a greatest critical dimension among the transition channel columns.
Kwon and Jung teach wherein the channel column [122 of Kwon] array comprises storage channel columns [first dummy structures 124; Fig. 3, para 0044 of Jung] and transition channel columns [second dummy structures 126; Fig. 3, para 0044 of Jung], arranged along the first lateral direction [first direction; Fig. 3 of Jung]; wherein:
the transition channel columns [126 of Jung] are arranged between the storage channel columns [124 of Jung] and the gate isolating trench [124 of Kwon]; and
each transition channel column [126 of Jung] in a row of transition channel columns that extends in the second lateral direction [second direction; Fig. 3 of Jung] and is immediately adjacent to the gate isolating trench [124 of Kwon] has a greatest critical dimension among the transition channel columns [furthest right column of 126 of Jung have the largest diameter; Fig. 3 of Jung; the furthest right column of 126 of Jung would be immediately adjacent to 124 of Kwon].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Kwon and Jung before the effective filing date of the claimed invention, to include the size of channel structures as well as transition channel columns as disclosed by Jung into the semiconductor device of Kwon in order to obtain a semiconductor device with transition channel columns and channel structures that are different sizes.
One of ordinary skill in the art would be motivated to obtain a semiconductor device with transition channel columns and channel structures that are different sizes to provide the predictable result of reducing defects in the structure [Jung, para 0052], as well as drastically limiting leakage current.
In reference to claim 2, Kwon and Jung teach the invention of claim 1.
Jung teaches The semiconductor device according to claim 1, wherein a critical dimension of the transition channel columns [126] is larger [126 are larger than 124; Fig. 3, para 0043] than a critical dimension of the storage channel columns [124].
In reference to claim 3, Kwon and Jung teach the invention of claim 1.
Kwon teaches The semiconductor device according to claim 1, wherein the dummy channel columns [126] are located in a stair-step region [126 are located in R2 (stair-step region); Fig. 1] of the stacked layers [102/134].
In reference to claim 5, Kwon and Jung teach the invention of claim 1.
Kwon teaches The semiconductor device according to claim 1, wherein the gate isolating trench [124] comprises a plurality of isolating trenches [124; Fig. 12] arranged at intervals along the second lateral direction [second direction] in a dotted line shape [124 arranged in a dotted-line shape; Fig. 12].
In reference to claim 8, Kwon and Jung teach the invention of claim 1.
Kwon teaches The semiconductor device according to claim 1, wherein a cross-sectional shape of the gate isolating trench [124] in the first lateral direction [first direction] comprises at least one of a rectangle [124 is rectangularly-shaped; Fig. 12], a trapezoid, or a semicircular shape [para 0131 discloses 124 may be various shapes], and a surface of the gate isolating trench [124] facing the dummy channel column [126] array is planar [124 is rectangular, so has a planar portion facing 126; Fig. 12].
In reference to claim 9, Kwon and Jung teach the invention of claim 2.
Jung teaches The semiconductor device according to claim 2, wherein an arrangement density of the transition channel columns [126] in the channel column array gradually decreases [the first spacings P1 increase from left to right, i.e. density decreases; Fig. 3, para 0045] towards the dummy channel column array [128 in R2] along the first lateral direction [first direction].
In reference to claim 10, Kwon and Jung teach the invention of claim 9.
Jung teaches The semiconductor device according to claim 9, wherein each of the transition channel columns [126] has a critical dimension from a center of each of the transition channel columns [126] to an edge of each of the transition channel columns [126], and the critical dimension of each of the transition channel columns [126] gradually increases [the column widths C1-3 of 126 increase from left to right, i.e. C3<C2<C1; Fig. 3, para 0042] towards the dummy channel column array [128 in R2] along the first lateral direction [first direction].
In reference to claim 11, Kwon teaches A method for preparing a semiconductor device, comprising:
providing a substrate [substrate 100; Fig. 1, para 0031];
forming stacked layers [insulating layers 102 and conductive layers 134; Fig. 1, para 0035] on the substrate [100] by alternately stacking insulating layers [102] and gate layers [134] along a vertical direction [third direction; Fig. 1], wherein the insulating layers [102] and gate layers [134] extend along a first lateral direction [first direction; Fig. 1] and a second lateral direction [second direction; Fig. 1], wherein the first lateral direction [first direction] and the second lateral direction [second direction] are perpendicular to each other and are both perpendicular to the vertical direction [first and second direction are perpendicular to each other, and perpendicular to the third direction];
forming a channel column [channel structure 122; Fig. 1, para 0032] array in the stacked layers [102/134], wherein the channel column [122] array comprises storage channel columns [122] operated to store charges [para 0050 discloses the columns contain a charge storage layer], arranged in the first lateral direction [first direction];
forming a dummy channel column [second dummy structure 126; Fig. 1, para 0032] array in the stacked layers [102/134], wherein the dummy channel column [126] array comprises a plurality of dummy channel columns [126] arranged in the first lateral direction [first direction] and the second lateral direction [second direction]; and
forming a gate isolating trench [first dummy structure 124; Fig. 2, para 0032] in the stacked layers [102/134], wherein the gate isolating trench [124] extends between the channel column [122] array and the dummy channel column array [126] along the second lateral direction [second direction; Figs. 1 and 12].
However, Kwon does not explicitly teach:
wherein the channel column array comprises storage channel columns and transition channel columns, arranged along the first lateral direction; wherein
the transition channel columns are arranged between the storage channel columns and the gate isolating trench; and
each transition channel column in a row of transition channel columns that extends in the second lateral direction and is immediately adjacent to the gate isolating trench has a greatest critical dimension among the transition channel columns.
Kwon and Jung teach wherein the channel column [122 of Kwon] array comprises storage channel columns [first dummy structures 124; Fig. 3, para 0044 of Jung] and transition channel columns [second dummy structures 126; Fig. 3, para 0044 of Jung], arranged along the first lateral direction [first direction; Fig. 3 of Jung]; wherein:
the transition channel columns [126 of Jung] are arranged between the storage channel columns [124 of Jung] and the gate isolating trench [124 of Kwon]; and
each transition channel column [126 of Jung] in a row of transition channel columns that extends in the second lateral direction [second direction; Fig. 3 of Jung] and is immediately adjacent to the gate isolating trench [124 of Kwon] has a greatest critical dimension among the transition channel columns [furthest right column of 126 of Jung have the largest diameter; Fig. 3 of Jung; the furthest right column of 126 of Jung would be immediately adjacent to 124 of Kwon].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Kwon and Jung before the effective filing date of the claimed invention, to include the size of channel structures as well as transition channel columns as disclosed by Jung into the semiconductor device of Kwon in order to obtain a semiconductor device with transition channel columns and channel structures that are different sizes.
One of ordinary skill in the art would be motivated to obtain a semiconductor device with transition channel columns and channel structures that are different sizes to provide the predictable result of reducing defects in the structure [Jung, para 0052], as well as drastically limiting leakage current.
In reference to claim 12, Kwon and Jung teach the invention of claim 11.
Jung teaches The method according to claim 11, wherein a critical dimension of the transition channel columns [126] is larger [126 are larger than 124; Fig. 3, para 0043] than a critical dimension of the storage channel columns [124].
In reference to claim 13, Kwon and Jung teach the invention of claim 11.
Kwon teaches The method according to claim 11, wherein the dummy channel columns [126] are located in a stair-step region [126 are located in R2 (stair-step region); Fig. 1] of the stacked layers [102/134].
In reference to claim 14, Kwon and Jung teach the invention of claim 11.
Kwon teaches The method according to claim 11, wherein the gate isolating trench [124] comprises a plurality of isolating trenches [124; Fig. 12] arranged at intervals along the second lateral direction [second direction] in a dotted line shape [124 arranged in a dotted-line shape; Fig. 12].
In reference to claim 17, Kwon and Jung teach the invention of claim 11.
Kwon and Jung teach The method according to claim 11, wherein a material filled in the transition channel columns [126 of Jung] is silicon oxide [Kwon, para 0050 discloses that the columns may contain silicon oxide].
In reference to claim 18, Kwon and Jung teach the invention of claim 1.
Kwon and Jung teach The semiconductor device according to claim 1, wherein a material filled in the transition channel columns [126 of Jung] is silicon oxide [Kwon, para 0050 discloses that the columns may contain silicon oxide].
In reference to claim 19, Kwon and Jung teach the invention of claim 1.
Kwon and Jung teach The semiconductor device according to claim 1, wherein a critical dimension of each of the transition channel columns [126] gradually increases towards the gate isolating trench [124 of Kwon] along the first lateral direction [furthest right column of 126 of Jung have the largest diameter, and decrease in the left direction, i.e. increase in the right direction; Fig. 3].
Claim(s) 6-7, 15-16, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Jung further in view of Lu et al. [hereinafter as Lu] (US 2019/0067314 A1).
In reference to claim 6, Kwon and Jung teach the invention of claim 1.
However, Kwon and Jung do not explicitly teach The semiconductor device according to claim 1, further comprising a gate line slit penetrating through the stacked layers in the vertical direction and extending along the first lateral direction.
Lu teaches a gate line slit [slit structures 114/228; Figs. 1A, 2, paras 0039, 0052] penetrating through the stacked layers [114/228 penetrate the stacked layers; Fig. 2] in the vertical direction [y-direction; Fig. 2] and extending along the first lateral direction [WL direction; Fig. 1A].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Kwon, Jung, and Lu before the effective filing date of the claimed invention, to include the slit structures as disclosed by Lu into the semiconductor device of Kwon and Jung in order to obtain a semiconductor device with slit structures.
One of ordinary skill in the art would be motivated to obtain a semiconductor device with slit structures to provide the predictable result of providing structural integrity and dividing memory blocks, and even function as a common source contact [Lu, para 0039].
In reference to claim 7, Kwon, Jung, and Lu teach the invention of claim 6.
Kwon and Lu teach The semiconductor device according to claim 6, wherein a material of the gate isolating trench [124 of Kwon may be polysilicon, for example; paras 0049-0050] is same as a material of the gate line slit [114/228 of Lu may be polysilicon, for example; para 0075].
In reference to claim 15, Kwon and Jung teach the invention of claim 11.
However, Kwon and Jung do not explicitly teach The method according to claim 11, further comprising a gate line slit extending through the stacked layers in the vertical direction and extending along the first lateral direction.
Lu teaches The method according to claim 11, further comprising a gate line slit [slit structures 114/228; Figs. 1A, 2, paras 0039, 0052] extending through the stacked layers [114/228 penetrate the stacked layers; Fig. 2] in the vertical direction [y-direction; Fig. 2] and extending along the first lateral direction [WL direction; Fig. 1A].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Kwon, Jung, and Lu before the effective filing date of the claimed invention, to include the slit structures as disclosed by Lu into the semiconductor device of Kwon and Jung in order to obtain a semiconductor device with slit structures.
One of ordinary skill in the art would be motivated to obtain a semiconductor device with slit structures to provide the predictable result of providing structural integrity and dividing memory blocks, and even function as a common source contact [Lu, para 0039].
In reference to claim 16, Kwon, Jung, and Lu teach the invention of claim 6.
Kwon and Lu teach The method according to claim 15, wherein a material of the gate isolating trench [124 of Kwon may be polysilicon, for example; paras 0049-0050] is same as a material of the gate line slit [114/228 of Lu may be polysilicon, for example; para 0075].
In reference to claim 20, Kwon and Jung teach the invention of claim 1.
However, Kwon and Jung do not explicitly teach The semiconductor device according to claim 1, wherein a material of the gate isolating trench is same as a material of a gate line slit extending through the stacked layers in the vertical direction.
Kwon and Lu teach wherein a material of the gate isolating trench [124 of Kwon may be polysilicon, for example; paras 0049-0050] is same as a material of a gate line slit [slit structures 114/228; Figs. 1A, 2, paras 0039, 0052 of Lu] extending through the stacked layers [114/228 penetrate the stacked layers; Fig. 2 of Lu] in the vertical direction [114/228 of Lu may be polysilicon, for example; para 0075].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Kwon, Jung, and Lu before the effective filing date of the claimed invention, to include the slit structures as disclosed by Lu into the semiconductor device of Kwon and Jung in order to obtain a semiconductor device with slit structures.
One of ordinary skill in the art would be motivated to obtain a semiconductor device with slit structures to provide the predictable result of providing structural integrity and dividing memory blocks, and even function as a common source contact [Lu, para 0039].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANDREW CHUNG/
Examiner, Art Unit 2898
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