The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (U.S. Patent Application Publication 2020/0006160, hereinafter referred to as Lin).
As to claim 1, Lin teaches 1. An integrated circuit comprising: a semiconductor device having a semiconductor region extending in a first direction from a source or drain region, and a gate structure extending in a second direction over the semiconductor region [see 204, 206 and 210 in Fig. 2]; and a conductive contact on at least a top surface of the source or drain region, wherein the conductive contact has a first section directly above the source or drain region and a second section extending away from the source or drain region such that the source or drain region is not below the second section, and wherein the first section has a first thickness and the second section has a second thickness, the first thickness being greater than the second thickness by 5 nm or more. [see 256 in Fig. 13]
As to claim 2, Lin teaches 2. The integrated circuit of claim 1, wherein the semiconductor region comprises a plurality of semiconductor nanoribbons. [¶0013]
As to claim 3, Lin teaches 3. The integrated circuit of claim 1, wherein a top surface of the first section of the conductive contact is substantially coplanar with a top surface of the second section of the conductive contact, and a bottom surface of the first section of the conductive contact is not coplanar with a bottom surface of the second section of the conductive contact due to the first thickness being greater than the second thickness. [see 256 in Fig. 13]
As to claim 4, Lin teaches 4. The integrated circuit of claim 1, wherein the source or drain region is a first source or drain region and the second section of the conductive contact extends over a second source or drain region of an adjacent semiconductor device. [see 256 in Fig. 13]
As to claim 5, Lin teaches 5. The integrated circuit of claim 4, wherein the first source or drain region has a different dopant type (n or p) than the second source or drain region. [see 214, 216 in Fig. 13]
As to claim 6, Lin teaches 6. The integrated circuit of claim 1, further comprising a conductive via that contacts a top surface of the second section of the conductive contact. [see 256 in Fig. 12]
As to claim 7, Lin teaches 7. The integrated circuit of claim 1, wherein both the first and second sections of the conductive contact comprise a continuous conductive liner and a continuous and monolithic body of conductive fill. [see 252, 250, 256 in Fig. 13]
As to claim 8, Lin teaches 8. A printed circuit board comprising the integrated circuit of claim 1. [¶0002, 0015]
As to claim 9, Lin teaches 9. An electronic device, comprising: a chip package comprising one or more dies, at least one of the one or more dies comprising a semiconductor device having a semiconductor region extending in a first direction from a source or drain region, and a gate structure extending in a second direction over the semiconductor region; and a conductive contact on at least a top surface of the source or drain region, wherein the conductive contact has a first section directly above the source or drain region and a second section extending away from the source or drain region such that the source or drain region is not below the second section, and wherein the first section has a first thickness and the second section has a second thickness, the first thickness being at least 10 nm greater than the second thickness. [see 204, 206 and 210 in Fig. 2; see 256 in Fig. 13; ¶0002; ¶0015]
As to claim 10, Lin teaches 10. The electronic device of claim 9, wherein a top surface of the first section of the conductive contact is substantially coplanar with a top surface of the second section of the conductive contact. [see 256 in Fig. 13]
As to claim 11, Lin teaches 11. The electronic device of claim 9, wherein the source or drain region is a first source or drain region and the second section of the conductive contact extends over a second source or drain region from an adjacent semiconductor device. [see 256 in Fig. 13]
As to claim 12, Lin teaches 12. The electronic device of claim 9, wherein the at least one of the one or more dies further comprises a conductive via that contacts a top surface of the second section of the conductive contact. [see 292 and 256 in Fig. 13]
As to claim 13, Lin teaches 13. The electronic device of claim 9, wherein the first thickness is at least two times greater than the second thickness. [see 256 in Fig. 13]
As to claim 14, Lin teaches 14. The electronic device of claim 9, further comprising a printed circuit board, wherein the chip package is coupled to the printed circuit board. [¶0002; ¶0015]
As to claim 15, Lin teaches 15. An integrated circuit comprising: a first semiconductor device having a first semiconductor region extending in a first direction from a first source or drain region; a second semiconductor device having a second semiconductor region extending in the first direction from a second source or drain region, the second source or drain region being adjacent to the first source or drain region along a second direction orthogonal to the first direction; and a conductive contact on at least a top surface of the first source or drain region, wherein the conductive contact has a first section directly above the first source or drain region and a second section extending away from the source or drain region and over, but not contacting, the second source or drain region, and wherein the first section has a first thickness and the second section has a second thickness, the first thickness being at least 5 nm greater than the second thickness. [see rejections claim 1 and 9 above]
As to claim 16, Lin teaches 16. The integrated circuit of claim 15, wherein a top surface of the first section of the conductive contact is substantially coplanar with a top surface of the second section of the conductive contact. [see 256 in Fig. 13]
As to claim 17, Lin teaches 17. The integrated circuit of claim 15, wherein the first source or drain region has a different dopant type (n or p) than the second source or drain region. [see 214, 216 in Fig. 13]
As to claim 18, Lin teaches 18. The integrated circuit of claim 15, further comprising a conductive via that contacts a top surface of the second section of the conductive contact. [see 292, 256 in Fig. 13]
As to claim 19, Lin teaches 19. The integrated circuit of claim 15, wherein both the first and second sections of the conductive contact comprise a conductive liner and a conductive fill. [see 252 in Fig. 13]
As to claim 20, Lin teaches 20. The integrated circuit of claim 15, wherein the first thickness is at least two times greater than the second thickness. [see 256 in Fig. 13]
Conclusion
Claims 1-20 are rejected as explained above.
The prior art made of record in the PTO-892 form and not relied upon is considered pertinent to applicant's disclosure.
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/JAEHWAN OH/
Primary Examiner, Art Unit 2899