Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/16/2024 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97.
Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 15, 16, 18, 19, 27 – 31, 33, and 34 are objected to because of the following informalities:
Claims 15, 16, 18, and 19, as written in the claims are dependent on a cancelled claim. For ease of examination, examiner will use claim 14 as the independent claim for claims 15, 16, 18, and 19.
Claims 27 – 31, 33, and 34, as written in the claims are dependent on a cancelled claim. For ease of examination, examiner will use claim 26 as the independent claim for claims 27 – 31, 33, and 34.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho (US 20200059210 A1).
Regarding Independent Claim 1, Cho teaches,
An amplifier (See Fig. 1) including:
an amplifier input terminal (Fig. 1, IN) configured to receive a radio-frequency (RF) signal (Fig. 1, IN is configured to receive a signal);
an amplifier core (Fig. 1, 100) including:
an amplifier core input terminal (Fig. 1, terminal of 100 coupled to CB1) configured to receive the RF signal through an input matching inductor (Fig. 1, 200 [See paragraph [0021], “The input matching circuit may include an input inductor connected between the input terminal and the first connection node and configured to perform impedance matching between the input terminal and the amplifying circuit, and a variable attenuation circuit connected in series to the input inductor and configured to adjust a signal damping ratio in conjunction with an amplification ratio of the amplifying circuit.”]) coupled between the amplifier input terminal (Fig. 1, IN) and the amplifier core input terminal (Fig. 1, terminal of 100 coupled to CB1); and
an amplified-signal terminal (Fig. 1, terminal of 100 coupled to N2);
an amplifier output terminal (Fig. 1, OUT);
an impedance matching network (Fig. 1, 300) coupled to the amplifier output terminal and to the amplified-signal terminal (Fig. 1, 300 is coupled to a terminal of 100 and to OUT);
a bypass circuit (Fig. 1, 400) coupled between the amplified-signal terminal and the amplifier core input terminal (Fig. 1, 400 is coupled to both terminals of 100), the bypass circuit including:
a first switch (Fig. 1, the switch in 400 directly coupled to N1, SW1) and a second switch (Fig. 1, the switch in 400 directly coupled to N2, SW2) coupled in series, the first switch being coupled to the amplifier core input terminal (Fig. 1, SW1 is coupled to the input terminal of 100);
a bypass circuit node (Fig. 5, N3) between the first switch and the second switch (Fig. 1, SW1 and SW2), the bypass circuit node configured to be coupled to a matching inductor (Fig. 1, 410);
a matching capacitor (Fig. 5, C40) coupled to the bypass circuit node (Fig. 1, N3); and
a bypass circuit path (Fig. 1, path comprising SW2, 300, and OUT) coupled to the second switch of the bypass circuit (Fig. 1, SW2), the impedance matching network (Fig. 1, 300), and the amplifier output terminal (Fig. 1, OUT), the bypass circuit path configured to allow, in at least one bypass mode of operation, an RF signal to propagate from the bypass circuit to the amplifier output terminal while avoiding the impedance matching network (Fig. 10 shows the application operating in “bypass mode” [See paragraph [0094], “FIG. 10 is a diagram showing an example of an operation of the amplifying device of FIG. 8 in a bypass mode.”]).
Regarding claim 2,
The invention of claim 1, wherein the amplifier core (Fig. 1, 100) includes a degeneration terminal (Fig. 8, terminal of L1), and further including a degeneration inductor (Fig. 1, L1) coupled between the degeneration terminal and a reference potential [See paragraph [0078], “A gate of the first transistor M1 may be connected to the input matching circuit 200 through the DC blocking capacitor CB1 and may be connected to a terminal of a first bias voltage VB1 through a resistor R1. An inductor L1 may be connected between ground and a source of the first transistor M1. For example, the inductor L1 may be a degeneration inductor for enhancing linearity.”].
Regarding claim 3,
The invention of claim 1, wherein the matching inductor is a variable inductor (the matching circuit comprises a variable attenuation circuit [See paragraph [0021], “The input matching circuit may include an input inductor connected between the input terminal and the first connection node and configured to perform impedance matching between the input terminal and the amplifying circuit, and a variable attenuation circuit connected in series to the input inductor and configured to adjust a signal damping ratio in conjunction with an amplification ratio of the amplifying circuit.”]).
Regarding claim 4,
The invention of claim 1, wherein the matching capacitor is a variable capacitor (the matching capacitor is a variable capacitor, [See paragraph [0022], “The output matching circuit may include an output inductor connected between a terminal of a power voltage and the second connection node at the output side of the amplifying circuit, a variable resistor circuit connected in parallel to the output inductor, a variable capacitor circuit connected between the second connection node and the output terminal, and an output capacitor connected between the output terminal and ground”].
Regarding claim 5,
The invention of claim 1, wherein the bypass circuit node is coupled to an AC ground (Fig. 5, N3 is coupled to ground).
Regarding claim 6,
The invention of claim 1, wherein the amplifier core includes a field-effect transistor stack (Fig. 8, the transistors are stacked, [See paragraph [0077], “the amplifying circuit 100 may include a first transistor M1, a second transistor M2, and a third transistor M3, which are stacked between the first connection node N1 and the second connection node N2”].
Regarding claim 7,
The invention of claim 1, wherein the impedance matching network (Fig. 1, 300) includes an output capacitor coupled to a load inductor [See paragraph [0085], “the output matching circuit 300 may include an output inductor L31, a variable resistor circuit R31, a variable capacitor circuit C31, and an output capacitor C32.”].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14 – 16, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Lee et al. (US 20200259471 A1), hereinafter Lee.
Regarding independent claim 14, Cho discloses,
An amplifier (See Fig. 1) including:
an amplifier input terminal (Fig. 1, IN) configured to receive a radio-frequency (RF) signal (Fig. 1, IN is configured to receive a signal);
an amplifier core (Fig. 1, 100) including:
an amplifier core input terminal (Fig. 1, terminal of 100 coupled to CB1) configured to receive the RF signal through an input matching inductor (Fig. 1, 200 [See paragraph [0021], “The input matching circuit may include an input inductor connected between the input terminal and the first connection node and configured to perform impedance matching between the input terminal and the amplifying circuit, and a variable attenuation circuit connected in series to the input inductor and configured to adjust a signal damping ratio in conjunction with an amplification ratio of the amplifying circuit.”]) coupled between the amplifier input terminal (Fig. 1, IN) and the amplifier core input terminal (Fig. 1, terminal of 100 coupled to CB1); and
an amplified-signal terminal (Fig. 1, terminal of 100 coupled to N2);
an amplifier output terminal (Fig. 1, OUT);
an impedance matching network (Fig. 1, 300) coupled to the amplifier output terminal and to the amplified-signal terminal (Fig. 1, 300 is coupled to a terminal of 100 and to OUT);
a bypass capacitor (Fig. 8, C31) coupled to the impedance matching network (Fig. 1, 300);
a bypass circuit (Fig. 1, 400) coupled between the bypass capacitor (Fig. 8, C31) and the amplifier core input terminal (Fig. 1, 400 is coupled to both terminals of 100), the bypass circuit (Fig. 1, 400) including:
a first switch (Fig. 1, the switch in 400 directly coupled to N1, SW1) and a second switch (Fig. 1, the switch in 400 directly coupled to N2, SW2) coupled in series, the first switch being coupled to the amplifier core input terminal (Fig. 1, SW1 is coupled to the input terminal of 100) and the second switch being coupled to the bypass capacitor (Figs. 1 and 8, SW2 is coupled to 300, which comprises CR31);
a bypass circuit node (Fig. 5, N3) between the first switch and the second switch (Fig. 1, SW1 and SW2); and
a bypass switch coupled between the amplifier input terminal and the bypass circuit node.
Cho is silent regarding:
a bypass switch coupled between the amplifier input terminal and the bypass circuit node.
Lee discloses:
a bypass switch (Fig. 5A, 535) coupled between the amplifier input terminal (Fig. 5A, 511) and the bypass circuit node (Fig. 5A, node between 535 and 531).
Cho and Lee are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a bypass switch in Cho’s design in order to enable a bypass mode in accordance with Lee’s design.
Regarding claim 15,
The invention of claim 12, wherein the amplifier core (Fig. 1, 100) includes a degeneration terminal (Fig. 8, terminal of L1), and further including a degeneration inductor (Fig. 1, L1) coupled between the degeneration terminal and a reference potential [See paragraph [0078], “A gate of the first transistor M1 may be connected to the input matching circuit 200 through the DC blocking capacitor CB1 and may be connected to a terminal of a first bias voltage VB1 through a resistor R1. An inductor L1 may be connected between ground and a source of the first transistor M1. For example, the inductor L1 may be a degeneration inductor for enhancing linearity.”].
Regarding claim 16,
The invention of claim 12, wherein the bypass circuit node is configured to be coupled to a matching inductor (Fig. 1, 200 comprises a matching inductor and is coupled to N3, [See paragraph [0021], “The input matching circuit may include an input inductor connected between the input terminal and the first connection node and configured to perform impedance matching between the input terminal and the amplifying circuit”]).
Regarding claim 18,
The invention of claim 12, wherein the bypass circuit node is coupled to an AC ground (Fig. 5, N3 is coupled to ground).
Regarding claim 19,
The invention of claim 12, wherein the amplifier core includes a field-effect transistor stack (Fig. 8, the transistors are stacked, [See paragraph [0077], “the amplifying circuit 100 may include a first transistor M1, a second transistor M2, and a third transistor M3, which are stacked between the first connection node N1 and the second connection node N2”].
Claims 26 – 31, 33, and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Ayranci et al. (US 20220393650 A1), hereinafter Ayranci.
Regarding independent claim 26, Cho discloses:
An amplifier (See Fig. 1) including:
an amplifier input terminal (Fig. 1, IN) configured to receive a radio-frequency (RF) signal (Fig. 1, IN is configured to receive a signal);
an amplifier core (Fig. 1, 100) including:
an amplifier core input terminal (Fig. 1, terminal of 100 coupled to CB1) configured to receive the RF signal through an input matching inductor (Fig. 1, 200 [See paragraph [0021], “The input matching circuit may include an input inductor connected between the input terminal and the first connection node and configured to perform impedance matching between the input terminal and the amplifying circuit, and a variable attenuation circuit connected in series to the input inductor and configured to adjust a signal damping ratio in conjunction with an amplification ratio of the amplifying circuit.”]) coupled between the amplifier input terminal (Fig. 1, IN) and the amplifier core input terminal (Fig. 1, terminal of 100 coupled to CB1); and
an amplified-signal terminal (Fig. 1, terminal of 100 coupled to N2);
a first bypass capacitor (Fig. 8, C32) coupled to the amplified-signal terminal (Fig. 1, terminal of 100 coupled to N2);
a first bypass switch coupled in parallel with the first bypass capacitor;
a bypass circuit (Fig. 1, 400) coupled between the bypass capacitor and the amplifier core input terminal (Fig. 1, 400 is coupled to the terminal of 100 that is coupled to N1), the bypass circuit (Fig. 1, 400) including:
a first switch (Fig. 1, the switch in 400 directly coupled to N1, SW1) and a second switch (Fig. 1, the switch in 400 directly coupled to N2, SW2) coupled in series, the first switch being coupled to the amplifier core input terminal (Fig. 1, SW1 is coupled to the input terminal of 100);
a bypass circuit node (Fig. 5, N3) between the first switch and the second switch (Fig. 1, SW1 and SW2);
a first matching capacitor (Fig. 5, C40) coupled to the bypass circuit node (Fig. 1, N3);
an amplifier output terminal (Fig. 1, OUT);
an output capacitor (Fig. 8, C31) coupled between the amplified-signal terminal and the amplifier output terminal (Fig. 8, C31 is coupled to OUT and the terminal of 100 coupled to N2);
a second matching capacitor coupled in parallel with the output capacitor;
a load inductor (Fig. 1, inductor in 300, [See paragraph [0085], “the output matching circuit 300 may include an output inductor L31, a variable resistor circuit R31, a variable capacitor circuit C31, and an output capacitor C32.”]) coupled to a common node (Fig. 1, N2) between the bypass capacitor and the output capacitor, the common node (Fig. 1, N2) being coupled to the amplified-signal terminal of the amplifier core (Fig. 1, N2 is coupled to the terminal of 100);
a mode switch coupled to the load inductor and configured to be coupled to a voltage source;
a second bypass capacitor coupled to a node between the node switch and the load inductor and to a reference potential; and
a second bypass switch coupled in parallel with the second bypass capacitor.
Cho is silent regarding:
a first bypass switch coupled in parallel with the first bypass capacitor;
a second matching capacitor coupled in parallel with the output capacitor;
a mode switch coupled to the load inductor and configured to be coupled to a voltage source;
a second bypass capacitor coupled to a node between the mode switch and the load inductor and to a reference potential; and
a second bypass switch coupled in parallel with the second bypass capacitor.
Ayranci discloses:
a first bypass switch (Fig. 3B, SwFB1) coupled in parallel with the first bypass capacitor;
a second matching capacitor (Fig. 3B, Cout) coupled in parallel with the output capacitor;
a mode switch (Fig. 3B, Sw2) coupled to the load inductor (Fig. 3B, L1) and configured to be coupled to a voltage source (Fig. 3B, VDD);
a second bypass capacitor (Fig. 3B, C1) coupled to a node (Fig. 3B, node coupled to VDD) between the mode switch (Fig. 3B, Sw2) and the load inductor (Fig. 3B, L1) and to a reference potential (Fig. 3B, VDD); and
a second bypass switch (Fig. 3B, Sw1) coupled in parallel with the second bypass capacitor (Fig. 3B, C1).
Cho and Ayranci are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include bypass switches and capacitors in Cho’s design in order to enable a bypass mode and provide DC blocking in accordance with Ayranci’s design.
Regarding claim 27,
The invention of claim 20, wherein the amplifier core (Fig. 1, 100) includes a degeneration terminal (Fig. 8, terminal of L1), and further including a degeneration inductor (Fig. 1, L1) coupled between the degeneration terminal and a reference potential [See paragraph [0078], “A gate of the first transistor M1 may be connected to the input matching circuit 200 through the DC blocking capacitor CB1 and may be connected to a terminal of a first bias voltage VB1 through a resistor R1. An inductor L1 may be connected between ground and a source of the first transistor M1. For example, the inductor L1 may be a degeneration inductor for enhancing linearity.”].
Regarding claim 28,
The invention of claim 20, wherein the load inductor is a variable inductor (the inductor is a variable inductor, [See paragraph [0022], “The output matching circuit may include an output inductor connected between a terminal of a power voltage and the second connection node at the output side of the amplifying circuit, a variable resistor circuit connected in parallel to the output inductor, a variable capacitor circuit connected between the second connection node and the output terminal, and an output capacitor connected between the output terminal and ground”].
Regarding claim 29,
The invention of claim 20, wherein the first matching capacitor is a variable capacitor (the matching capacitor is a variable capacitor, [See paragraph [0022], “The output matching circuit may include an output inductor connected between a terminal of a power voltage and the second connection node at the output side of the amplifying circuit, a variable resistor circuit connected in parallel to the output inductor, a variable capacitor circuit connected between the second connection node and the output terminal, and an output capacitor connected between the output terminal and ground”].
Regarding claim 30, Cho is silent regarding:
The invention of claim 20, wherein the second matching capacitor is a variable capacitor.
Ayranci discloses:
The invention of claim 20, wherein the second matching capacitor is a variable capacitor [See paragraph [0035], “A second terminal of the multi-mode inductor circuit 312 is coupled to a first terminal of an output capacitor C.sub.OUT, which may be adjustable, as shown, or have a fixed value.”].
Cho and Ayranci are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a variable capacitor in Cho’s design in order to provides DC blocking and output impedance matching for loads coupled to the output terminal in accordance with Ayranci’s design.
Regarding claim 31, Cho is silent regarding:
The invention of claim 20, wherein the bypass circuit node is configured to be selectably coupled to a matching inductor through a connecting switch.
Ayranci discloses:
The invention of claim 20, wherein the bypass circuit node (Fig. 3B, node in 316 coupled to SwFBN) is configured to be selectably coupled to a matching inductor (Fig. 3B, LSER) through a connecting switch (Fig. 3B, SwFBN).
Cho and Ayranci are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a connecting switch in Cho’s design in order to make a connection between the bypass circuit to a matching inductor in accordance with Ayranci’s design.
Regarding claim 33,
The invention of claim 20. wherein the bypass circuit node is coupled to an AC ground (Fig. 5, N3 is coupled to ground).
Regarding claim 34,
The invention of claim 20, wherein the amplifier core includes a field-effect transistor stack (Fig. 8, the transistors are stacked, [See paragraph [0077], “the amplifying circuit 100 may include a first transistor M1, a second transistor M2, and a third transistor M3, which are stacked between the first connection node N1 and the second connection node N2”].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE E PINERO whose telephone number is (703)756-4746. The examiner can normally be reached M-F 8:00 AM - 5:00 PM (ET).
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/JOSE E PINERO/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/ Supervisory Patent Examiner, Art Unit 2843