Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites the limitation "the solder" in line 1, however in claim 16, from which it depends, there is a first recitation of “at least one first interconnect on each first die and comprising solder” and also “solder comprising indium, copper, and tin” (emphasis examiner’s). Therefore, examiner is unable to determine which solder’s composition is being further limited in claim 20 and so the claim is unable to be examined on the merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 12-13 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pietambaram et al. (US20190393145A1, hereinafter Pietambaram).
Regarding claim 12, Pietambaram discloses a method of manufacturing an electronic package comprising:
receiving a first die over a carrier (Fig. 2 die 206 over substrate 202);
forming a first interconnect on the first die and comprising placing solder over or under a first metal feature having copper (Fig. 2 die 206 has via assembly 210 and figs. 5/7 illustrates solder cap layer 432 over leftmost via 710);
forming a second interconnect on the first die (Fig. 2 bridge die 205 connected to die 206 by via assembly 212) and comprising forming a second metal feature comprising copper (Fig. 7 second via 710 from the left), solder over or under the second metal feature (Figs. 5/7 solder cap layer 712 disposed over second via 710 from the left), and a layer between the solder and the second metal feature (Fig. 7 electromigration resistant cap layer 434), wherein the layer comprises iron (Par. 50 “the electromigration resistant cap layer 434 includes an…iron alloy”) and has a different material than material of the first interconnect (Par. 43 “base pad 404 is…formed with copper” which is a different material than an iron alloy); and
coupling a second die to the first die through the second interconnect (Fig. 2 bridge die 205 coupled to first die 206 through via assembly 212).
Regarding claim 13, Pietambaram discloses the method of claim 12, comprising
coupling the second die to a third die over the carrier and having the first and second interconnects, and coupling through a second interconnect of the third die (Par. 28 “FIG. 2 shows one example of a bridge die 205” and fig. 1 shows bridges 106 connecting plurality of devices 104).
Regarding claim 15, Pietambaram discloses the method of claim 12,
wherein forming the second interconnect comprises covering an intermediate assembly with the first and second metal features with a resist (Par. 27 “[t]hese features are formed with build-up techniques including, but not limited to, techniques that gradually build layers of the substrate, photolithograph the features or the like”);
exposing the second metal features through openings in the resist without exposing the first metal features; and placing the layer on the second metal features within the openings (Figs. 5/7 via 426 has electromigration layer 434 disposed upon it and as Pietambaram also teaches using photolithography construction techniques they teach the above claimed method).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Pietambaram (US20190393145A1) in view of Gamba et al. (US20210391266A1, hereinafter Gamba).
Regarding claim 1, Pietambaram discloses an electronic package, comprising:
a first die having at least one first interconnect with solder over or under a first metal feature (Fig. 2 die 206 has via assembly 210 and figs. 5/7 illustrates solder cap layer 432 over leftmost via 710); and
a second die having at least one second interconnect to the first die (Fig. 2 bridge die 205 connected to die 206 by via assembly 212), the second interconnect comprising a second metal feature (Fig. 7 second via 710 from the left), the second interconnect comprising solder and being over or under the second metal feature (Figs. 5/7 solder cap layer 712 disposed over second via 710 from the left), the second interconnect including a layer between the solder and the second metal feature (Fig. 7 electromigration resistant cap layer 434), wherein the layer comprises iron (Par. 50 “the electromigration resistant cap layer 434 includes an…iron alloy”) and has a different material than material of the first interconnect (Par. 43 “base pad 404 is…formed with copper” which is a different material than an iron alloy).
Pietambaram does not appear to teach
solder comprising indium.
Gamba teaches
solder comprising indium (Par. 64 “a low-temperature solder 166 may include indium).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Pietambaram with the teachings of Gamba because as both Pietambaram and Gamba teach suitable materials for use as a solder, it would have been obvious to substitute Pietambaram’s tin solder with Gamba’s indium solder to achieve the predictable result of soldering using indium.
Regarding claim 2, the combination of Pietambaram and Gamba teaches the electronic package of claim 1,
wherein the layer further comprises cobalt (Pietambaram par. 44 “the electromigration resistant via includes, but is not limited to one or more of a nickel or nickel alloy via, a cobalt alloy via, an iron alloy via” and so the combination of Pietambaram and Gamba would teach to a person of ordinary skill in the art an alloy comprising both iron and cobalt).
Regarding claim 3, the combination of Pietambaram and Gamba teaches the electronic package of claim 1,
wherein the layer further comprises nickel (Pietambaram par. 44 “the electromigration resistant via includes, but is not limited to one or more of a nickel or nickel alloy via, a cobalt alloy via, an iron alloy via” and so the combination of Pietambaram and Gamba would teach to a person of ordinary skill in the art an alloy comprising both iron and nickel).
Regarding claim 4, the combination of Pietambaram and Gamba teaches the electronic package of claim 1,
wherein the first interconnect is without an intermetallic compound (IMC) barrier layer between the solder and metal features on the first interconnect (The combination of Pietambaram and Gamba does not teach the use of an intermetallic compound barrier layer between the solder and leftmost via 710 as shown in Pietambaram figs. 5/7, see above rejection of claim 1).
Regarding claim 5, the combination of Pietambaram and Gamba teaches the electronic package of claim 1,
wherein the first interconnect comprises a first layer between the solder and first metal feature (Pietambaram fig. 7 leftmost via 710 has electromigration resistant cap layer 434 between it and solder cap layer 712),
wherein the layer of the second interconnect is a second layer (Pietambaram figs. 5/7 electromigration resistant cap layer 434 on the second via from the left 710 is a second layer), and
wherein the first layer is without iron (Pietambaram par. 44 “the electromigration resistant via includes, but is not limited to one or more of a nickel or nickel alloy via” which are both without iron).
Regarding claim 6, the combination of Pietambaram and Gamba teaches the electronic package of claim 5,
wherein the first layer comprises nickel and is a barrier layer (Pietambaram par. 44 “the electromigration resistant via includes, but is not limited to one or more of a nickel or nickel alloy via” and as it is electromigration resistant it would constitute a barrier).
Regarding claim 7, the combination of Pietambaram and Gamba teaches the electronic package of claim 1,
wherein the first interconnect comprises a first layer between the solder and first metal feature (Pietambaram fig. 7 leftmost via 710 has electromigration resistant cap layer 434 between it and solder cap layer 712),
wherein the layer of the second interconnect is a second layer (Pietambaram figs. 5/7 electromigration resistant cap layer 434 on the second via from the left 710 is a second layer), and
wherein the first layer comprises iron and a first material and the second layer comprises iron and a second material different than the first material (Pietambaram par. 44 “the electromigration resistant via includes, but is not limited to one or more of a nickel or nickel alloy via, a cobalt alloy via, an iron alloy via” and so the combination of Pietambaram and Gamba teaches the electromigration resistant cap layer 434 within the leftmost via to comprise an alloy of iron and nickel and also teaches the electromigration resistant cap layer 434 within the second via from the left to comprise an alloy of iron and cobalt).
Regarding claim 8, the combination of Pietambaram and Gamba teaches the electronic package of claim 7,
wherein the first layer comprises iron and one of nickel and cobalt, and the second layer comprises iron and the other of nickel and cobalt (Pietambaram par. 44 “the electromigration resistant via includes, but is not limited to one or more of a nickel or nickel alloy via, a cobalt alloy via, an iron alloy via” and so the combination of Pietambaram and Gamba teaches the electromigration resistant cap layer 434 within the leftmost via to comprise an alloy of iron and nickel and also teaches the electromigration resistant cap layer 434 within the second via from the left to comprise an alloy of iron and cobalt).
Regarding claim 9, the combination of Pietambaram and Gamba teaches the electronic package of claim 1, comprising
multiple first interconnects and multiple second interconnects (Pietambaram fig. 2 first contact array 208 and second contact array 209 both have a plurality of interconnects), and
wherein the multiple first interconnects have a pitch greater than a pitch of the multiple second interconnects (Pietambaram fig. 2 first contact array 208 has an increased contact density compared to the contact density of second contact array 209).
Regarding claim 10, the combination of Pietambaram and Gamba teaches the electronic package of claim 1,
wherein a thickness of the layer is approximately 1 micron or thicker (Pietambaram par. 51 “the layer 434 is…around 15 microns” which is greater than 1 micron).
Regarding claim 11, the combination of Pietambaram and Gamba teaches the electronic package of claim 1,
wherein the second die comprises an interconnect to a third die (Fig. 1 bridges 106 connecting plurality of devices 104), wherein the second die is at least one of a bridge die, an embedded multi-die interconnect bridge (EMIB), or a chiplet, and wherein the second die couples the first die to the third die (Par. 28 “FIG. 2 shows one example of a bridge die 205” and fig. 1 shows bridges 106 connecting plurality of devices 104).
Regarding claim 16, Pietambaram teaches an electronic system, comprising:
multiple first dice (Fig. 1 plurality of devices 104);
at least one first interconnect on each first die and comprising solder over or under a first metal feature (Fig. 2 die 206, one of the devices 104, has via assembly 210 and figs. 5/7 illustrates solder cap layer 432 over leftmost via 710);
at least one second interconnect on each first die and comprising a second metal feature (Fig. 7 second via 710 from the left), solder over or under the second metal feature (Figs. 5/7 solder cap layer 712 disposed over second via 710 from the left, par. 43 “[t]he solder cap layer 412 includes, but is not limited to, tin or tin alloys”), and a layer between the solder and the second metal feature (Fig. 7 electromigration resistant cap layer 434), wherein the layer comprises one of: (1) nickel, (2) iron and cobalt, and (3) iron and nickel (Par. 50 “the electromigration resistant cap layer 434 includes an…iron alloy”), and wherein the layer has a different material than material of the first interconnect (Par. 43 “base pad 404 is…formed with copper” which is a different material than an iron alloy); and
a second die coupled to the second interconnects of multiple first dice (Fig. 2 bridge die 205 connected to die 206 by via assembly 212).
Pietambaram does not appear to teach
solder comprising indium
Gamba teaches
solder comprising indium (Par. 64 “a low-temperature solder 166 may include indium).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Pietambaram with the teachings of Gamba because as both Pietambaram and Gamba teach suitable materials for use as a solder, it would have been obvious to substitute Pietambaram’s tin solder with Gamba’s indium solder to achieve the predictable result of soldering using indium.
Regarding claim 17, the combination of Pietambaram and Gamba teaches the electronic system of claim 16,
wherein at least one of the first interconnects or at least one of the second interconnects or both has multiple layers comprising at least one layer over the solder and at least one layer under the solder, wherein the layer over the solder has a different material than a material of the layer under the solder (Fig. 5 illustrates via 426 with electromigration resistance cap 434 and solder cap 432 disposed sequentially upon it. Fig. 2 die 206 would have a plurality of contact pad for first contact array 208 to contact. While Pietambaram does not explicitly disclose a second electromigration resistance cap layer between the solder and the plurality of contact pads for die 206, the primary function of electromigration resistance cap layer is to minimize electromigration between the solder and contacts. A duplication of an electromigration resistance cap layer to form a second electromigration resistance cap layer between the solder and the plurality of contact pads on die 206 would not provide any new or unexpected results as the primary function of minimizing electromigration between the solder and contacts is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore duplicate electromigration resistance cap layer to form a second electromigration resistance cap layer between the solder and the plurality of contact pads on die 206, see MPEP 2144.04(VI)(B)).
Regarding claim 18, the combination of Pietambaram and Gamba teaches the electronic system of claim 17,
wherein both layers above and below the solder on a same interconnect comprises iron (Pietambaram par. 44 “the electromigration resistant via includes, but is not limited to one or more of a nickel or nickel alloy via, a cobalt alloy via, an iron alloy via” and so it can comprise an iron alloy), and wherein the layer under the solder comprises a first additional material different than a second additional material of the layer over the solder (Pietambaram par. 44 “the electromigration resistant via includes, but is not limited to one or more of a nickel or nickel alloy via, a cobalt alloy via, an iron alloy via” and so Pietambaram teaches a first electromigration resistance cap layer above the solder comprising an iron nickel alloy and a second electromigration resistance cap layer, see above rejection of claim 17, comprising an iron cobalt alloy).
Regarding claim 19, the combination of Pietambaram and Gamba teaches the electronic system of claim 16,
wherein the layer is a barrier layer (Fig. 2 electromigration resistance cap layer 434 is a barrier to electromigration), and the system comprises a Cu layer between the barrier layer and the solder (Pietambaram teaches in par. 16 that “inter-metallic compounds (IMCs, such as alloys of copper and tin)” are formed due to electromigration. Therefore, while not explicitly shown in a figure, Pietambaram teaches that a copper layer forms between electromigration resistance cap layer 434 and solder cap layer 432. Examiner notes that while electromigration resistance cap layer 434 minimizes this growth, it does not prevent it outright and so the copper layer is still present).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Pietambaram (US20190393145A1).
Regarding claim 14, Pietambaram teaches the method of claim 12, comprising
forming multiple first interconnects on the first die with a pitch greater than 25 microns and multiple second interconnects on the first die with a pitch equal to or less than 25 microns (While Pietambaram does not explicitly teach pitch ranges, in par. 31 they teach “variations in density such as the fine pitch of the via assemblies 212 (and accordingly dense packing of the via assemblies 212) relative to the coarse pitch of the via assemblies 210 (or less dense packing of the via assemblies 210).” Therefore, as the only difference between Pietambaram and the claimed invention is a relative recitation of dimensions and nothing within the disclosure indicates that a device having the claimed dimensions would perform differently than Pietambaram, such a recitation of relative dimensions is not enough to be patentably distinct, see MPEP 2144.04(IV)(A)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Iuchi et al. (US20200376808A1) teaches a method of inhibiting intermetallic compound growth through specific under barrier metals.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COLE LEON LINDSEY/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812