Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see sections titled “Rejections Under 35 U.S.C. 102” and “Rejections Under 35 U.S.C. 103,” filed 05/19/2026, with respect to the rejection of claims 1-20 have been fully considered and are persuasive. The rejection of claims 1-20 has been withdrawn.
Applicant’s arguments, see sections titled “Rejections Under 35 U.S.C. 102” and “Rejections Under 35 U.S.C. 103,” filed 05/19/2026, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the combination of Hua (US20040262778A1) and Pietambaram et al. (US20170287838A1, hereinafter Pietambaram).
Regarding claim 1, Hua teaches an electronic package, comprising:
a first die (Fig. 3 device 210) having at least one interconnect via structure embedded within a dielectric material (Fig. 3 plurality of interconnect structures 215), the at least one interconnect via structure comprising:
a first portion comprising a metal (Fig. 3 bump 230 which par. 28 teaches that “[s]uitable conductive materials for the bump include…copper”);
a second portion directly on the first portion, the second portion comprising iron (Fig. 3 first electromigration barrier material 235 and par. 23 teaches that “[s]uitable barrier materials include…iron”);
a third portion directly on the second portion, the third portion comprising a solder material (Fig. 3 solder joint 240, and par. 14 teaches that the “solder joint may be formed from a solder bump”);
a fourth portion directly on the third portion, the fourth portion comprising iron (Fig. 3 second electromigration barrier material 245 and par. 23 teaches that “[s]uitable barrier materials include…iron”); and
a fifth portion directly on the fourth portion, the fifth portion comprising a metal (Fig. 3 pad 250, and par. 29 teaches that “the pads may contain copper or a copper-containing material”); and
a second die directly on the fifth portion (Fig. 3 substrate 260 is directly on pad 250), and wherein the at least one interconnect via structure is coupled to the first die and to the second die (Fig. 3 interconnects 215 couple device 210 and substrate 260).
Hua does not appear to teach
wherein the second die is embedded within the dielectric material.
Pietambaram teaches
wherein the second die is embedded within the dielectric material (Fig. 1 bridge die 130 embedded within same dielectric 110 that the interconnect to dies 120/121 are embedded within).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hua with the teachings of Pietambaram because Pietambaram’s bridge die configuration can “provide a chip-to-chip connection between the electronic components” above which allows for more dense and complex configurations (Pietambaram par. 44).
See below for full claims mapping.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-8, 10-13, 16-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hua (US20040262778A1) in view of Pietambaram (US20170287838A1).
Regarding claim 1, Hua teaches an electronic package, comprising:
a first die (Fig. 3 device 210) having at least one interconnect via structure embedded within a dielectric material (Fig. 3 plurality of interconnect structures 215), the at least one interconnect via structure comprising:
a first portion comprising a metal (Fig. 3 bump 230 which par. 28 teaches that “[s]uitable conductive materials for the bump include…copper”);
a second portion directly on the first portion, the second portion comprising iron (Fig. 3 first electromigration barrier material 235 and par. 23 teaches that “[s]uitable barrier materials include…iron”);
a third portion directly on the second portion, the third portion comprising a solder material (Fig. 3 solder joint 240, and par. 14 teaches that the “solder joint may be formed from a solder bump”);
a fourth portion directly on the third portion, the fourth portion comprising iron (Fig. 3 second electromigration barrier material 245 and par. 23 teaches that “[s]uitable barrier materials include…iron”); and
a fifth portion directly on the fourth portion, the fifth portion comprising a metal (Fig. 3 pad 250, and par. 29 teaches that “the pads may contain copper or a copper-containing material”); and
a second die directly on the fifth portion (Fig. 3 substrate 260 is directly on pad 250), and wherein the at least one interconnect via structure is coupled to the first die and to the second die (Fig. 3 interconnects 215 couple device 210 and substrate 260).
Hua does not appear to teach
wherein the second die is embedded within the dielectric material.
Pietambaram teaches
wherein the second die is embedded within the dielectric material (Fig. 1 bridge die 130 embedded within same dielectric 110 that the interconnect to dies 120/121 are embedded within).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hua with the teachings of Pietambaram because Pietambaram’s bridge die configuration can “provide a chip-to-chip connection between the electronic components” above which allows for more dense and complex configurations (Pietambaram par. 44).
Regarding claim 2, the combination of Hua and Pietambaram teaches the electronic package of claim 1,
wherein at least one of the second portion or the fourth portion the layer further comprises cobalt (Hua par. 23 teaches that “[s]uitable barrier materials include, but are not limited to, nickel, cobalt, titanium, iron, and combinations thereof” and so either first/second electromigration barrier material 235/245 may further comprise cobalt).
Regarding claim 3, the combination of Hua and Pietambaram teaches the electronic package of claim 1,
wherein at least one of the second portion or the fourth portion the layer further comprises nickel (Hua par. 23 teaches that “[s]uitable barrier materials include, but are not limited to, nickel, cobalt, titanium, iron, and combinations thereof” and so either first/second electromigration barrier material 235/245 may further comprise nickel).
Regarding claim 5, the combination of Hua and Pietambaram teaches the electronic package of claim 1,
wherein the at least one interconnect via structure extends between the first die and the second die (Hua fig. 3 plurality of interconnect structures 215 that extend between device 210 and substrate 260).
Regarding claim 6, the combination of Hua and Pietambaram teaches the electronic package of claim 1,
wherein at least one of the second portion or the fourth portion comprises nickel and is a barrier layer (Hua par. 23 teaches that “[s]uitable barrier materials include, but are not limited to, nickel, cobalt, titanium, iron, and combinations thereof” and so either first/second electromigration barrier material 235/245 may further comprise nickel and it is an electromigration barrier layer).
Regarding claim 7, the combination of Hua and Pietambaram teaches the electronic package of claim 1,
wherein at least one of the first portion or the fifth portion comprises copper or copper alloys (Hua fig. 3 bump 230 which par. 28 teaches that “[s]uitable conductive materials for the bump include…copper”).
Regarding claim 8, the combination of Hua and Pietambaram teaches the electronic package of claim 7,
wherein at least one of the second portion or the fourth portion further comprises one of nickel or cobalt (Hua par. 23 teaches that “[s]uitable barrier materials include, but are not limited to, nickel, cobalt, titanium, iron, and combinations thereof” and so either first/second electromigration barrier material 235/245 may further comprise cobalt or nickel).
Regarding claim 10, the combination of Hua and Pietambaram teaches the electronic package of claim 1,
wherein a thickness of at least one of the second portion or the fourth portion is approximately 1 micron or thicker (Hua par. 23 teaches that “[t]he barrier materials may include layers, caps, or other structures having a thickness between…0.05 to 10 μm” which overlaps the claimed range, see MPEP 2144.05(I)).
Regarding claim 11, the combination of Hua and Pietambaram teaches the electronic package of claim 1,
wherein the second die comprises an interconnect to a third die, wherein the second die is at least one of a bridge die, an embedded multi-die interconnect bridge (EMIB), or a chiplet, and wherein the second die couples the first die to the third die (Pietambaram teaches the use of a bridge die, see claim 1. Therefore, the combination of Hua and Pietambaram teaches the use of a third interconnect on the second die which allows it to act as a bridge die, see Pietambaram fig. 1).
Regarding claim 12, Hua teaches a method of manufacturing an electronic package comprising:
forming an interconnect (Fig. 3 plurality of interconnect structures 215) on the first die (Fig. 3 device 210) comprising:
forming a first metal feature having copper (Fig. 3 bump 230 which par. 28 teaches that “[s]uitable conductive materials for the bump include…copper”);
forming a first layer comprising iron on the first metal feature (Fig. 3 first electromigration barrier material 235 and par. 23 teaches that “[s]uitable barrier materials include…iron”);
forming a solder material on the first layer (Fig. 3 solder joint 240, and par. 14 teaches that the “solder joint may be formed from a solder bump”);
forming a second layer comprising iron on the solder material (Fig. 3 second electromigration barrier material 245 and par. 23 teaches that “[s]uitable barrier materials include…iron”);
forming a second metal feature on the second layer (Fig. 3 pad 250, and par. 29 teaches that “the pads may contain copper or a copper-containing material”); and
coupling a second die (Fig. 3 substrate 260 is directly on pad 250) to the first die through the interconnect (Fig. 3 interconnects 215 couple device 210 and substrate 260).
Hua does not appear to teach
receiving a first die over a carrier.
Pietambaram teaches
receiving a first die over a carrier (Figs. 4A-4K illustrate the use of a carrier die 442 which pars. 56 and 69 teaches that the use of a carrier allows “separation of a manufactured non-singulated molded bridge substrate from the carrier” after processing which allows for “multiple bridges [to] be manufactured simultaneously”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hua with the teachings of Pietambaram because the use of a carrier allows “separation of a manufactured non-singulated molded bridge substrate from the carrier” after processing to simplify the process which allows for “multiple bridges [to] be manufactured simultaneously” (Pietambaram pars. 56/69).
Regarding claim 13, the combination of Hua and Pietambaram teaches the method of claim 12.
The combination of Hua and Pietambaram do not appear to teach
coupling the second die to a third die over the carrier and having the first and second interconnects, and coupling through a second interconnect of the third die.
Pietambaram further teaches
coupling the second die to a third die over the carrier and having the first and second interconnects, and coupling through a second interconnect of the third die (Fig. 1 teaches bridge die 131 coupling together electronic components 120 and 121 with a plurality of interconnects between each component and the bridge die).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because Pietambaram’s bridge die configuration can “provide a chip-to-chip connection between the electronic components” above which allows for more dense and complex configurations (Pietambaram par. 44).
Regarding claim 16, Hua teaches an electronic system, comprising:
a first die (Fig. 3 device 210);
at least one interconnect on the first die (Fig. 3 plurality of interconnect structures 215) and comprising:
a first portion comprising a metal (Fig. 3 bump 230 which par. 28 teaches that “[s]uitable conductive materials for the bump include…copper”);
a second portion directly on the first portion, the second portion comprising iron (Fig. 3 first electromigration barrier material 235 and par. 23 teaches that “[s]uitable barrier materials include…iron”);
a third portion directly on the second portion, the third portion comprising a solder material (Fig. 3 solder joint 240, and par. 14 teaches that the “solder joint may be formed from a solder bump”);
a fourth portion directly on the third portion, the fourth portion comprising iron (Fig. 3 second electromigration barrier material 245 and par. 23 teaches that “[s]uitable barrier materials include…iron”); and
a fifth portion directly on the fourth portion, the fifth portion comprising a metal (Fig. 3 pad 250, and par. 29 teaches that “the pads may contain copper or a copper-containing material”); and
a second die coupled to the interconnects the first die (Fig. 3 substrate 260 is directly on pad 250 and interconnects 215 couple device 210 and substrate 260).
Hua does not appear to teach
multiple first dice coupled to a second die which is coupled to the interconnects of the multiple first dice.
Pietambaram teaches
multiple first dice coupled to a second die which is coupled to the interconnects of the multiple first dice (Fig. 1 teaches bridge die 131 coupling together electronic components 120 and 121 with a plurality of interconnects between each component and the bridge die).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hua with the teachings of Pietambaram because Pietambaram’s bridge die configuration can “provide a chip-to-chip connection between the electronic components” above which allows for more dense and complex configurations (Pietambaram par. 44).
Regarding claim 17, the combination of Hua and Pietambaram teaches the electronic system of claim 16,
wherein at least one of the second portion or the fourth portion has a different material than the other one of the second portion or the fourth portion (Hua par. 23 teaches that “[s]uitable barrier materials include, but are not limited to, nickel, cobalt, titanium, iron, and combinations thereof” and so the combination of Hua and Pietambaram teaches embodiments in which the first electromigration barrier material 235 further comprises cobalt and second electromigration barrier material 245 further comprises nickel).
Regarding claim 19, the combination of Hua and Pietambaram teaches the electronic system of claim 16,
wherein at least one of the second portion or the fourth portion is a barrier layer Hua par. 23 teaches that “[s]uitable barrier materials include, but are not limited to, nickel, cobalt, titanium, iron, and combinations thereof” and so the first/second electromigration barrier material 235/245 are both barriers).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Hua and Pietambaram as applied to claim 12 above, and further in view of Collins et al. (US20190206792A1, hereinafter Collins).
Regarding claim 14, the combination of Hua and Pietambaram teaches the method of claim 12.
The combination of Hua and Pietambaram does not appear to teach
forming multiple first interconnects on the first die with a pitch greater than 25 microns and forming multiple second interconnects on the first die with a pitch equal to or less than 25 microns.
Collins teaches
forming multiple first interconnects on the first die with a pitch greater than 25 microns (Par. 26 teaches “the average pitch between bumps 32 of region 41 may be in a range of from about 75 microns to about 150 microns” which overlaps the claimed range, see MPEP 2144.05(I)) and forming multiple second interconnects on the first die with a pitch equal to or less than 25 microns (Par. 26 teaches “the average pitch between bumps 30 of region 43, may be in a range of from about 20 microns to about 70 microns” which overlaps the claimed range, see MPEP 2144.05(I)).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Hua and Pietambaram with the teachings of Collins because, as the combination of Hua and Pietambaram do not explicitly teach pitch ranges for use in a bridge die, this would motivate a person of ordinary skill in the art to seek out references such as Collins who do explicitly teach pitch ranges for use in a bridge die.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Hua and Pietambaram as applied to claim 16 above, and further in view of Unruh et al. (US20170287860A1, hereinafter Unruh).
Regarding claim 20, the combination of Hua and Pietambaram teaches the electronic system of claim 16.
The combination of Hua and Pietambaram does not appear to teach
wherein the solder material comprises at least one of nickel, tungsten, or phosphorous.
Unruh teaches
wherein the solder material comprises at least one of nickel, tungsten, or phosphorous (Par. 10 teaches that “FIGS. 1A-1D show a cross-section schematic view of formation of a solder bump 121 using an electroless nickel or nickel alloy/palladium/tin or tin alloy (ENEPET) stack in accordance with embodiments of the disclosure”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Hua and Pietambaram with the teachings of Unruh because as both Hua and Unruh teach suitable materials for use as a solder bump, it would have been obvious to substitute Hua’s tin solder with Unruh’s solder containing nickel to achieve the predictable result of forming a solder bump containing nickel.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights