Prosecution Insights
Last updated: October 02, 2026
Application No. 18/087,811

METHOD OF MANUFACTURING SEMICONDUCTOR CHIP INCLUDING FORMING DICING GROOVES AND SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Dec 23, 2022
Priority
Sep 05, 2022 — RE 10-2022-0112433
Examiner
PETERSON, ERIK T
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK hynix Inc.
OA Round
4 (Non-Final)
76%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
283 granted / 370 resolved
+8.5% vs TC avg
Moderate +11% lift
Without
With
+11.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
47 currently pending
Career history
413
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
44.4%
+4.4% vs TC avg
§102
20.6%
-19.4% vs TC avg
§112
29.1%
-10.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 370 resolved cases

Office Action

§102 §103
DETAILED ACTION This action is responsive to the amendment filed May 11, 2026. The amendment has been entered. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered. Claim Rejections - 35 USC § 102 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 1, 6-9, 11-12, and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han et al. (US 2020/0091100), of record. (Re Claim 1) Han teaches a method of manufacturing a semiconductor chip comprising (see Figs. 1-9 and corresponding text): forming a substrate that includes an active layer (active layer is from/above 100 up through and including 130, alternatively the active layer may further include 141a and 151, the claimed active layer is not well defined) and an organic layer (153 is polyimide) on a semiconductor base (100); and forming dicing grooves by recessing parts of the active layer (Fig. 5C), the dicing grooves being extended to face each other along first dicing lines from points at which the first dicing lines and second dicing lines intersect (see Fig. 2), wherein the substrate includes a chip region (10) and a scribe lane region (20), the scribe lane region surrounding the chip region (Figs. 1-2), wherein the organic layer is formed on the active layer in a shape comprising an opening portion, wherein the organic layer is formed so that the opening portion overlaps the scribe lane region to surround the chip region, and exposes a part of the active layer and the dicing grooves (see Fig. 5H, organic layer 153 having an opening portion OP2 (see OP portion in Fig. 2) wherein several parts of the active layer are exposed in the opening portion, referring to Figs. 1 and 2, the opening portion OP/OP2 overlaps the scribe lane region 20 and surrounds every chip region 10 as the opening portion is patterned along every scribe lane in each direction), and wherein the opening portion (OP/OP2) continuously extends along all of the first and second dicing lines (the opening portion OP/OP2 continually extends, for a distance, locally, along all of the first and second dicing lines, see Figs. 1-2, OP is located at every intersection, the claim language does not require the opening to be formed as one single continuous opening across the entire wafer/coextensive with every dicing line, and may be met by a perforated opening, e.g. an opening comprising discrete, spaced apart parts, each portion of the opening being locally continuous, as claimed). (Re Claim 6) wherein the dicing grooves are further extended along the second dicing lines and have cross shapes when the dicing grooves are viewed on a plane (Fig. 2). (Re Claim 7) wherein the dicing grooves are formed to be spaced apart from each other along the first dicing lines (Fig. 2). (Re Claim 8) wherein the recessing of the parts of the active layer is performed so that remaining portions of the active layer remain between bottoms of the dicing grooves and the semiconductor base (Fig. 5H). (Re Claim 9) wherein the opening portion of the organic layer is extended along the first and second dicing lines so that the dicing grooves and the parts of the active layer disposed between the dicing grooves are exposed (see Figs. 2, 5H, and 6). (Re Claim 11) Han teaches a method of manufacturing a semiconductor chip, comprising (see Figs. 1-9 and corresponding text): forming a substrate that includes an active layer (active layer is from/above 100 up through and including 130, alternatively the active layer may further include 141a and 151, the claimed active layer is not well defined) and an organic layer (153 is polyimide) on a semiconductor base (100), the substrate further includes first and second scribe lane regions that intersect to partition chip regions (Figs. 1-2); and forming dicing grooves that are extended to face each other in a direction in which the first scribe lane regions are extended from points at which the first and second scribe lane regions intersect, wherein the forming of the dicing grooves comprises recessing parts of the active layer (see Figs. 2, 5C, 5H), wherein the organic layer is formed on the active layer in a shape comprising an opening portion, and wherein the organic layer is formed so that the opening portion (OP in Fig. 2, OP2 in Fig. 5H) overlaps the first and second scribe lane regions (20) to surround the chip regions (10), and exposes a part of the active layer and the dicing grooves (see Fig. 5H, organic layer 153 having an opening portion wherein several parts of the active layer are exposed in the opening portion, referring to Figs. 1, 2 and 5H, the opening portion OP/OP2 overlaps the scribe lane region 20 and surrounds every chip region 10 as the opening portion is patterned along every scribe lane in each direction), wherein the dicing grooves are formed at points which first dicing lines and second dicing lines intersect (see Figs. 1-2, 5C), and wherein the opening portion (OP/OP2) continuously extends along all of the first and second dicing lines (the opening portion OP/OP2 continually extends, for a distance, locally, along all of the first and second dicing lines, see Figs. 1-2, OP is located at every intersection, the claim language does not require the opening to be formed as one single continuous opening across the entire wafer/coextensive with every dicing line, and may be met by a perforated opening, e.g. an opening comprising discrete, spaced apart parts, each portion of the opening being locally continuous, as claimed). (Re Claim 12) wherein: each of the dicing grooves is formed to be disposed adjacent to corners of the chip region (Figs. 1-2). (Re Claim 17) wherein the dicing grooves are further extended along the second scribe lane regions and have cross shapes when the dicing grooves are viewed on a plane (Figs. 1-2). (Re Claim 18) wherein the dicing grooves are formed to be spaced apart from each other along the first scribe lane regions (Figs. 1-2). (Re Claim 19) wherein the recessing of the parts of the active layer is performed so that remaining portions of the active layer remain between bottoms of the dicing grooves and the semiconductor base (Fig. 5H). (Re Claim 20) wherein the opening portion of the organic layer is extended along the first and second scribe lane regions so that the dicing grooves and the part of the active layer disposed between the dicing grooves are exposed (see Figs. 2, 5H, and 6). Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 2-5 and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. as applied above and further in view of Fukuyo et al. (US 2004/0002199) and Ono et al. (US 2020/0294934). (Re Claims 2 and 13) further comprising: forming modified patterns (SP) within the semiconductor base; and dicing the substrate into semiconductor chips by propagating cracks into the substrate from the modified patterns (Figs. 5H-5I and ¶¶73-75 describe a conventional stealth dicing process). (Re Claims 3 and 14) wherein some of the modified patterns are formed to overlap the dicing grooves (Fig. 5H). (Re Claims 4 and 15) wherein the modified patterns are formed to be aligned along the first and second dicing lines/scribe lane regions. (Re Claims 5 and 16) wherein the forming of the modified patterns comprises sequentially radiating a laser light into parts of the semiconductor base at which the modified patterns are to be disposed. Han teaches a conventional stealth dicing technique is used in Figs. 5H-5I and ¶¶73-75 where a modified/damaged region SP is formed with a laser below the dicing groove but is silent regarding cracks and specifically aligned along the dicing/scribe lines as Han only shows a single modified region. A PHOSITA would be motivated to look to related stealth dicing art to provide additional details of this well known dicing technique. Related art from Fukuyo teaches forming a plurality of modified regions along the center of the dicing lines and that cracks initiate from the modified regions thereby facilitating singulation (see Figs. 1-6, 8-15, 35-39, 44-47, 44-66, 96-100 and supporting text). Related art from Ono similarly teaches forming the modified regions along the center of the dicing lines and that cracks initiate from the modified regions allowing singulation (see Figs. 1-10 and supporting text). A PHOSITA would find it obvious to perform the conventional stealth dicing disclosed by Han according to the well known processes disclosed by Fukuyo and Ono wherein the modified regions are formed along each dicing line in each direction and cracks initiate from the modified regions allowing for singulation. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (Re Claim 10) wherein: the opening portion of the organic layer is extended along the first and second dicing lines, and the recessing of the parts of the active layer comprises: forming a mask pattern that covers the organic layer and that exposes the parts of the active layer; and etching the parts of the active layer that are exposed to the mask pattern. In Han’s process according to Fig. 5A-5I, Han is silent regarding an additional mask on the organic layer and etching the active layer through the mask, however Han teaches in Figs. 18A-18D and ¶¶101-116, an alternative patterning strategy to the technique used in Figs. 5B-5G wherein a mask Mpc is formed on the organic layer 153 and then the active layer (layer between 100 and 130) is etched. A PHOSITA would find it obvious to use this alternative technique for the advantages recognized by Han (¶116). Response to Arguments Applicant's arguments have been fully considered but they are not persuasive. Applicant argues Han does not teach the amended claims, specifically with respect to the opening portion continuously extends along all of the first and second dicing lines. The Examiner respectfully disagrees. The opening portion OP/OP2 continually extends, for a distance, locally along all of the first and second dicing lines, see Figs. 1-2. The opening OP is located at every intersection. The claim language does not require the opening to be formed as one single continuous or contiguous opening across the entire wafer and/or coextensive with every dicing line. The opening portion may be met by a perforated opening, e.g. an opening comprising discrete, spaced apart regions, such that each part of the opening is locally continuous, as claimed. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches dicing processes using an organic layer, e.g. photoresist, with the claimed opening. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
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Prosecution Timeline

Show 5 earlier events
Jan 16, 2026
Request for Continued Examination
Jan 27, 2026
Response after Non-Final Action
Feb 11, 2026
Non-Final Rejection mailed — §102, §103
May 11, 2026
Response Filed
Jul 16, 2026
Final Rejection mailed — §102, §103
Aug 26, 2026
Applicant Interview (Telephonic)
Aug 26, 2026
Examiner Interview Summary
Sep 16, 2026
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

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Patent 12707935
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3y 2m to grant Granted Aug 11, 2026
Patent 12672497
WAFER WITH TEST STRUCTURE AND METHOD OF DICING WAFER
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Patent 12660541
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4y 0m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
76%
Grant Probability
88%
With Interview (+11.0%)
2y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 370 resolved cases by this examiner. Grant probability derived from career allowance rate.

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