DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “about” in claims 16 and 19 is a relative term which renders the claim indefinite. The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
For the purpose of examination, this term is omitted in claims 16 and 19, and the ranges are rigorously defined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ju et. al., US. Pat. Pub. 2021/0343713, hereafter Ju.
Regarding claim 1, Ju discloses (Figs 24-28, see Figs 28, 27C) an integrated circuit comprising:
a first semiconductor device [202A] having a first semiconductor region [208A] extending in a first direction between a first source region [310A] and a first drain region [310A], and a first gate structure [374A] extending in a second direction over the first semiconductor region [208A] ([220’]);
a second semiconductor device [202B] having a second semiconductor region [208B] extending in the first direction between a second source region [310B] and a second drain region [310B], and a second gate structure [374B] extending in the second direction over the second semiconductor region [208B] ([220’]); and
a gate cut [270B] between the first gate structure [374A] and the second gate structure [374B], the gate cut comprising
a first dielectric layer [262] along edges of the gate cut [270B],
a dielectric fill [264] on the first dielectric layer [262], and
a second dielectric layer [266] (labels in Fig. 27) on a top surface of the dielectric fill [264],
wherein the first dielectric layer [262] has a higher dielectric constant than the dielectric fill [264] (par. [0028], layer [262] can be silicon nitride, which has a dielectric constant above 6, while layer [264] can be silicon oxide with the dielectric constant of about 3.9).
Regarding claim 2, Ju further discloses wherein the first dielectric layer [264] directly contacts the first gate structure [374A] and the second gate structure [374B] (gate dielectric [372], see Fig. 24, is a part of both gate structures [374A,B]).
Regarding claim 3, Ju further discloses (par. [0028]) wherein the first dielectric layer [262] comprises silicon and nitrogen (e.g., a silicon nitride layer) and the dielectric fill comprises silicon and oxygen (silicon oxide).
Regarding claim 4, Ju further discloses (Fig. 27B) wherein the first gate structure [374A] includes a first gate dielectric [372] around the first semiconductor region [220’], and the second gate structure [374B] includes a second gate dielectric [372] around the second semiconductor region [220’].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ju et. al., US. Pat. Pub. 2021/0343713, hereafter Ju, in view of Wei et. al., U.S. Pat. Pub. 2021/0280708, hereafter Wei.
Regarding claim 5, Ju discloses everything as applied above. Ju fails to explicitly disclose wherein the first gate dielectric and the second gate dielectric are not present on any sidewall of the gate cut.
However, Wei discloses (Fig. 4B, par. [0027]) wherein the first gate dielectric and the second gate dielectric are not present on any sidewall of the gate cut.
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to remove gate dielectric from the sidewalls of the gate cut, because Wei teaches (par. [0027]) that using an etch process that can remove both the gate electrode materials and the surrounding dielectrics provides improvements in terms of accuracy, reduced metal line resistance and reduced droop.
Regarding claim 6, Ju discloses everything as applied above. Ju fails to explicitly disclose wherein the gate cut further comprises a conductive via extending vertically in a third direction through the gate cut.
However, Wei discloses (Fig. 5D, par. [0077]) wherein the gate cut [312-2] further comprises a conductive via [502] extending vertically in a third direction through the gate cut [312-2].
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to include power rails in the gate cut as taught by Wei because Wei teaches (par. [0027]) that such a modification provides improvement in terms of metal line resistance and reduced voltage droop.
Regarding claim 7, Ju discloses everything as applied above. Ju fails to explicitly disclose a printed circuit board comprising the integrated circuit of claim 1.
However Wei discloses (Fig. 10, par. [0109]) a printed circuit board [2302] comprising the integrated circuit.
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to put IC device of claim 1 on a PCB, as taught by Wei, because such assembly is conventional and widely used in computer systems, where using a PCB offers an inexpensive alternative to semiconductor packages.
Regarding claim 8, Ju discloses one or more dies comprising
a first semiconductor device [202A] having a first semiconductor region [208A] extending in a first direction between a first source region [310A] and a first drain region [310A], and a first gate structure [374A] extending in a second direction over the first semiconductor region [208A] ([220’]);
a second semiconductor device [202B] having a second semiconductor region [208B] extending in the first direction between a second source region [310B] and a second drain region [310B], and a second gate structure [374B] extending in the second direction over the second semiconductor region [208B] ([220’]); and
a gate cut [270B] between the first gate structure [374A] and the second gate structure [374B], the gate cut comprising
a first dielectric layer [262] along edges of the gate cut [270B],
a dielectric fill [264] on the first dielectric layer [262], and
a second dielectric layer [266] (labels in Fig. 27) on a top surface of the dielectric fill [264],
wherein the first dielectric layer [262] has a higher dielectric constant than the dielectric fill [264] (par. [0028], layer [262] can be silicon nitride, which has a dielectric constant above 6, while layer [264] can be silicon oxide with the dielectric constant of about 3.9).
Ju fails to explicitly disclose a chip package comprising the one or more dies.
However, Wei discloses (Figs. 9-10) a chip package comprising the one or more dies.
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to include the IC die of Ju in a package of Wei to protect the IC die from environment and to connect the die in a computer system.
Regarding claim 9, Ju in view of Wei discloses everything as applied above. Ju further discloses wherein the first dielectric layer [264] directly contacts the first gate structure [374A] and the second gate structure [374B] (gate dielectric [372], see Fig. 24, is a part of both gate structures [374A,B]).
Regarding claim 10, Ju in view of Wei discloses everything as applied above. Ju further discloses (par. [0028]) wherein the first dielectric layer [262] comprises silicon and nitrogen (e.g., a silicon nitride layer) and the dielectric fill comprises silicon and oxygen (silicon oxide).
Regarding claim 11, Ju in view of Wei discloses everything as applied above. Wei further discloses (Fig. 5D, par. [0077]) wherein the gate cut [312-2] further comprises a conductive via [502] extending vertically in a third direction through the gate cut [312-2].
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to remove gate dielectric from the sidewalls of the gate cut, because Wei teaches (par. [0027]) that such a modification provides improvement in terms of metal line resistance and reduced voltage droop.
Regarding claim 12, Ju in view of Wei discloses everything as applied above. Wei further discloses (Fig. 10, par. [0109]) a printed circuit board [2302] comprising the integrated circuit.
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to put IC device of claim 8 on a PCB, as taught by Wei, because such assembly is conventional and widely used in computer systems, where using a PCB offers an inexpensive alternative to semiconductor packages.
Regarding claim 13, Ju discloses (Figs 24-28) an integrated circuit comprising:
one or more semiconductor regions [208 A,B],[220’] extending in a first direction between corresponding source or drain regions [310A];
a gate structure [374A],[374B] extending in a second direction over the one or more semiconductor regions [208A,B],[220’]; and
a gate cut [270B] extending in a third direction through an entire thickness of the gate structure [374A,B], the gate cut comprising
a first dielectric layer [262] along edges of the gate cut [270B],
a second dielectric layer [264] on the first dielectric layer [262], the second dielectric layer having a lower dielectric constant than the first dielectric layer (par. [0028], layer [262] can be silicon nitride, which has a dielectric constant above 6, while layer [264] can be silicon oxide with the dielectric constant of about 3.9),
a third dielectric layer [266] on a top surface of the second dielectric layer [264].
Ju fails to explicitly disclose
a conductive via extending through a central axis of the gate cut and along an entire height of at least the second dielectric layer in the third direction.
However, Wei discloses (Fig. 5D)
a conductive via [502] extending through a central axis of the gate cut in the third direction.
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to include power rails in the gate cut as taught by Wei because Wei teaches (par. [0027]) that such a modification provides improvement in terms of metal line resistance and reduced voltage droop.
Ju in view of Wei fails to explicitly disclose the via along an entire height of at least the second dielectric layer.
However, it would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to have the via extend along the entire height of at least the second dielectric layer, because such a change merely involves a change of relative dimension of the via and the second dielectric layer. Such a change is normally considered to be within the ability of one of ordinary skill in the art. (MPEP, 2144.04.IV.A, a change of relative dimension is normally obvious).
Regarding claim 14, Ju in view of Wei discloses everything as applied above. Ju further discloses wherein the first dielectric layer [262] directly contacts the first gate structure [374A] and the second gate structure [374B] (gate dielectric [372], see Fig. 24, is a part of both gate structures [374A,B]).
Regarding claim 15, Ju in view of Wei discloses everything as applied above. Ju further discloses (par. [0028]) wherein the first dielectric layer [262] comprises silicon and nitrogen (e.g., a silicon nitride layer).
Regarding claim 16, Ju in view of Wei discloses everything as applied above. The range of claim 16 is further obvious over Ju because Ju discloses an overlapping range (par. [0029]) with the thickness of the first dielectric layer between about 2 nm and about 4 nm.
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) (MPEP, Latest Edition, 2144.05.I, and case law therein).
Regarding claim 17, Ju in view of Wei discloses everything as applied above. Ju further discloses (Figs 24-28, par. [0029]) wherein the second dielectric layer [264] comprises silicon and oxygen.
Regarding claim 18, Ju in view of Wei discloses everything as applied above. Ju in view of Wei fails to explicitly disclose wherein the third dielectric layer comprises silicon and nitrogen or comprises silicon and carbon.
However, it would have been obvious to one of ordinary skill in the art prior to effective date of the instant application to use silicon nitride for the third dielectric layer because it is a known dielectric having etching selectivity with silicon oxide.
The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (Claims to a printing ink comprising a solvent having the vapor pressure characteristics of butyl carbitol so that the ink would not dry at room temperature but would dry quickly upon heating were held invalid over a reference teaching a printing ink made with a different solvent that was nonvolatile at room temperature but highly volatile when heated in view of an article which taught the desired boiling point and vapor pressure characteristics of a solvent for printing inks and a catalog teaching the boiling point and vapor pressure characteristics of butyl carbitol.)[AltContent: rect]
See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious); Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323 (Fed. Cir. 1988) (Claimed agricultural bagging machine, which differed from a prior art machine only in that the brake means were hydraulically operated rather than mechanically operated, was held to be obvious over the prior art machine in view of references which disclosed hydraulic brakes for performing the same function, albeit in a different environment.).
(MPEP, latest edition, 2144.07)
Regarding claim 19, Ju in view of Wei discloses everything as applied above. “wherein the third dielectric layer has a thickness between about 20 nm and about 30 nm” is obvious over Ju because Ju teaches and overlapping range (par. [0035], for the thickness of the layer [266] in Fig. 27C).
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) (MPEP, Latest Edition, 2144.05.I, and case law therein).
Regarding claim 20, Ju in view of Wei discloses everything as applied above. Ju further discloses wherein the gate structure includes a gate dielectric around the one or more semiconductor regions.
Ju fails to explicitly disclose wherein the gate dielectric is not present on any sidewall of the gate cut.
However, Wei discloses (Fig. 4B, par. [0027]) wherein the first gate dielectric and the second gate dielectric are not present on any sidewall of the gate cut.
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to remove gate dielectric from the sidewalls of the gate cut, because Wei teaches (par. [0027]) that using an etch process that can remove both the gate electrode materials and the surrounding dielectrics provides improvements in terms of accuracy, reduced metal line resistance and reduced droop.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR V BARZYKIN whose telephone number is (571)272-0508. The examiner can normally be reached Monday-Friday, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VICTOR V BARZYKIN/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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