Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 7-8 of the remarks, filed 4/28/2026, with respect to the amended claim language of “wherein how many PTE cachelines are in the set is determined based on one bit included in each cacheline in the set.” Is persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kwon ("Pinning Page Structure Entries to Last-Level Cache for Fast Address Translation", IEEE Access, Vol. 10, 2022, pp. 114552-114565. As listed on the IDS dated 4/28/2026).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huberty (US 2023/0066236) in view of Kwon ("Pinning Page Structure Entries to Last-Level Cache for Fast Address Translation", IEEE Access, Vol. 10, 2022, pp. 114552-114565. As listed on the IDS dated 4/28/2026)
In regards to claims 1, 10, and 19, taking claim 1 as exemplary Huberty teaches
A processor comprising: (fig. 1)
a plurality of cores, each core to execute instructions and process data; (fig. 1, ¶25-26, processors 10A-10N, each processor executes instructions from the instruction cache 20 and accesses data in the data cache 28)
a cache to be shared by a subset of the plurality of cores (fig. 1, ¶28, last level cache (LLC) 14, comprising cache 32 accessed by processors 10A-10N)
for storing page table entry (PTE) cachelines and non-PTE cachelines; (¶26-27, the LLC caches data for the MMU 30 (i.e. page table entries, PTE) cachelines, and also for the ICache 20 and DCache 28 (i.e. non-PTE) cachelines.
Huberty may not explicitly teach
the cache comprising an N-way set associative cache
a cache manager to implement a PTE-aware eviction policy for evicting cachelines from the cache, the PTE-aware eviction policy to reduce a rate at which the PTE cachelines are evicted to service non-PTE cacheline fills, wherein cacheline eviction in a set in the N-way set associative cache following the PTE-aware eviction policy is based on how many PTE cachelines are in the set, and wherein how many PTE cachelines are in the set is determined based on one bit included in each cacheline in the set.
In regards to “the cache comprising an N-way set associative cache”, Huberty does teach in ¶28 that the cache 32 of the LLC 14 “may have any capacity and configuration”. ¶4 teaches set associative caches, with a plurality (i.e. N) number of columns referred to as ways (i.e. an N-way set associative cache). ¶23 teaches that wide set associative caches (i.e. the larger the value of N, the wider) can be useful for implementing a replacement policy that uses criticality values of the cachelines as a factor).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the invention to have modified the system of Huberty to make the cache 32 of the LLC 14 a N-way associated cache. The motivation for such is that Huberty suggests that a set associate cache may simplify the replacement policy that takes into account the criticality values of cache lines, and the substitution of a N-way set associative cache for a generic cache would yield predictable results to one of ordinary skill in the art.
In regards to, a cache manager to implement a PTE-aware eviction policy for evicting cachelines from the cache, the PTE-aware eviction policy to reduce a rate at which the PTE cachelines are evicted to service non-PTE cacheline fills wherein cacheline eviction in a set in the N-way set associative cache following the PTE-aware eviction policy is based on how many PTE cachelines are in the set”, Huberty does teach in ¶48 that the criticality control circuit 34 is responsible for replacement (i.e. implementing an eviction policy) of cache lines in the cache 32 of the LLC 14 when a cache miss is detected (i.e. servicing a cacheline fill). ¶27-30 teaches that cache lines can be marked critical or non-critical, and that entries for the MMU (i.e. page table entries, PTEs) can marked (categorized) as critical, while other requests (i.e. non-PTEs) can be considered non-critical. ¶50 and fig. 4 teaches that cache lines marked as critical (i.e. PTEs) can be probabilistically biased to prevent critical cache lines from being replaced (i.e. the rate which PTE cachelines are selected to be evicted is reduced compared to non-PTE cachelines based on the number of cachelines in a set).
It would have been obvious to one of ordinary skill in the art prior the effective filing date of the claimed invention to modify the system of Huberty to implement a “PTE-aware” eviction policy by only marking MMU (i.e. PTE) as critical, and other entries (i.e. non-PTE as non-critical), as to decrease the rate of replacement of critical cachelines compared to non-critical cachelines by using a biased pseudo-random selection to preferentially select non-critical (non-PTE) marked cachelines for replacement over critical (PTE) cachelines. The motivation for such modifications is based on the teachings above (and it’s use of “may” when determining which factors to consider for marking cachelines as critical/non-critical), and the fact that Huberty explicitly that various modifications and variations would be apparent to those skilled in the art (¶119, ¶20). These modifications would yield predictable results to one of ordinary skill in the art.
In regards to wherein how many PTE cachelines are in the set is determined based on one bit included in each cacheline in the set.
Kwon teaches in page 114560 that an additional bit can be added to identify (and count) PSE (i.e. PTE cachelines), and another bit to pin the PSE to the cache, which prevents the PSE from being evicted. When the number of PSEs in the cache (i.e. counted by using the extra bit) exceeds a pinned limit the LRU PSE has its pinned bit reset and become eligible for selection as a victim block along with other data blocks and unpinned PSEs.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of claimed invention to have used the teachings of Kwon to modify the system of Huberty such that Huberty’s use of a critical/non-critical bit can be replaced by a dedicated bit that marks a PTE, along with including an additional pinned bit, such that a set number (i.e. cache capacity) can be allocated to a pinned (non-victimizable) set of PTEs, and when that set number is exceeded, any non-pinned PTEs become eligible for cache victimization along with cache lines storing regular data. These modifications would yield predictable results to one of ordinary skill in the art. The motivation for making such modifications, is that this allows better tracking and allocation of a dedicated portion of the cache for storing PTEs that have a high change of being reused, enhancing the functionality of the system.
In regards to claims 2-4, 11-13, and 20-22, Huberty and Kwon further makes obvious
wherein if a number of PTE cachelines in a set is less than a first threshold, the cache manager is to evict PTE cachelines from the set at a first rate or with a first probability and wherein if the number of PTE cachelines in a set is greater than the first threshold, the cache manager is to evict PTE cachelines from the set at a second rate greater than the first rate or with a second probability greater than the first probability
wherein if a number of PTE cachelines in the set is greater than a third threshold, the cache manager is to evict PTE cachelines from the set at a third rate greater than the second rate or with a third probability greater than the second probability.
wherein the first probability is in a range of 0% to 1%, the second probability is in a range of 5% to 20%, and the third probability is in a range of 95% to 100%.
¶50 and ¶64 of Huberty teaches that criticality control circuit 34 (cache manager) may employ multiple biased pseudo-random selections based on different probabilities. The probabilities of selection would increase as the number of critical (PTE) cachelines increases, and probability functions could be chosen such that the probability ranges (i.e. first-third probability) are fulfilled when a certain number (or percent) of the cache is currently above/below (first and third threshold) the number of cachelines marked as critical (PTE). This is a design issue that could be implemented by one of ordinary skill in the art while yielding predictable results, based on the size of the cache, the number of ways, and the desired probabilities.
In regards to claims 5, 14, and 23, Huberty and Kwon further makes obvious
wherein each cacheline is to include a PTE bit to differentiate between the PTE cachelines and the non-PTE cachelines (Huberty ¶36 teaches the cache may have a field (i.e. a bit) for a criticality value (i.e. a 1 for critical (PTE), and 0 for non-critical (non-PTE) data and/or Kwon teaches in page 114560 that an additional bit can be added to identify (and count) PSE (i.e. PTE cachelines))
the cache manager to determine the number of PTE cachelines in the set based on a number of PTE bits set to 1 in the set. (Huberty ¶35-36 teaches that the amount/capacity of a cache can be determined based off a field in the cache tag (i.e. the critical/non-critical, PTE/non-PTE field))
In regards to claims 6, 15, and 24, Huberty and Kwon further makes obvious
wherein the cache manager is to generate a way mask with a bit value associated with each way to indicate if a PTE cacheline is stored in the way. (Huberty ¶50, criticality control circuit 34 (cache manager) may selectively mask critical (PTE) cache lines). ¶4 as each entry is associated with a “way”, the masking for each row can be seen as a “way” mask.)
In regards to claims 7, 16, and 25, Huberty and Kwon further makes obvious
wherein the cache manager is to determine an eviction candidate for a first set based on a least recently used (LRU) eviction policy, the cache manager to exclude certain ways from the LRU eviction policy based on the way mask. (see at least fig. 4 and ¶48-50 of Huberty where an LRU entry is selected and cachelines marked as critical (i.e. containing PTEs) can be selectively masked (i.e. the ways containing those entries are excluded from selection)
In regards to claims 8, 17, and 26, Huberty and Kwon further makes obvious
wherein the cache manager is to exclude ways from consideration which are indicated in the way mask to store PTE cachelines. (see at least fig. 4 and ¶48-50 of Huberty where an LRU entry is selected and cachelines marked as critical (i.e. containing PTEs) can be selectively masked (i.e. the ways containing those entries are excluded from selection)
In regards to claims 9, 18, and 27, Huberty and Kwon further makes obvious
wherein the cache manager is to increase the eviction rate or probability of PTE cacheline evictions for PTE cachelines without a cache hit within a pre-defined window. (Huberty, ¶66 teaches that the criticality control circuit 34 may accelerate (increase rate/probability) the eviction of cache lines identified as critical (PTE cachelines) based on one or more indications. Hubety, ¶67-72 teaches one of these indications is if the critical cachelines are not being accessed any longer (i.e. no cache hits within a pre-defined window), and/or the cache hit rates are below a set threshold (i.e. the number of cache hits within a certain amount of requests (i.e. window) is below a set amount).
EXAMINER’S NOTE
Examiner has cited particular paragraphs, figures, and/or columns and line numbers in the references applied to the claims above for the convenience of the Applicants. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicants in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON W BLUST whose telephone number is (571)272-6302. The examiner can normally be reached 12-8:30 EST.
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/JASON W BLUST/ Primary Examiner, Art Unit 2132
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