DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 23 Dec 2022 for application number 18/087,990. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, and Claims.
Claims 1-20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 23 Dec 2022 was filed before the mailing of this Office Action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Device embodiment II., Modification A2. in the reply filed on 15 Jun 2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 10-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. [hereinafter as Chen] (US 2018/0175214 A1).
In reference to claim 1, Chen teaches A semiconductor structure comprising:
a gate region [channel region; Fig. 17A, para 0074];
a source/drain region [SD region; Fig. 17A, para 0074]; and
a nanosheet semiconductor layer [second semiconductor layers 25N; Fig. 17A, paras 0075] extending continuously across the gate region [channel region] and the source/drain region [SD region], the nanosheet semiconductor layer comprising a first portion [25N over channel region; Fig. 17A] extending through the gate region [channel region] and a second portion [25N over SD region; Fig. 17A] extending through the source/drain region [SD region];
wherein the source/drain region [SD region] comprises a cladded epitaxial layer [S/D epitaxial layers 80N; Fig. 17A, para 0065] wrapping around the second portion [25N over SD region] of the nanosheet semiconductor layer [25N].
In reference to claim 2, Chen teaches The semiconductor structure of claim 1, further comprising a gate spacer [sidewall spacer 76; Figs. 16A-17A, para 0064] disposed between the gate region [channel region] and the source/drain region [SD region].
In reference to claim 3, Chen teaches The semiconductor structure of claim 1, wherein the first portion [25N over channel region] of the nanosheet semiconductor layer has a first thickness and the second portion [25N over SD region] of the nanosheet semiconductor layer has a second thickness different than the first thickness [the thicknesses of 25N over channel region and 25N over SD region are different].
In reference to claim 4, Chen teaches The semiconductor structure of claim 3, wherein the second thickness is less than the first thickness [thickness of 25N over SD region is less than thickness of 25N over channel region].
In reference to claim 10, Chen teaches The semiconductor structure of claim 1, further comprising a wrap-all-around contact [contact metals 39; Fig. 29, para 0093] surrounding the cladded epitaxial layer [80N] wrapping around the second portion [25N over SD region] of the nanosheet semiconductor layer.
In reference to claim 11, Chen teaches The semiconductor structure of claim 1, wherein the gate region [channel region] wraps all around the first portion [25N over channel region] of the nanosheet semiconductor layer.
In reference to claim 12, Chen teaches A gate-all-around transistor comprising:
a gate region [channel region; Fig. 17A, para 0074];
a source/drain region [SD region; Fig. 17A, para 0074]; and
a plurality of nanosheet semiconductor layers [second semiconductor layers 25N; Fig. 17A, paras 0075] extending continuously across the gate region [channel region] and the source/drain region [SD region], each of the plurality of nanosheet semiconductor layers comprising a first portion [25N over channel region; Fig. 17A] extending through the gate region [channel region] and a second portion [25N over SD region; Fig. 17A] extending through the source/drain region [SD region];
wherein the source/drain region [SD region] comprises cladded epitaxial layers [S/D epitaxial layers 80N; Fig. 17A, para 0065] wrapping around the second portion [25N over SD region] of each of the plurality of nanosheet semiconductor layers.
In reference to claim 13, Chen teaches The gate-all-around transistor of claim 12, wherein the first portion [25N over channel region] of each of the plurality of nanosheet semiconductor layers has a first thickness and the second portion [25N over SD region] of each of the plurality of nanosheet semiconductor layers has a second thickness different than the first thickness [the thicknesses of 25N over channel region and 25N over SD region are different].
In reference to claim 14, Chen teaches The gate-all-around transistor of claim 13, wherein the second thickness is less than the first thickness [thickness of 25N over SD region is less than thickness of 25N over channel region].
In reference to claim 15, Chen teaches The gate-all-around transistor of claim 12, further comprising a wrap-all-around contact [contact metals 39; Fig. 29, para 0093] surrounding the cladded epitaxial layers [80N] wrapping around the second portion [25N over SD region] of each of the plurality of nanosheet semiconductor layers.
In reference to claim 16, Chen teaches The gate-all-around transistor of claim 12, wherein the gate region [channel region] wraps all around the first portion [25N over channel region] of each of the plurality of nanosheet semiconductor layers.
In reference to claim 17, Chen teaches An integrated circuit comprising:
a gate-all-around transistor [transistor in Fig. 17A] structure comprising:
a gate region [channel region; Fig. 17A, para 0074];
a source/drain region [SD region; Fig. 17A, para 0074]; and
a plurality of nanosheet semiconductor layers [second semiconductor layers 25N; Fig. 17A, paras 0075] extending continuously across the gate region [channel region] and the source/drain region, each of the plurality of nanosheet semiconductor layers comprising a first portion [25N over channel region; Fig. 17A] extending through the gate region [channel region] and a second portion [25N over SD region; Fig. 17A] extending through the source/drain region [SD region];
wherein the source/drain region [SD region] comprises cladded epitaxial layers [S/D epitaxial layers 80N; Fig. 17A, para 0065] wrapping around the second portion [25N over SD region] of each of the plurality of nanosheet semiconductor layers [25N].
In reference to claim 18, Chen teaches The integrated circuit of claim 17, wherein the first portion [25N over channel region] of each of the plurality of nanosheet semiconductor layers has a first thickness and the second portion [25N over SD region] of each of the plurality of nanosheet semiconductor layers has a second thickness different than the first thickness [the thicknesses of 25N over channel region and 25N over SD region are different].
In reference to claim 19, Chen teaches The integrated circuit of claim 17, further comprising a wrap-all-around contact [contact metals 39; Fig. 29, para 0093] surrounding the cladded epitaxial layers [80N] wrapping around the second portion [25N over SD region] of each of the plurality of nanosheet semiconductor layers.
In reference to claim 20, Chen teaches The integrated circuit of claim 17, wherein the gate region [channel region] wraps all around the first portion [25N over channel region] of each of the plurality of nanosheet semiconductor layers.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Liaw et al. [hereinafter as Liaw] (US 2021/0118884 A1).
In reference to claim 5, Chen teaches the invention of claim 1.
However, Chen does not explicitly teach The semiconductor structure of claim 1, wherein the nanosheet semiconductor layer further comprises a third portion between the first portion and the second portion, wherein the third portion comprises a doped region.
Chen and Liaw teach The semiconductor structure of claim 1, wherein the nanosheet semiconductor layer further comprises a third portion [inner spacers 250 of Liaw; Fig. 9B, para 0051] between the first portion [25N over channel of Chen] and the second portion [25N over SD region of Chen], wherein the third portion [250 of Liaw] comprises a doped region [250 of Liaw may be doped; para 0051].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Chen and Liaw before the effective filing date of the claimed invention, to include the third portion as disclosed by Liaw into the semiconductor device of Chen in order to obtain a semiconductor device with first, second, and third portions continuous portions of a nanosheet semiconductor layer.
One of ordinary skill in the art would be motivated to obtain a semiconductor device with first, second, and third portions continuous portions of a nanosheet semiconductor layer to provide the predictable result of improving performance through electrical performance improvement and better structural integrity.
In reference to claim 6, Chen and Liaw teach the invention of claim 5.
Chen and Liaw teach The semiconductor structure of claim 5, wherein the semiconductor structure comprises an n-type transistor [Fig. 17A, para 0074 of Chen discloses a n-type transistor], and the doped region comprises one or more n-type dopants [250 of Liaw can be n-type doped; para 0051].
In reference to claim 7, Chen and Liaw teach the invention of claim 5.
Chen and Liaw teach The semiconductor structure of claim 5, wherein the semiconductor structure comprises a p-type transistor [Fig. 3, para 0052 of Chen discloses that n- and p-type transistors may exist], and the doped region comprises one or more p-type dopants [250 of Liaw can be p-type doped; para 0051].
In reference to claim 8, Chen and Liaw teach the invention of claim 5.
Chen and Liaw teach The semiconductor structure of claim 5, wherein the first portion [25N over channel region] of the nanosheet semiconductor layer has a first thickness, the second portion [25N over SD region] of the nanosheet semiconductor layer has a second thickness, and the third portion [250 of Liaw] of the nanosheet semiconductor layer has a third thickness, the first thickness and the third thickness each being greater than the second thickness [Chen: thickness of 25N over SD region is less than thickness of 25N over channel region, i.e. first thickness is greater than second thickness; Liaw: thickness (315 in Fig. 9B) of 250, i.e. third portion, is greater than thickness of semiconductor layer 220B (which has thickness of 310; see Fig. 6B); para 0031 discloses 315 is greater than 310].
In reference to claim 9, Chen and Liaw teach the invention of claim 5.
Chen and Liaw teach The semiconductor structure of claim 5, wherein the first portion [25N over channel region] of the nanosheet semiconductor layer has a first thickness, the second portion [25N over SD region] of the nanosheet semiconductor layer has a second thickness, and the third portion [250 of Liaw] of the nanosheet semiconductor layer has a third thickness, the first thickness being greater than the second thickness and the third thickness being greater than the first thickness [Chen: thickness of 25N over SD region is less than thickness of 25N over channel region, i.e. first thickness is greater than second thickness; Liaw: thickness (315 in Fig. 9B) of 250, i.e. third portion, is greater than thickness of semiconductor layer 220B (which has thickness of 310; see Fig. 6B); para 0031 discloses 315 is greater than 310].
Examiner’s Note
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure as follows. Applicant is reminded that in amending in response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR § 1.111(0).
Majhi et al. [hereinafter as Majhi] (US-20230178658-A1) discloses semiconductor layers extending into S/D regions [Fig. 6].
Conclusion
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/ANDREW CHUNG/
Examiner, Art Unit 2898
