DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 18/088,153, application filed on 12/23/2022.
3. Claims 1-20 are currently pending in this application.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 04/26/2023, 04/26/2023 and 12/28/2023, respectively, is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claim(s) 1, 7-12, 17-18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Levi (US PG Pub No. 20130144589).
7. With respect to claims 1 and 11, Levi teaches:
A method of manufacturing an integrated-circuit device having a floating-point adder (see design and synthesis of adder, bit-width, para 7; see wires of floating point adder, para 9-12; see components of floating point adder, para 109; implementing floating point adder in hardware, para 108-112; see wire widths according to implementation of floating point adder, para 10-15), the method comprising:
synthesizing (see circuit synthesis, Abstract; synthesis of floating point adder circuit, para 12, 15, 18-19), within a computing device, a netlist (synthesized netlist, para 12; synthesized into netlist, para 15) that defines bit-widths (specifying bit-widths, para 7; pre-defined bit-widths, para 11; 16, 110) of conductive paths within the floating-point adder (wiring of floating point adder, para 9-12, 14) according to one or more bus width parameters declared within a hardware description language (HDL) specification of the floating-point adder (see wire specifications based on HDL structure and format, para 90), the one or more bus width parameters corresponding to a first floating-point adder precision within a predetermined range of different floating-point adder precisions (see range, para 107; see 32-bit and 64-bit precisions, para 110); and
fabricating the integrated circuit device according to the netlist such that the conductive paths within the floating-point adder have bit-widths according to the netlist (assembling circuit components to build floating point adder circuit, para 124-125).
8. With respect to claims 12 and 20, Levi teaches:
A method of manufacturing an integrated-circuit device having a floating-point adder (see design and synthesis of adder, bit-width, para 7; see wires of floating point adder, para 9-12; see components of floating point adder, para 109; implementing floating point adder in hardware, para 108-112; see wire widths according to implementation of floating point adder, para 10-15), the method comprising:
specifying, within a netlist (synthesized netlist, para 12; synthesized into netlist, para 15; specifying bit-widths, para 7; pre-defined bit-widths, para 11; 16, 110) , circuit interconnections corresponding to one of a plurality of different floating-point adder precisions (see wire specifications based on HDL structure and format, para 90; see range, para 107; see 32-bit and 64-bit precisions, para 110; assembling circuit components to build floating point adder circuit, para 124-125) according to one or more bus width parameters declared within a hardware description language (HDL) specification (see wire specifications based on HDL structure and format, para 90), including specifying either a first quantity or a second quantity of conductive interconnects (see values on wires for interconnects, para 5) between first and second components of the floating-point adder according to whether a first bus width parameter of the one or more bus width parameters specifies a first value or a second value, respectively (see range, para 107; see 32-bit and 64-bit precisions, para 110); and
fabricating the integrated circuit device according to the netlist such that the first and second components of the floating-point adder are coupled to one another via either the first quantity or the second quantity of conductive interconnects in accordance with the first bus width parameter declared within the HDL specification (assembling circuit components to build floating point adder circuit, para 124-125).
9. With respect to independent claim 7, Levi teaches:
The method of claim 1 wherein the predetermined range of different floating-point adder precisions includes maximum and minimum floating-point adder precisions at opposite ends of the range and for which the maximum floating-point adder precision is at least twice the minimum floating-point adder precision (see range, para 107; see 32-bit and 64-bit precisions for adder, para 110; minimum/maximum bit-width, para 11).
10. With respect to independent claim 8, Levi teaches:
The method of claim 1 wherein the predetermined range of different floating-point adder precisions spans at least from a first precision corresponding to 16-bit binary floating point number to a second precision corresponding to a 32-bit binary floating point number (see range, para 107; see 16-bit, 32-bit and 64-bit precisions for adder, para 110, 135).
11. With respect to independent claim 9, Levi teaches:
The method of claim 1 wherein the one or more bus width parameters comprise a plurality of bus width parameters, and wherein the HDL specification indicates, for one or more floating-point adder precisions at a lower end of the predetermined range of floating-point adder precisions (see range, para 107; see 16-bit, 32-bit and 64-bit precisions for adder, para 110, 135; see wire specifications based on HDL structure and format, para 90; see range, para 107; see 32-bit and 64-bit precisions, para 110; assembling circuit components to build floating point adder circuit, para 124-125), that one or more of the width parameters within the plurality of bus width parameters are to be bypassed in favor of other parameters (see bypassing components, para 212-214, 218; modifying parameters, para 6; specifying other options for bit-widths parameters, para 7-8).
12. With respect to independent claim 10, Levi teaches:
The method of claim 1 wherein the one or more bus width parameters declared within the HDL specification of the floating-point adder comprise one of a plurality of sets of the one or more bus width parameters (see range, para 107; see 16-bit, 32-bit and 64-bit precisions for adder, para 110, 135; see wire specifications based on HDL structure and format, para 90; see range, para 107; see 32-bit and 64-bit precisions, para 110; assembling circuit components to build floating point adder circuit, para 124-125), each of the sets of the one or more bus width parameters corresponding to a respective one of the different floating-point adder precisions within the predetermined range (see range, para 107; see 32-bit and 64-bit precisions for adder, para 110; minimum/maximum bit-width, para 11).
13. With respect to independent claim 17, Levi teaches:
The method of claim 12 wherein the plurality of different floating-point adder precisions comprise a predetermined range of different floating-point adder precisions that spans at least from a first precision corresponding to 16-bit binary floating point number to a second precision corresponding to a 32-bit binary floating point number (see range, para 107; see 32-bit and 64-bit precisions for adder, para 110; minimum/maximum bit-width, para 11; see range, para 107; see 16-bit, 32-bit and 64-bit precisions for adder, para 110, 135; see wire specifications based on HDL structure and format, para 90; see range, para 107; see 32-bit and 64-bit precisions, para 110; assembling circuit components to build floating point adder circuit, para 124-125).
14. With respect to independent claim 18, Levi teaches:
The method of claim 12 wherein the floating-point adder comprises a component of a multiply-accumulate processor within the integrated-circuit device (see multiply, accumulate components for adder, para 40-45, 107).
Claim Rejections - 35 USC § 103
15. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
16. Claim(s) 2 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Levi (US PG Pub No. 20130144589) in view of Roberts et al. (US PG Pub No. 2019/0102175).
17. With respect to claim 2, Levi teaches:
The method of claim 1 wherein the one or more bus width parameters declared within the HDL specification include a plurality of bus width parameters (see range, para 107; see 32-bit and 64-bit precisions for adder, para 110; minimum/maximum bit-width, para 11; see range, para 107; see 16-bit, 32-bit and 64-bit precisions for adder, para 110, 135; see wire specifications based on HDL structure and format, para 90; see range, para 107; see 32-bit and 64-bit precisions, para 110; assembling circuit components to build floating point adder circuit, para 124-125).
Levi appears to be silent regarding:
including a first bus width parameter that matches a bit width of a mantissa value according to the first floating-point adder precision.
However, Roberts teaches:
including a first bus width parameter that matches a bit width of a mantissa value according to the first floating-point adder precision (see bit-size parameters that match or are the same for mantissa value of floating-point adder precision, para 37, 43-46).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated Roberts’ matching bit width of mantissa value into the precision floating point adder design of Levi for at least the following reason(s): Roberts’ hybrid floating point circuitry improves the adder circuitry architecture of Levi by providing a design that can lower power usage at a per-watt efficiency, thus providing a useful improvement in the art.
18. With respect to independent claim 19, Levi teaches:
The method of claim 1 wherein the one or more bus width parameters declared within the HDL specification include a plurality of bus width parameters (see range, para 107; see 32-bit and 64-bit precisions for adder, para 110; minimum/maximum bit-width, para 11; see range, para 107; see 16-bit, 32-bit and 64-bit precisions for adder, para 110, 135; see wire specifications based on HDL structure and format, para 90; see range, para 107; see 32-bit and 64-bit precisions, para 110; assembling circuit components to build floating point adder circuit, para 124-125).
Levi appears to be silent regarding:
including a first bus width parameter that matches a bit width of a mantissa value according to a first floating-point adder precision within a predetermined range of different floating-point adder precisions.
However, Roberts teaches:
including a first bus width parameter that matches a bit width of a mantissa value according to a first floating-point adder precision within a predetermined range of different floating-point adder precisions (see bit-size parameters that match or are the same for mantissa value of floating-point adder precision, para 37, 43-46).
It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated Roberts’ matching bit width of mantissa value into the precision floating point adder design of Levi for at least the following reason(s): Roberts’ hybrid floating point circuitry improves the adder circuitry architecture of Levi by providing a design that can lower power usage at a per-watt efficiency, thus providing a useful improvement in the art.
Allowable Subject Matter
19. Claims 3-6 and 13-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
20. With respect to dependent claim 3 (and claims 4-6 which depend therefrom), the prior art made of record fails to teach the combination of steps recited in claim 3, including the following particular combination of steps as recited in claim 3, as follows:
wherein synthesizing the netlist comprises defining a first conductive path that (i) conveys the mantissa value to an input of a combinatorial logic circuit within the floating-point adder and (ii) has a bit width according to the first bus width parameter, and wherein fabricating the integrated circuit device according to the netlist comprises fabricating the first conductive path having the bit width that matches the bit width of the mantissa value.
21. With respect to dependent claim 13 (and claim 14 which depends therefrom), the prior art made of record fails to teach the combination of steps recited in claim 13, including the following particular combination of steps as recited in claim 13, as follows:
wherein specifying circuit interconnections within the netlist further includes specifying either a third quantity or a fourth quantity of conductive interconnects between the second component and a third component of the floating-point adder according to whether a second bus width parameter of the one or more bus width parameter specifies a third value or a fourth value, respectively.
22. With respect to dependent claim 15 (and claim 16 which depends therefrom), the prior art made of record fails to teach the combination of steps recited in claim 3, including the following particular combination of steps as recited in claim 3, as follows:
wherein: the first component of the floating-point adder comprises a first register to store a first mantissa of a first floating-point operand; and the second component of the floating-point adder comprises a right-shift circuit to receive the first mantissa from the first register and generate a right-shifted version of the first mantissa.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851