Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Non-Final office action based on application 18/088,172 in response to Information disclosure statement filed March 3, 2026. Claims 1-5, 7, 9-14 & 16-18 are currently pending and have been considered below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 4, & 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lue (Pre-Grant Publication 2020/0381450, previously cited reference) in view of Sun (Pre-Grant Publication 2021/0391354, newly cited from IDS filed March 3, 2026).
Regarding claim 1, Lue discloses a non-memory device (flash memory – paragraphs [0003] and [0005]) comprising:
a substrate (Fig. 7, 100);
a gate structure including a plurality of gate electrode layers (126) and a plurality of interlayer insulating layers (104), which are alternately stacked in a vertical direction over the substrate, the gate structure including a hole pattern (Paragraph [0068]);
a data storage layer (110) disposed inside the hole pattern; and
a channel layer (112) disposed on the data storage layer inside the hole pattern, wherein the channel layer is disposed at each of different levels isolated from each other in the vertical direction by the plurality of interlayer insulating layers (112 is disposed at each of the levels associated with the gates 126).
a first insulating pillar (Fig. 1e, 114, which would be located in 112 of figure 7) disposed in a central region of the hole pattern (paragraph [0046]); and
a first source/drain pillar (122) and a second source/drain pillar (124) penetrating the first insulating pillar (fig. 1e).
Lue does not disclose wherein the first and second source/drain pillar penetrate a portion of the channel layer. However Sun discloses a memory device comprising:
An opening (Fig. 1g, 130) penetrating a portion channel layer (126a/126b) wherein the opening is filled with a conductive material (Fig. 1h, 134 & 136) to form source/drain pillars (Paragraph [0047]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the source/drain pillars penetrating a portion the channel layer because it will divide the channel layer into separated portions thereby 2 bit per cell storage and higher cell density can be achieved (Paragraph [0043]), which will increase the functionality of the memory device.
Regarding claim 3, Lue further discloses:
wherein, in the gate structure, the plurality of interlayer insulating layers protrude farther into the hole pattern compared to the gate electrode layers (Fig. 7).
Regarding claim 4, Lue further discloses:
the data storage layer is disposed along a side surface of the hole pattern, wherein the channel layer is disposed along a side surface of the data storage layer, wherein the hole pattern includes a concave part that is defined at the same level as each of the plurality of gate electrode layers, the concave part being defined between the plurality of interlayer insulating layers that overlap with each other in the vertical direction, and wherein the data storage layer and the channel layer are disposed in the concave part (Fig. 7 & Paragraph [0068]).
Regarding claim 7, Lue further discloses:
a second insulating pillar (116) between the first source/drain pillar and the second source/drain pillar.
Claims 2, 11-12, 14, 16 & 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lue (Pre-Grant Publication 2020/0381450, previously cited reference) in view of Sun (Pre-Grant Publication 2021/0391354, newly cited from IDS filed March 3, 2026) as applied to claim 1, and further in view of Kim (Pre-Grant Publication 2019/0198509, previously cited reference).
Regarding claim 2, Lue and Sun disclose all of the limitations of claim 1 (addressed above). Lue further discloses:
The channel layer (112) is discontinuous in the vertical direction and the channel layer being formed at levels in which each of the plurality of gate electrode layers is formed (Fig. 7).
Lue does not disclose the data storage layer is discontinuous in the vertical direction and formed at level in which each of the gate electrode is formed or at least one of a dielectric layer and metal layer disposed between the data storage layer and the channel layer. However Kim discloses a memory device comprising:
Charge storage material (Fig. 16, 36) formed with cavities (26) wherein the charge storage material is formed discontinuous and formed at levels in which gate electrodes are formed (58).
Kim further discloses tunneling layers (40-44) made of a dielectric/insulating material (Paragraph [0037]) formed between the data storage layer (36) and a channel layer (46).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the data storage layer discontinuous in the vertical direction because it may alleviate charge leakage between neighboring charge storage regions and mitigate coupling of charge storage regions with other components and thereby improve performance of the memory device (Paragraph [0059]). Further by forming the dielectric tunneling layer between the data storage layer and channel layer, the tunneling layer will serve to promote passage of charge carriers during programming/erase operations of the memory device (Paragraph [0036]).
Regarding claim 11 & 17, Lue discloses a memory device comprising:
a gate structure including a plurality of gate electrode layers (126) and a plurality of interlayer insulating layers (104), which are alternately stacked in a vertical direction over a substrate (100);
a channel layer (112) disposed on the substrate, the channel layer disposed adjacent to each of the plurality of gate electrode layers of the gate structure;
a data storage layer (110) disposed between each of the plurality of gate electrode layers and the channel layer; and
a first source/drain pillar (122) and a second source/drain pillar (124) penetrating the gate structure.
Lue does not disclose the data storage layer is discontinuous in the vertical direction and formed at level in which each of the gate electrode is formed, at least one of a dielectric layer and metal layer disposed between the data storage layer and the channel layer, or the first and second source/drain pillar penetrate a portion of the channel layer. However Kim discloses a memory device comprising:
Charge storage material (Fig. 16, 36) formed with cavities (26) wherein the charge storage material is formed discontinuous and formed at levels in which gate electrodes are formed (58).
Kim further discloses tunneling layers (40-44) made of a dielectric/insulating material (Paragraph [0037]) formed between the data storage layer (36) and a channel layer (46).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the data storage layer discontinuous in the vertical direction because it may alleviate charge leakage between neighboring charge storage regions and mitigate coupling of charge storage regions with other components and thereby improve performance of the memory device (Paragraph [0059]). Further by forming the dielectric tunneling layer between the data storage layer and channel layer, the tunneling layer will serve to promote passage of charge carriers during programming/erase operations of the memory device (Paragraph [0036]).
Further Sun discloses a memory device comprising:
An opening (Fig. 1g, 130) penetrating a portion channel layer (126) wherein the opening is filled with a conductive material (Fig. 1h, 134 & 136) to form source/drain pillars (Paragraph [0047]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the source/drain pillars penetrating a portion the channel layer because it will divide the channel layer into separated portion thereby 2 bit per cell storage and higher cell density can be achieved (Paragraph [0043]).
Regarding claim 12, Lue further discloses:
the channel layer and the data storage layer are disposed between the plurality of interlayer insulating layers (Fig. 7).
Regarding claim 14, Lue further discloses:
a first insulating pillar (114) penetrating the gate structure; and
a second insulating pillar (116) between the first source/drain pillar and the second source/drain pillar, wherein the first source/drain pillar (122) and the second source/drain pillar (124) penetrate the first insulating pillar (Fig. 1e).
Regarding claim 16, Lue further discloses:
the plurality of interlayer insulating layers (104) include a first interlayer insulating layer and a second interlayer insulating layer, which are adjacent to each other in the vertical direction, and wherein the channel layer and the data storage layer are disposed between the first interlayer insulating layer and the second interlayer insulating layer (Fig. 7).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lue (Pre-Grant Publication 2020/0381450 previously cited reference) in view of Sun (Pre-Grant Publication 2021/0391354, newly cited from IDS filed March 3, 2026) as applied to claim 1, and further in view of Park (Pre-Grant Publication 2022/0271057, previously cited reference).
Regarding claim 5, Lue and Sun disclose all of the limitations of claim 1 (addressed above). Neither reference disclose the data storage layer include ferroelectrics. However Park discloses a memory device comprising:
A charge storage layer that includes a ferroelectric material (Paragraph [0132]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the data storage layer including a ferroelectric material because it will allow the memory device to operate at high speed and allow long data retention thereby improving performance of the memory device (Paragraph [0132]).
Claim(s) 13 & 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lue (Pre-Grant Publication 2020/0381450 previously cited reference), Sun (Pre-Grant Publication 2021/0391354, newly cited from IDS filed March 3, 2026) and, Park (Pre-Grant Publication 2022/0271057, previously cited reference) as applied to claim 11, & 17 above, and further in view of Park (Pre-Grant Publication 2022/0271057)
Regarding claims 13, & 18, Lue, Sun, and Kim disclose all of the limitations of claims 11 & 17 addressed above.
Kim discloses (for the combination of Lue, Sun, and Kim as described above with respect to claims 11 & 17):
Tunneling layers (40-44) made of a dielectric/insulating material (Paragraph [0037]) formed between the data storage layer (36) and a channel layer (46).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the dielectric tunneling layer between the data storage layer and channel layer, the tunneling layer will serve to promote passage of charge carriers during programming/erase operations of the memory device (Paragraph [0036]).
Park discloses a memory device comprising:
A charge storage layer that includes a ferroelectric material (Paragraph [0132]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the data storage layer including a ferroelectric material because it will allow the memory device to operate at high speed and allow long data retention thereby improving performance of the memory device (Paragraph [0132]).
Allowable Subject Matter
Claims 9-10 are allowed.
The following is an examiner’s statement of reasons for allowance: Claim 9 is allowed because none of the prior art either alone or in combination discloses a non-volatile memory device comprising: the gate structure including a hole pattern and a concave part, the concave part located between vertically adjacent interlayer insulating layers among the plurality of interlayer insulating layers; a channel layer disposed in the concave part; a data storage layer disposed between the channel layer and each of the plurality of gate electrode layers; a dielectric layer disposed between the data storage layer and the channel layer; and a metal layer disposed between the data storage layer and the dielectric layer. Claim 10 is also allowed based on its dependency from claim 9.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 & 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM.
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/BRANDON C FOX/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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