Prosecution Insights
Last updated: April 19, 2026
Application No. 18/088,460

COIL STRUCTURE TO CONTROL VIA IMPEDANCE

Non-Final OA §102§103
Filed
Dec 23, 2022
Examiner
TRAN, BINH BACH THANH
Art Unit
2848
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
92%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allow Rate
545 granted / 680 resolved
+12.1% vs TC avg
Moderate +12% lift
Without
With
+12.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
28 currently pending
Career history
708
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
54.1%
+14.1% vs TC avg
§102
35.3%
-4.7% vs TC avg
§112
8.5%
-31.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 680 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 – 3, 5 – 10, 12 - 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (US 20160276091). Regarding claim 1, Zhang discloses an apparatus comprising: a printed circuit board (PCB in Fig. 3); a via (a via 110) including a barrel (a stub portion 130) through the PCB, the barrel electrically connected to a pad (a conductor cap 160) in a plane of the PCB; and a coil (the inductor path 152) around the pad in the plane of the PCB, the coil of conductor in the plane of the PCB, the coil electrically connected to the pad (the inductor 152 electrically connected to the pad 160, Fig. 2). Regarding claim 2, Zhang discloses the claimed invention as set forth in claim 1. Zhang further discloses the PCB further comprises an inner routing layer (the layer containing the inductor 154, Fig. 2 or consider another inductor, in Fig. 3, to be in the same plane; or 254, Fig. 4), wherein the plane comprises the inner routing layer. Regarding claim 3, Zhang discloses the claimed invention as set forth in claim 1. Zhang further suggests the plane comprises either a top layer (the top layer of the stack, Fig. 3) of the PCB or a bottom layer of the PCB. Regarding claim 5, Zhang discloses the claimed invention as set forth in claim 3. Zhang further discloses the pad comprises a first pad (160) and the coil (152) comprises a first coil (152), wherein the first pad and the first coil are in the top layer of the PCB, the PCB further comprising: an inner routing layer including a second pad (the pad connected to 154, Fig. 2) in a plane (the plane of 154) of the inner routing layer, with a second coil (154) around the second pad in the inner routing layer. Regarding claim 6, Zhang discloses the claimed invention as set forth in claim 3. Zhang further suggests the pad comprises a first pad (160) and the coil comprises a first coil (152), wherein the first pad and the first coil are in the bottom layer (consider the layer through 152 is a bottom layer) of the PCB, the PCB further comprising: an inner routing layer including a second pad (the pad connected to 154) in a plane (a plane of 154) of the inner routing layer, with a second coil (154) around the second pad in the inner routing layer. Regarding claim 7, Zhang discloses the claimed invention as set forth in claim 1. Zhang further discloses the plane comprises a first plane, the pad comprises a first pad (the pad 160), and the coil comprises a first coil (152), and further comprising a second pad (the pad connected to 154) in a second plane (the plane through 154) of the PCB with a second coil (154) around the second pad in the second plane of the PCB, wherein the first coil and the second coil are coiled in opposite radial directions (152 and 154 are opposite in the radial directions). Regarding claim 8, Zhang discloses a computer system, comprising: a host processor (a processor in the device, paragraph 17); and a memory module (paragraph 17) including multiple memory devices disposed on a printed circuit board (PCB, Fig. 3), the PCB including: a via (a via 110) including a barrel (a stub portion 130) through the PCB, the barrel electrically connected to a pad (a conductor cap 160) in a plane of the PCB; and a coil (the inductor path 152) around the pad in the plane of the PCB, the coil of conductor in the plane of the PCB, the coil electrically connected to the pad (the inductor 152 electrically connected to the pad 160, Fig. 2). Regarding claim 9, Zhang discloses the claimed invention as set forth in claim 8. Zhang further suggests the PCB further comprises an inner routing layer (layer having 154 if the word inner is inside the substrate, Fig. 2; otherwise, consider the routing layer 252 and 254, Fig. 4), wherein the plane (the plane through 154) comprises the inner routing layer. Regarding claim 10, Zhang discloses the claimed invention as set forth in claim 8. Zhang further suggests the plane comprises either a top layer of the PCB or a bottom layer of the PCB (consider the layer through 152 is a top or bottom layer). Regarding claim 12, Zhang discloses the claimed invention as set forth in claim 10. Zhang further discloses the pad comprises a first pad (160) and the coil comprises a first coil (152), wherein the first pad and the first coil are in the top layer of the PCB (Fig. 2), the PCB further comprising: an inner routing layer including a second pad (the pad connected to 154) in a plane (a plane through 154) of the inner routing layer, with a second coil (154) around the second pad in the inner routing layer. Regarding claim 13, Zhang discloses the claimed invention as set forth in claim 10. Zhang further discloses a first pad (160) and the coil comprises a first coil (152), wherein the first pad and the first coil are in the bottom layer of the PCB, the PCB further comprising: an inner routing layer (the layer through 154) including a second pad (the pad connected to 154) in a plane of the inner routing layer, with a second coil (154) around the second pad in the inner routing layer. Regarding claim 14, Zhang discloses the claimed invention as set forth in claim 8. Zhang further discloses the plane comprises a first plane, the pad comprises a first pad (the pad 160), and the coil comprises a first coil (152), and further comprising a second pad (the pad connected to 154) in a second plane (the plane through 154) of the PCB with a second coil (154) around the second pad in the second plane of the PCB, wherein the first coil and the second coil are coiled in opposite radial directions (152 and 154 are opposite in the radial directions). Regarding claim 15, Zhang discloses the claimed invention as set forth in claim 8. Zhang further suggests the host processor comprises a multicore processor (processors, paragraph 54); or the computer system further comprising: a display communicatively coupled to the host processor; or the computer system further comprising: a network interface communicatively coupled to the host processor (network chips, paragraph 54); or the computer system further comprising: a battery to power the computer system. Regarding claim 16, Zhang discloses a printed circuit board (PCB) comprising: multiple planes of routing layers (Fig. 2 & 3), including a top routing layer (top layer, Fig. 2 & 3), a bottom routing layer (bottom layer, Fig. 2 & 3), and an inner routing layer (inner routing layer through 154) between the top routing layer and the bottom routing layer; a via (120) including a barrel (130) through the top routing layer, the inner routing PCB, and the bottom routing layer, the barrel electrically connected to a pad (160) in a first plane of the multiple planes of routing layers; and a coil (152) around the pad in the first plane, the coil of conductor in the first plane, the coil electrically connected to the pad (Fig. 2). Regarding claim 17, Zhang discloses the claimed invention as set forth in claim 16. Zhang further suggests the first plane comprises the inner routing layer (plane through 154). Regarding claim 18, Zhang discloses the claimed invention as set forth in claim 16. Zhang further suggests the first plane comprises either the top routing layer or the bottom routing layer (the plane through either top or bottom layers, Fig. 2). Regarding claim 19, Zhang discloses the claimed invention as set forth in claim 18. Zhang further discloses the pad comprises a first pad (160) and the coil comprises a first coil (152), wherein the first pad and the first coil are in the top routing layer or the bottom routing layer, and further comprising a second pad (the pad connected to 154) in the inner routing layer with a second coil (154) around the second pad in the inner routing layer. Regarding claim 20, Zhang discloses the claimed invention as set forth in claim 16. Zhang further discloses the plane comprises a first plane, the pad comprises a first pad (the pad 160), and the coil comprises a first coil (152), and further comprising a second pad (the pad connected to 154) in a second plane (the plane through 154) of the PCB with a second coil (154) around the second pad in the second plane of the PCB, wherein the first coil and the second coil are coiled in opposite radial directions (152 and 154 are opposite in the radial directions). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 4, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20160276091), in view of Hu (US 20170110244). Regarding claim 4, Zhang discloses the claimed invention as set forth in claim 3. Zhang further suggests the pad comprises a first pad (160) and the coil comprises a first coil (152), wherein the first pad and the first coil are in the top layer of the PCB (Fig. 2). Zhang does not explicitly disclose a second pad in the bottom layer of the PCB with a second coil around the second pad in the bottom layer of the PCB. Hu suggests a second pad (121, Fig. 2) in the bottom layer of the PCB with a second coil (the inductor coil 11) around the second pad in the bottom layer of the PCB. It would have been obvious to one having skill in the art at the effective filing date of the invention to add more routing layers to the circuit board in order to increase the complexity of the circuitry and adding more function to the electronic device. Regarding claim 11, Zhang discloses the claimed invention as set forth in claim 10. Zhang further suggests the pad comprises a first pad (160) and the coil comprises a first coil (152), wherein the first pad and the first coil are in the top layer of the PCB (Fig. 2). Zhang does not explicitly disclose a second pad in the bottom layer of the PCB with a second coil around the second pad in the bottom layer of the PCB. Hu suggests a second pad (121, Fig. 2) in the bottom layer of the PCB with a second coil (the inductor coil 11) around the second pad in the bottom layer of the PCB. It would have been obvious to one having skill in the art at the effective filing date of the invention to add more routing layers to the circuit board in order to increase the complexity of the circuitry and adding more function to the electronic device. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Meyer (US 9888577) discloses an inductor connected to the inner pad, Fig. 14A. Li (US 20210352807) discloses an inductor connected to the inner pad, Fig. 4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BINH B TRAN/Primary Examiner, Art Unit 2848
Read full office action

Prosecution Timeline

Dec 23, 2022
Application Filed
Jun 28, 2023
Response after Non-Final Action
Feb 28, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
92%
With Interview (+12.4%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 680 resolved cases by this examiner. Grant probability derived from career allow rate.

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