Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 – 3, 7 – 10, 14 - 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20160276091), in view of Hu (US 20170110244).
Regarding claim 1, Zhang discloses an apparatus comprising:
a printed circuit board (PCB in Fig. 3);
a via (a via 110) including a barrel (a stub portion 130) through the PCB, the barrel electrically connected to a first pad (a conductor cap 160) in a first plane of the PCB; and
a first coil (the inductor path 152) around the first pad in the first plane of the PCB, the first coil of conductor in the plane of the PCB, the first coil electrically connected to the first pad (the inductor 152 electrically connected to the pad 160, Fig. 2);
a second pad (the pad connected to the inductor pad 154) in a second plane of the PCB (the plane through 154) with a second coil (the inductor path 154) curved around the second pad in the second plane of the PCB.
Zhang does not explicitly disclose the first coil and the second coil have overlapping patterning.
Hu teaches the first coil (the first inductance coil 11) and the second coil (the first conductive hole 23) have overlapping patterning (Figures 2 - 4).
It would have been obvious to one having skill in the art at the effective filing date of the invention to rearrange the position of the components in the circuit board in order to fit all the components of the intended circuitry into the limited space of the circuit substrate.
Regarding claim 2, Zhang discloses the claimed invention as set forth in claim 1. Zhang further discloses the PCB further comprises an inner routing layer (the layer containing the inductor 154, Fig. 2 or consider another inductor, in Fig. 3, to be in the same plane; or 254, Fig. 4), wherein the second plane comprises the inner routing layer.
Regarding claim 3, Zhang discloses the claimed invention as set forth in claim 1. Zhang further suggests the second plane comprises either a top layer (the top layer of the stack, Fig. 3) of the PCB or a bottom layer of the PCB.
Regarding claim 7, Zhang discloses the claimed invention as set forth in claim 1. Zhang further discloses wherein the first coil and the second coil are coiled in opposite radial directions (152 and 154 are opposite in the radial directions).
Regarding claim 8, Zhang discloses a computer system, comprising:
a host processor (a processor in the device, paragraph 17); and
a memory module (paragraph 17) including multiple memory devices disposed on a printed circuit board (PCB, Fig. 3),
the PCB including:
a via (a via 110) including a barrel (a stub portion 130) through the PCB, the barrel electrically connected to a first pad (a conductor cap 160) in a first plane of the PCB; and
a first coil (the inductor path 152) curved around the first pad in the first plane of the PCB, the first coil of conductor in the first plane of the PCB, the coil electrically connected to the first pad (the inductor 152 electrically connected to the pad 160, Fig. 2).
a second pad (the pad connected to the inductor pad 154) in a second plane of the PCB (the plane through 154) with a second coil (the inductor path 154) curved around the second pad in the second plane of the PCB.
Zhang does not explicitly disclose the first coil and the second coil have overlapping patterning.
Hu teaches the first coil (the first inductance coil 11) and the second coil (the first conductive hole 23) have overlapping patterning (Figures 2 - 4).
It would have been obvious to one having skill in the art at the effective filing date of the invention to rearrange the position of the components in the circuit board in order to fit all the components of the intended circuitry into the limited space of the circuit substrate.
Regarding claim 9, Zhang discloses the claimed invention as set forth in claim 8. Zhang further suggests the PCB further comprises an inner routing layer (layer having 154 if the word inner is inside the substrate, Fig. 2; otherwise, consider the routing layer 252 and 254, Fig. 4), wherein the second plane (the plane through 154) comprises the inner routing layer.
Regarding claim 10, Zhang discloses the claimed invention as set forth in claim 8. Zhang further suggests the second plane comprises either the other of the top layer of the PCB or the bottom layer of the PCB (consider the layer through 152 is a top or bottom layer).
Regarding claim 14, Zhang discloses the claimed invention as set forth in claim 8. Zhang further discloses wherein the first coil and the second coil are coiled in opposite radial directions (152 and 154 are opposite in the radial directions).
Regarding claim 15, Zhang discloses the claimed invention as set forth in claim 8. Zhang further suggests the host processor comprises a multicore processor (processors, paragraph 54); or the computer system further comprising: a display communicatively coupled to the host processor; or the computer system further comprising: a network interface communicatively coupled to the host processor (network chips, paragraph 54); or the computer system further comprising: a battery to power the computer system.
Regarding claim 16, Zhang discloses a printed circuit board (PCB) comprising:
multiple planes of routing layers (Fig. 2 & 3), including a top routing layer (top layer, Fig. 2 & 3), a bottom routing layer (bottom layer, Fig. 2 & 3), and an inner routing layer (inner routing layer through 154) between the top routing layer and the bottom routing layer;
a via (120) including a barrel (130) through the top routing layer, the inner routing PCB, and the bottom routing layer, the barrel electrically connected to a first pad (160) in a first plane of the multiple planes of routing layers, wherein the first plane is either the top routing layer or the bottom routing layer (Fig. 2); and
a first coil (152) around the first pad in the first plane, the first coil of conductor in the first plane, the coil electrically connected to the first pad (Fig. 2).
a second pad (the pad connected to the inductor pad 154) in a second plane of the PCB (the plane through 154) with a second coil (the inductor path 154) curved around the second pad in the second plane of the PCB.
Zhang does not explicitly disclose the first coil and the second coil have overlapping patterning.
Hu teaches the first coil (the first inductance coil 11) and the second coil (the first conductive hole 23) have overlapping patterning (Figures 2 - 4).
It would have been obvious to one having skill in the art at the effective filing date of the invention to rearrange the position of the components in the circuit board in order to fit all the components of the intended circuitry into the limited space of the circuit substrate.
Regarding claim 17, Zhang discloses the claimed invention as set forth in claim 16. Zhang further suggests the second plane comprises the inner routing layer (plane through 154).
Regarding claim 18, Zhang discloses the claimed invention as set forth in claim 16. Zhang further suggests the second plane comprises the other of top routing layer or the bottom routing layer (the plane through either top or bottom layers, Fig. 2).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Culp (US 20160007462 A1) discloses two parallel patterns overlapping each other.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BINH B TRAN/Primary Examiner, Art Unit 2847
Prosecution Insights