DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-9, and 11-20 is/are rejected under 35 U.S.C. 102(a)(2) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Sharma et al (US Pub 2023/0422485).
In re claim 1, Sharma et al discloses an integrated circuit structure (i.e. see at least Figure 3), comprising: a front side structure comprising: a GaN-based device layer (i.e. 306) (i.e. see at least paragraph 0142 disclosing the use of gallium nitride in the device); and one or more metallization layers (i.e. 308) above the GaN-based device layer; a backside structure (i.e. 302) below and coupled to the GaN-based layer, the backside structure including metal layers (i.e. BM0-BM3) and one or more alternating laterally-recessed metal insulator metal capacitors (i.e. 316B, MIM).
In the alternative, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the device layer 306 be gallium nitride based as gallium nitride is typically used in semiconductor devices along with the combination of what is disclosed in paragraph 0142.
In re claim 2, Sharma et al discloses wherein the GaN-based device layer is on a silicon layer of the front side structure (i.e. see at least paragraph 0073 disclosing an example of a silicon fin).
In re claim 3, Sharma et al discloses wherein the backside structure is coupled to the GaN-based layer by one or more through-silicon vias (i.e. 1312).
In re claim 5, Sharma et al discloses an integrated circuit structure (i.e. see at least Figure 3), comprising: a front side structure comprising: a GaN-based device layer (i.e. 306) (i.e. see at least paragraph 0142 disclosing the use of gallium nitride in the device); one or more silicon-based transistors (i.e. FETs) (i.e. see at least paragraph 0073 disclosing an example of a silicon fin); one or more metallization layers (i.e. 308) above the GaN-based device layer and the one or more silicon-based transistors; a backside structure (i.e. 302) below and coupled to the GaN-based layer and the one or more silicon-based transistors, the backside structure including metal layers (i.e. BM0-BM3) and one or more alternating laterally-recessed metal insulator metal capacitors (i.e. 316B, MIM).
In the alternative, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the device layer 306 be gallium nitride based as gallium nitride is typically used in semiconductor devices along with the combination of what is disclosed in paragraph 0142.
In re claim 6, Sharma et al discloses wherein the one or more silicon-based transistors are one or more fin-based transistors (i.e. see at least paragraph 0046).
In re claim 7, Sharma et al discloses wherein the one or more silicon-based transistors are one or more nano-wire-based transistors (i.e. see at least paragraph 0046).
In re claim 8, Sharma et al discloses wherein the GaN-based device layer is on a silicon layer of the front side structure (i.e. see at least paragraph 0068).
In re claim 9, Sharma et al discloses wherein the backside structure is coupled to the GaN-based layer by one or more through-silicon vias (i.e. 1312).
In re claim 11, Sharma et al discloses (i.e. see at least Figures 3 and 12) a computing device (i.e. 1200), comprising: a board (i.e. 1202); and a component (i.e. see at least paragraph 0144 disclosing a number of components) coupled to the board, the component including an integrated circuit structure (i.e. 300), comprising: a front side structure comprising: a GaN-based device layer (i.e. 306) (i.e. see at least paragraph 0142 disclosing the use of gallium nitride in the device); and one or more metallization layers (i.e. 308) above the GaN-based device layer; a backside structure (i.e. 302) below and coupled to the GaN-based layer, the backside structure including metal layers (i.e. BM0-BM3) and one or more alternating laterally-recessed metal insulator metal capacitors (i.e. 316B, MIM).
In the alternative, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the device layer 306 be gallium nitride based as gallium nitride is typically used in semiconductor devices along with the combination of what is disclosed in paragraph 0142.
In re claim 12, Sharma et al discloses a memory coupled to the board (i.e. see at least paragraph 0145).
In re claim 13, Sharma et al discloses a communication chip (i.e. 1206) coupled to the board (i.e. see at least paragraph 0144).
In re claim 14, Sharma et al discloses wherein the component is a packaged integrated circuit die (i.e. see at least paragraph 0147).
In re claim 15, Sharma et al discloses wherein the component is at least a processor (i.e. 1204) (i.e. see at least paragraph 0144).
In re claim 16, Sharma et al discloses (i.e. see at least Figures 3 and 12) a computing device (i.e. 1200), comprising: a board (i.e. 1202); and a component (i.e. see at least paragraph 0144 disclosing a number of components) coupled to the board, the component including an integrated circuit structure (i.e. 300), comprising: a front side structure comprising: a GaN-based device layer (i.e. 306) (i.e. see at least paragraph 0142 disclosing the use of gallium nitride in the device); one or more silicon-based transistors (i.e. FETs) (i.e. see at least paragraph 0073 disclosing an example of a silicon fin); one or more metallization layers (i.e. 308) above the GaN-based device layer and the one or more silicon-based transistors; a backside structure (i.e. 302) below and coupled to the GaN-based layer and the one or more silicon-based transistors, the backside structure including metal layers (i.e. BM0-BM3) and one or more alternating laterally-recessed metal insulator metal capacitors (i.e. 316B, MIM).
In the alternative, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the device layer 306 be gallium nitride based as gallium nitride is typically used in semiconductor devices along with the combination of what is disclosed in paragraph 0142.
In re claim 17, Sharma et al discloses a memory coupled to the board (i.e. see at least paragraph 0145).
In re claim 18, Sharma et al discloses a communication chip (i.e. 1206) coupled to the board (i.e. see at least paragraph 0144).
In re claim 19, Sharma et al discloses wherein the component is a packaged integrated circuit die (i.e. see at least paragraph 0147).
In re claim 20, Sharma et al discloses wherein the component is at least a processor (i.e. 1204) (i.e. see at least paragraph 0144).
Allowable Subject Matter
Claims 4 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY HO whose telephone number is (571)270-1432. The examiner can normally be reached 9AM - 5PM, Monday-Friday.
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/ANTHONY HO/Primary Examiner, Art Unit 2817
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