DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, and 5-13,15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tabe (US-20130157729-A1; Tabe) in view of in view of Makabe (US-20190027577-A1; Makabe) and further in view of Suda et al. (US-20090072243-A1; Suda).
Regarding claim 1, Tabe discloses an integrated circuit structure (Fig. 1/13,400; ¶88/116), comprising: a substrate comprising silicon (Fig. 1/13,712; ¶88/116); but is silent on a layer comprising silicon and carbon above the substrate, the layer comprising silicon and carbon having a top surface with a silicon face; and a layer comprising gallium and nitrogen on …the layer comprising silicon and carbon, the layer comprising gallium and nitrogen having a gallium-polar orientation with a top crystal plane consisting of a gallium face.
Tabe discloses an integrated circuit structure comprising a GaN-HEMT device on a silicon substrate (¶116), but is silent on how the GaN-HEMT is configured.
Makabe discloses an GaN-HEMT device comprising silicon and carbon (Fig. 7A,110; ¶39-40) that would be above the substrate, the layer comprising silicon and carbon having a top surface with a silicon face (¶39); a layer comprising gallium and nitrogen (Fig. 7A, 112; ¶39-40) on the layer comprising silicon and carbon, the layer comprising gallium and nitrogen having a gallium-polar orientation with a top crystal plane consisting of a gallium face.
Tabe and Makabe are silent on the layer comprising gallium and nitrogen on and in direct physical contact with the layer comprising silicon and carbon.
Suda discloses an HEMT device where the Ga-polar GaN layer (Fig. 4e, 17; ¶ 47) is in direct physical contact with the SiC layer (Fig. 4e, 1; ¶ 47) without an intervening buffer layer.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use a Ga-polar/Si-face HEMT configuration for making a high efficiency HEMT device in communication device; for removing the AlN buffer layer to achieve a different threshold voltage..
Regarding claim 2, Tabe in view of Makabe and Suda discloses the integrated circuit structure of claim 1, wherein the layer comprising gallium and nitrogen is a Ga-polar GaN layer. (Fig. 7A, 112; ¶39-40 Makabe)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use a Ga-polar/Si-face HEMT configuration for making a high efficiency HEMT device in communication device.
Regarding claim 3, Tabe in view of Makabe and Suda discloses the integrated circuit structure of claim 1, wherein the layer comprising silicon and carbon is a Si-face SiC layer. (Fig. 7A,110; ¶39-40 Makabe)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use a Ga-polar/Si-face HEMT configuration for making a high efficiency HEMT device in communication device.
Regarding claim 5, Tabe in view of Makabe and Suda discloses the integrated circuit structure of claim 1, further comprising a Ga-polar GaN transistor (Fig. 7A,2A; ¶38-40 Makabe) in or on the Ga-polar GaN layer. (Fig. 7A,112; ¶39-40 Makabe)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use a Ga-polar/Si-face HEMT configuration for making a high efficiency HEMT device in communication device.
Regarding claim 6, Tabe discloses a computing device (Fig. 1/13,400; ¶88/116), comprising: a board (Fig. 13, not labeled motherboard of mobile device 400; ¶88/116); and a component (Fig. 1/13,detection platform 706; ¶88/116) coupled to the board, the component including an integrated circuit structure (Fig. 1/13, CMOS antenna circuit; ¶88/116) , comprising: a substrate comprising silicon (Fig. 1/13, 712; ¶88/116) ; but is silent on a layer comprising silicon and carbon above the substrate, the layer comprising silicon and carbon having a top surface with a silicon face; a layer comprising gallium and nitrogen on the layer comprising silicon and carbon, the layer comprising gallium and nitrogen having a gallium-polar orientation with a top crystal plane consisting of a gallium face.
Tabe discloses an integrated circuit structure comprising a GaN-HEMT device on a silicon substrate (¶116), but is silent on how the GaN-HEMT is configured.
Makabe discloses an GaN-HEMT device comprising silicon and carbon (Fig. 7A,110; ¶39-40) that would be above the substrate, the layer comprising silicon and carbon having a top surface with a silicon face (¶39); a layer comprising gallium and nitrogen (Fig. 7A, 112; ¶39-40) on the layer comprising silicon and carbon, the layer comprising gallium and nitrogen having a gallium-polar orientation with a top crystal plane consisting of a gallium face.
Tabe and Makabe are silent on the layer comprising gallium and nitrogen on and in direct physical contact with the layer comprising silicon and carbon.
Suda discloses an HEMT device where the Ga-polar GaN layer (Fig. 4e, 17; ¶ 47) is in direct physical contact with the SiC layer (Fig. 4e, 1; ¶ 47) without an intervening buffer layer.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use a Ga-polar/Si-face HEMT configuration for making a high efficiency HEMT device in communication device; for removing the AlN buffer layer to achieve a different threshold voltage..
Regarding claim 7, Tabe in view of Makabe and Suda discloses the computing device of claim 6, further comprising: a memory (not shown) coupled to the board. (Fig. 1, motherboard of 400; ¶88 Tabe)
All mobile phones have memory connected to a mother board.
Regarding claim 8, Tabe in view of Makabe and Suda discloses the computing device of claim 6, further comprising: a communication chip (Fig. 1, not shown;¶88 Tabe) coupled to the board. (Fig. 1, motherboard of 400; ¶88 Tabe)
All mobile phones have a communication chip connected to a main board.
Regarding claim 9, Tabe in view of Makabe and Suda discloses the computing device of claim 6, further comprising: a camera (Fig. 1/8, 404; ¶88,108 Tabe) coupled to the board. (Fig. 1, motherboard of 400; ¶88 Tabe)
Regarding claim 10, Tabe in view of Makabe and Suda discloses the computing device of claim 6, wherein the component is a packaged (packaged in 400; Tabe) integrated circuit die. (Fig. 1/13, CMOS; ¶15, 88,116 Tabe)
Regarding claim 11, Tabe discloses an integrated circuit structure (Fig. 1/13,400; ¶88/116), comprising: a substrate (Fig. 1/13,712; ¶88/116) comprising silicon; but is silent on a layer comprising silicon and carbon above the substrate, the layer comprising silicon and carbon having a top surface with a carbon face; a layer comprising gallium and nitrogen on the layer comprising silicon and carbon, the layer comprising gallium and nitrogen having a nitrogen-polar orientation with a top crystal plane consisting of a nitrogen face.
Tabe discloses an integrated circuit structure comprising a GaN-HEMT device on a silicon substrate (¶116), but is silent on how the GaN-HEMT is configured.
Makabe discloses an GaN-HEMT device comprising silicon and carbon (Fig. 7B,120; ¶39-40) that would be above the substrate, the layer comprising silicon and carbon having a top surface with a carbon face (¶40); a layer comprising gallium and nitrogen (Fig. 7B, 122; ¶39-40) on the layer comprising silicon and carbon, the layer comprising gallium and nitrogen having a nitrogen-polar orientation with a top crystal plane consisting of a nitrogen face.
Tabe and Makabe are silent on the layer comprising gallium and nitrogen on and in direct physical contact with the layer comprising silicon and carbon.
Suda discloses an HEMT device where the N-polar GaN layer (Fig. 4e, 17a; ¶ 47) is in direct physical contact with the SiC layer (Fig. 4e, 1a; ¶ 47) without an intervening buffer layer.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use a N-polar/C-face HEMT configuration for making an improving linear-saturation characteristics of the transistor and reduce the drain conductance as compared to Ga-polar/Si-face configurations; for removing the AlN buffer layer to achieve a different threshold voltage.
Regarding claim 12, Tabe in view of Makabe and Suda discloses the integrated circuit structure of claim 11, wherein the layer comprising gallium and nitrogen is an N-polar GaN layer. (Fig. 7B, 122; ¶39-40)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use a N-polar/C-face HEMT configuration for making an improving linear-saturation characteristics of the transistor and reduce the drain conductance as compared to Ga-polar/Si-face configurations.
Regarding claim 13, Tabe in view of Makabe and Suda discloses the integrated circuit structure of claim 11, wherein the layer comprising silicon and carbon is a C-face SiC layer. (Fig. 7B,120; ¶39-40)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use a N-polar/C-face HEMT configuration for making an improving linear-saturation characteristics of the transistor and reduce the drain conductance as compared to Ga-polar/Si-face configurations.14. The integrated circuit structure of claim I1, further comprising an amorphous silicon layer or a polycrystalline silicon layer between the substrate and the layer comprising silicon and carbon.
Regarding claim 15, Tabe in view of Makabe and Suda discloses the integrated circuit structure of claim 11, further comprising an N-polar GaN transistor (Fig. 5B, 2A; ¶39-40 Makabe) in or on the N-polar GaN layer. (Fig. 7B,112; ¶39-40 Makabe)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use a N-polar/C-face HEMT configuration for making an improving linear-saturation characteristics of the transistor and reduce the drain conductance as compared to Ga-polar/Si-face configurations.
Regarding claim 16, Tabe discloses a computing device, comprising: a board (Fig. 13, not labeled motherboard of mobile device 400; ¶88/116); and a component (Fig. 1/13,detection platform 706; ¶88/116)coupled to the board, the component including an integrated circuit structure (Fig. 1/13, CMOS antenna circuit; ¶88/116), comprising: a substrate comprising silicon (Fig. 1/13, 712; ¶88/116); but is silent on a layer comprising silicon and carbon above the substrate, the layer comprising silicon and carbon having a top surface with a carbon face; a layer comprising gallium and nitrogen on the layer comprising silicon and carbon, the layer comprising gallium and nitrogen having a nitrogen-polar orientation with a top crystal plane consisting of a nitrogen face.
Tabe discloses an integrated circuit structure comprising a GaN-HEMT device on a silicon substrate (¶116), but is silent on how the GaN-HEMT is configured.
Makabe discloses an GaN-HEMT device comprising silicon and carbon (Fig. 7B,120; ¶39-40) that would be above the substrate, the layer comprising silicon and carbon having a top surface with a carbon face (¶40); a layer comprising gallium and nitrogen (Fig. 7B, 122; ¶39-40) on the layer comprising silicon and carbon, the layer comprising gallium and nitrogen having a nitrogen-polar orientation with a top crystal plane consisting of a nitrogen face.
Tabe and Makabe are silent on the layer comprising gallium and nitrogen on and in direct physical contact with the layer comprising silicon and carbon.
Suda discloses an HEMT device where the N-polar GaN layer (Fig. 4e, 17a; ¶ 47) is in direct physical contact with the SiC layer (Fig. 4e, 1a; ¶ 47) without an intervening buffer layer.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use a N-polar/C-face HEMT configuration for making an improving linear-saturation characteristics of the transistor and reduce the drain conductance as compared to Ga-polar/Si-face configurations; for removing the AlN buffer layer to achieve a different threshold voltage.
Regarding claim 17, Tabe in view of Makabe and Suda discloses the computing device of claim 16, further comprising: a memory (not shown) coupled to the board. (Fig. 1, motherboard of 400; ¶88 Tabe)
All mobile phones have memory connected to a motherboard.
Regarding claim 18, Tabe in view of Makabe and Suda discloses the computing device of claim 16, further comprising: a communication chip (Fig. 1, not shown;¶88 Tabe) coupled to the board. (Fig. 1, motherboard of 400; ¶88 Tabe)
All mobile phones have a communication chip connected to a main board.
Regarding claim 19, Tabe in view of Makabe and Suda discloses the computing device of claim 16, further comprising: a camera (Fig. 1/8, 404; ¶88,108 Tabe) coupled to the board. (Fig. 1, motherboard of 400; ¶88 Tabe)
Regarding claim 20, Tabe in view of Makabe and Suda discloses the computing device of claim 16, wherein the component is a packaged (packaged in 400; Tabe) integrated circuit die. (Fig. 1/13, CMOS; ¶15, 88,116 Tabe)
Allowable Subject Matter
Claims 4 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
The relevant art (JP-2020513681-A) discloses an amorphous silicon layer between a temporary Aluminum nitride substrate and a silicon carbide layer. The amorphous silicon layer is removed in the process of removing the AlN layer for attaching the permanent substrate to the GaN layer. The art is silent on the limitations cited below in combination with the rest of the claimed limitations.
Regarding claim 4, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " an amorphous silicon layer or a polycrystalline silicon layer between the substrate and the layer comprising silicon and carbon. ”, as recited in Claim 4, with the remaining features.
Regarding claim 14, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " an amorphous silicon layer or a polycrystalline silicon layer between the substrate and the layer comprising silicon and carbon. ”, as recited in Claim 14, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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