DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 5-7, 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Block (US 20200035560), hereinafter Block.
Regarding claims 1 and 5-7, Block (US 20200035560) (refer to Figure 3i) teaches an integrated circuit structure, comprising:
a front side structure comprising:
a device layer (215, described as “device layer 215” in para 150); and
a plurality of metallization layers (333, described as “Front-side interconnect metallization 333” in para 150; see Figure 3i) above the device layer (215);
a backside structure (334, described as “Back-side interconnect metallization 334” in para 150; see Figure 3i) below and coupled to (para 150) the device layer (215), the backside structure including metal lines (321, described as “plurality of interconnect metallization levels 321 embedded within inter-layer dielectric” which is included in 334 – see para 150) and is capable of power delivery and signal routing to the device layer (215).
The embodiment of Figure 3i of Block does not specifically show that the device layer (251) has the specific recited devices; i.e. the device layer comprises “a dynamic random access memory (DRAM) layer having one or more capacitors” over one or more “transistors” and as such, also does not teach that the backside structure is coupled specifically to “transistors of the DRAM layer” of the device layer (215) for delivery of power and signal routing, wherein the transistors of the DRAM layer are “planar transistors” (as required for claim 1), OR are “non-planar-based transistors” (as required for claim 5); further wherein the one or more non-planar-based transistors of the DRAM layer are one or more a). “fin-based transistors” (as recited in claim 6); OR b). “nanowire-based transistors” (as recited in claim 7).
However, Block contemplates device layer comprising a DRAM layer including DRAM capacitor structures and transistors (see para 361 that describes “first device stratum including DRAM capacitor structures while the second device stratum includes access transistor structures”; also see para 338), and also discloses that although methods are disclosed for non-planar transistors such as fin-based transistors (see “finFETs” example in para 150) or such as nanowire transistors (see “nanowire transistor” example of para 185 and 198), the same are applicable to planar transistor structures (para 165, especially last sentence; also see para 234). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Block so that the device layer comprises a dynamic random access memory (DRAM) layer having one or more capacitors over one or more transistors, and the backside structure is coupled specifically to the transistors of the DRAM layer for delivery of power and signal routing; and still further that the transistors of the DRAM layer are “planar transistors” (as required for claim 1), OR are “non-planar-based transistors” (as required for claim 5), further wherein the one or more non-planar-based transistors of the DRAM layer are one or more a). “fin-based transistors” (as recited in claim 6); OR b). “nanowire-based transistors” (as recited in claim 7).
The ordinary artisan would have been motivated to modify Block for at least the purpose of routing power and signals to access transistors of DRAM layer (para 361 of Block), with either the use of planar transistors (para 338 of Block), which enables fewer masking and etching steps for specific geometries compared to non-planar transistors, thus simplifying manufacturing; or with non-planar-based transistors (para 361 of Block) such as finFETs which are a mature technology that gives better control on electrical properties than planar transistors or using nanowire transistors that facilitate smaller devices with channel region fully depleted (para 198 of Block, especially last sentence).
Regarding claims 11 and 16 (and their dependent claims 12-15 and 17-20), the following teachings of Block are noted and will be referenced in the rejections below: Block (refer to Figure 81 and 3i) teaches the following: a computing device (8105, such as "a smart phone, laptop computer" – see para 425) may include a system (such as “a chip-level or package-level integrated circuit 8110” – see para 425). Further, “disposed withing the integrated system 8110” may further be a sub-system (8150, described as "monolithic SoC 8150” in para 426); and 8150 may further include “a memory block” such as “RAM" (para 426, 1st sentence) and “a microprocessor” (para 426, 1st sentence) . Still further, para 426 describes “The monolithic SoC 8150 may be further coupled to a board, a substrate, or an interposer 8160 along with, one or more of a power management integrated circuit (PMIC) 8130, RF (wireless) integrated circuit (RFIC) 8125 including a wideband RF (wireless) transmitter and/or receiver (TX/RX)” – emphasis added by bold/underlined text. Still further, para 426 describes “The monolithic SoC 8150” also includes “at least one device stratum including front-side structures that have been revealed from the back side, for example as described elsewhere herein”, such as the structure of Figure 3i. Further note that the “integrated circuit structure” recited in claim 11 is substantially the same as that of claim 1, while the “integrated circuit structure” recited in claim 16 is substantially the same as that of claim 6, and as such, they have already been addressed in rejections of claims 1 and 5, respectively.
Based on the above described teachings of Block in context of claims 11 and 16, it is clear that Block (refer to Figure 81 and 3i) teaches the limitations recited in claims 11 and 16 by teaching a computing device (8105, such as "a smart phone, laptop computer" described above), comprising:
a board (described above as “a board” to which 8150 is coupled); and
a component (8150 described above) coupled to (described above) the board,
the component including an integrated circuit structure, comprising: either the integrated circuit structure of claim 1 that has already been addressed (for claim 11), or the integrated circuit structure of claim 5 which has also already been addressed (for claim 16).
Regarding claims 12 and 17, Block teaches the computing device of claim 11 and 16, further comprising: a memory coupled to the board (as described above, 8150 may further include “a memory block” such as “RAM" and may be coupled to a board; also see para 426).
Regarding claims 13 and 18, Block teaches the computing device of claim 11 and 16, further comprising: a communication chip [such as RF (wireless) integrated circuit (RFIC) 8125 including a wideband RF (wireless) transmitter and/or receiver (TX/RX) described above; also see para 426] coupled to the board.
Regarding claims 14 and 19, Block teaches the computing device of claim 11 and 16, wherein the component (8150) is a packaged integrated circuit die (as described above, “The monolithic SoC 8150” also includes “at least one device stratum including front-side structures that have been revealed from the back side, for example as described elsewhere herein”, such as the structure of Figure 3i; also see para 426).
Regarding claims 15 and 20, Block teaches the computing device of claim 11 and 16, wherein the component (8150) is selected from the group consisting of a processor, a communications chip, and a digital signal processor (as described above, 8150 may further include “a memory block” such as “RAM" (para 426, 1st sentence) and “a microprocessor”; also see para 426)
Claims 2, 3, 8, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Block in view of Liaw (US 20240040763), hereinafter Liaw.
Regarding claims 2, 3, 8 and 9, Block (refer to Figure 3i) teaches the integrated circuit structure of claim 1 and 5, but does not teach wherein “a read path for the DRAM layer is included in the plurality of metallization layers of the front side structure” (as recited in claim 2 and also in claim 8); OR wherein (as recited in claim 3, and also in claim 9) “a write path for the DRAM layer is included in the backside structure”.
Liaw (US 20240040763) teaches that in integrated circuit which may comprise memory such as DRAM (para 29), it is known that “Some of the metal conductors such as read bit-line conductors are fabricated on the front-side of the structure” and “Other metal conductors such as write bit-line conductor and write bit-line-bar (also referred to as complementary bit-line) conductor are fabricated on the back-side of the structure” (para 27).
It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Block so that “a read path for the DRAM layer is included in the plurality of metallization layers of the front side structure” (as recited in claim 2 and 8); OR wherein (as recited in claim 3 and 9) “a write path for the DRAM layer is included in the backside structure”. The ordinary artisan would have been motivated to modify Block for at least the purpose of improving device performance, such as by making write bit-line conductor and write bit-line-bar conductor wider than those metal conductors at the front-side, thereby reducing the resistance (para 27 of Liaw) and also making them more suitable for power delivery (para 182 of Block).
Claims 4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Block in view of Malhotra (US 20140187018), hereinafter Malhotra.
Regarding claims 4 and 10, Block (refer to Figure 3i) teaches the integrated circuit structure of claim 1 or 5, but does not teach wherein “the one or more capacitors of the DRAM layer are non-planar metal insulator metal capacitors” (as recited in each of claims 4 and 10).
Malhotra (US 20140187018) teaches an integrated circuit structure comprising DRAM layer with one or more capacitors in the DRAM layer (para 2), further teaching that use of metal insulator capacitors for higher performance are known in the art (para 5, especially last sentence), and that the capacitors may be planar or non-planar.
It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Block so that the one or more capacitors of the DRAM layer are non-planar metal insulator metal capacitors. The ordinary artisan would have been motivated to modify Block for at least the purpose of achieving known advantage of MIM capacitors such as fast device speeds (para 6 of Malhotra), with non-planar morphologies giving more varied design choices for achieving target electrical parameters.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AJAY ARORA whose telephone number is (571)272-8347. The examiner can normally be reached 9 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Drew Richards can be reached at 5712721736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AJAY ARORA/Primary Examiner, Art Unit 2892